数字校准信号输出电路、方法、芯片及电子设备
By sampling and processing the clock signal inside the chip to obtain the time difference and output a digital signal, the problem of low clock signal calibration efficiency caused by the lack of a frequency multiplier circuit is solved, and higher clock signal accuracy is achieved.
CN120469541BActive Publication Date: 2026-07-17CHIPSEA TECH SHENZHEN CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHIPSEA TECH SHENZHEN CO LTD
- Filing Date
- 2025-03-31
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In the existing technology, the lack of a frequency multiplier circuit inside the chip results in low clock signal calibration efficiency, which affects the accuracy of the clock signal.
Method used
By setting the first processing module to sample the clock signal and obtain the time difference, and using the second processing module to output a digital signal based on the time difference and the clock signal frequency, digital calibration without frequency doubling is achieved.
Benefits of technology
It improves the efficiency and accuracy of real-time clock signal calibration, especially in chips without frequency multiplier circuits.
✦ Generated by Eureka AI based on patent content.
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Abstract
本申请涉及集成电路技术领域，尤其涉及一种数字校准信号输出电路、方法、芯片及电子设备，通过设置第一处理模块，对第一时钟信号进行采样，根据采样结果获取第一时间差；通过设置第二处理模块，根据所述第一时间差以及所述第一时钟信号的第一频率输出第一数字信号；无需对第一时钟信号进行倍频操作，在未设置倍频电路的芯片内部实现了根据第一时钟信号输出第一数字信号，有利于提高第一时钟信号的实时校准效率，从而提高第一时钟信号的精度。
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