A numerical comparator, a B2S converter, and a random computing integrated circuit.

Abstract

This invention discloses a numerical comparator, comprising a memory cell array. The memory cells of the array are connected via word lines and bit lines to form an array. A first number to be compared is sequentially stored in memory cells on different word lines of the same bit line, in bit order. These different word lines on the same bit line form a first word line group. A second number to be compared is sequentially stored in memory cells on the complementary bit line corresponding to the first word line, in bit order, on word lines that are different from any word line in the first word line group. These word lines that are different from any word line in the first word line group form a second word line group. The bit lines and complementary bit lines are connected to the input terminal of a sensing amplifier corresponding to the bit line. The memory cell is a DRAM memory cell. The first and second numbers are binary numbers.

Description

Technical Field

[0001] This disclosure belongs to the field of integrated circuit technology, and specifically relates to a DRAM-based in-memory computing numerical comparator, a B2S converter, a random computing integrated circuit, and its design method. Background Technology

[0002] General Matrix-Vector Multiplication (GEMV) is a core operation in many computational workloads, encompassing scientific computing, machine learning, and large language models (LLMs). In high-performance computing, GEMV is a critical computationally intensive operation, often used to optimize the performance of matrix operations. For example, implementing efficient matrix-vector multiplication on GPUs or multi-core CPUs can accelerate scientific computing and engineering applications.

[0003] However, GEMV is still essentially limited by memory and is often constrained by data transfer bottlenecks and memory access latency. In-memory processing (PIM) aims to alleviate these problems by integrating computation directly into the memory array and reducing high-energy data transfer. Dynamic random access memory (DRAM) has become a hot topic for developing DRAM-based in-memory processing (DRAM-PIM) architectures due to its maturity, scalability and high storage density. Although known prototypes such as Samsung's FIMDRAM[7], Hynix's AiM[8], and UPMEM[6] have demonstrated progress in this field, the DRAM-PIM architecture itself still has limitations, especially in terms of computational performance. For example, in DRISA[5], multiplication operations take up to 1600 nanoseconds, which limits its application in computationally intensive tasks.

[0004] To address this issue, Samsung attempted to introduce random computing (SC) into DRAM-based in-memory processing (DRAM-PIM), resulting in a peak performance increase of up to 4x.

[0005] However, despite the immense potential of integrating SC with DRAM, existing research has primarily focused on optimizing random operations such as random multiplication, neglecting a crucial component: the random number generator (SNG), which typically occupies 90% of the area in the entire SC system. Current implementations often place the SNG (B2S module) near memory rather than in memory, leading to increased area overhead and additional data handling. This placement diminishes the advantages of PIM, as the external location of the SNG negates the benefits of reduced data transfer and power consumption. The core challenge lies in the lack of efficient in-memory SNG designs, which limits the full potential of SC in DRAM-PIM-based systems.

[0006] To address this limitation, this disclosure proposes a novel approach to directly integrate the SNG (Signal Generation Unit) into the DRAM, eliminating the need for an external SNG module. Specifically, we focus on a key component within the SNG—the binary digital comparator (CNC). Unlike existing methods that typically require hardware modifications, this design leverages the inherent characteristics of the DRAM, such as capacitor charge / discharge and sensing amplifiers (SAs), to efficiently implement these functions without modifying the DRAM's own circuitry or adding any additional circuitry. This approach not only reduces area overhead but also minimizes data movement, thereby improving the overall accuracy and efficiency of the in-memory SNG. Summary of the Invention

[0007] One embodiment of this disclosure provides a numerical comparator, which includes a DRAM memory cell array. The memory cells of the memory cell array are connected via word lines and bit lines to form an array.

[0008] The first number to be compared is stored in the storage units of different word lines on the same bit line in bit order, and the different word lines on the same bit line form the first word line group.

[0009] The second number involved in the comparison is stored in bit order on the same complementary bit line (BLB) corresponding to the bit line (BL), in the storage unit of the word line that is different from any word line in the first word line group. The word lines that are different from any word line in the first word line group form the second word line group.

[0010] The bit line and the complementary bit line are connected to the input terminal of the sensing amplifier corresponding to the bit line.

[0011] One embodiment of this disclosure is a B2S converter (SNG) including the aforementioned numerical comparator, wherein the first number is an input binary number and the second number is a converted random number.

[0012] This disclosure addresses the high area overhead and frequent data movement issues of B2S modules in existing DRAM-PIM architectures. By implementing B2S functionality entirely within the DRAM core array, external comparator and random number generator modules are eliminated, thereby significantly reducing hardware costs, decreasing data transmission, and improving the energy efficiency and performance of in-memory computing. Attached Figure Description

[0013] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0014] Figure 1 A schematic diagram of the three basic modules of existing random computation (SC).

[0015] Figure 2 A schematic diagram comparing the present disclosure with existing random computation and DRAM-PIM architectures, based on one embodiment of the present disclosure.

[0016] Figure 3 A schematic diagram comparing the chip area ratio of this disclosure with existing circuit designs, based on one embodiment of this disclosure.

[0017] Figure 4 A schematic diagram comparing the latency of different design architectures under different GEMV dimensions according to one of the embodiments of this disclosure.

[0018] Figure 5 A schematic diagram of a B2S conversion circuit according to one embodiment of the present disclosure.

[0019] Figure 6 is a schematic diagram comparing the SPICE simulation results of the sense amplifier (SA) performance under different bit line configurations according to one of the embodiments of this disclosure. Detailed Implementation

[0020] In the existing in-memory computing (PIM) architecture based on dynamic random access memory (DRAM), the binary-to-random number (B2S) conversion module is the core component for realizing stochastic computing (SC).

[0021] Figure 1 is an overview of random computation (SC): (a) binary to random (B2S) conversion, (b) computation process including AND-based multiplication (MUL) and multiplexer-based addition (ADD), and (c) random to binary (S2B) conversion. Figure 1 This diagram illustrates a binary-to-random (B2S) conversion module in randomized computation (SC). A traditional B2S module typically consists of a random number generator (RNS) and a comparator. The comparator requires dedicated logic circuitry, such as a CMOS comparator or a lookup table, to compare the binary value with the random number, thereby generating a random bitstream. The English terms used in the diagram are explained below:

[0022] 1. Random number source (RNS) – Generates a string of random numbers (shown in binary form in the diagram) to be compared with a given binary number.

[0023] 2. Binary number – A binary number that is compared with a random number generated by a random number generator.

[0024] 3. Comparator (R vs. B) – Receives a random number (R) from a random number generator and a specific binary number (B). Its function is to compare these two numbers and generate an output signal (S) based on the comparison result. It converts 3-bit binary data into a random bitstream of length 2. 3 Taking 8 bits as an example: The comparator's truth table shows the output under different comparison conditions: If the random number R is less than the binary number B (e.g., R=001, B=100), the output S is 1. If the random number R is greater than or equal to the binary number B (e.g., R=111, B=100), the output S is 0. This comparison process is a crucial step in the random number generator's production of random bitstream data.

[0025] 4. Stochastic number / stochastic bit stream – This is the output of the comparator, represented as a "random number," and is a result where the probability of containing a "1" is represented. For example, "1011 0010" represents "4 / 8," and "0000 1111" also represents "4 / 8," regardless of the position of the "1." Another example is "0011 1100 00001111," which represents "8 / 16." This data reflects the result of comparing the random number with a given binary number.

[0026] 5. AND-based Multiplication (MUL) – “MUL” is an abbreviation for “Multiplication”.

[0027] 6. Addition operation based on multiplexer (MUX) (ADD) — ADD means "addition operation", and "MUX" is an abbreviation for "multiplexer".

[0028] 7. Stochastic-to-Binary (S2B) Conversion – “S2B” is an abbreviation for “Stochastic-to-Binary”, which means “random-to-binary conversion”, converting the random result generated by random computation into a deterministic binary number.

[0029] Figure 1Multiplication based on AND gates (MUL) is a method for implementing multiplication in random computation, that is, using AND gates to perform random multiplication. Addition based on multiplexers (ADD) uses multiplexers (MUX) to implement random addition. Random-to-binary (S2B) conversion refers to the process of converting the random result generated by random computation back into a binary number.

[0030] Figure 1 The B2S module shown is a key component in random computation, generating a random bit stream by comparing randomly generated numbers with predetermined binary numbers. The entire random computation process also includes random-to-binary conversion and complex computational operations based on these random bit streams.

[0031] Furthermore, the existing SCOPE architecture deploys the B2S module in the near-memory region near the DRAM memory cells, such as... Figure 2 As shown in (a). Figure 2 The random computing architecture is: (a) the SCOPE architecture [3] with a binary-to-random (B2S) module and a random-to-binary (S2B) module located near the memory bank; and (b) the proposed design that embeds the binary-to-random (B2S) module and random adder into the dynamic random access memory (DRAM) bank. Figure 2 The English terms in the text include:

[0032] DRAM - Dynamic Random Access Memory

[0033] Bank — Storage

[0034] SA—Sensing Amplifier

[0035] Binary ADD — Binary addition

[0036] Stochastic MUL - Random Multiplication

[0037] B2S - Binary to Random Number Conversion

[0038] S2B - Random Number to Binary Conversion

[0039] Near Bank Hardware – Near Bank Hardware

[0040] data_in — Input data

[0041] data_out — Output data

[0042] Stochastic ADD — Random Addition

[0043] Shifter

[0044] Figure 2 This includes the location and integration method of the binary-to-random (B2S) module and the random-to-binary (S2B) module in the random computing architecture design scheme. Figure 2 (a) The SCOPE architecture deploys B2S modules in a near-memory region near dynamic random access memory (DRAM) cells. This reduces the distance data travels during computation, thereby lowering latency and power consumption. Its processing flow includes:

[0045] (1) The input binary data (Binary data_in) is first converted into a random bit stream by the B2S module.

[0046] (2) The converted random bit stream participates in random multiplication (Stochastic MUL).

[0047] (3) The result of random multiplication is then converted back to binary form by the S2B module.

[0048] (4) The final binary result (Binary data_out) is output from the storage.

[0049] Figure 2 (b) Furthermore, the B2S module and the Stochastic Adder (Stochastic ADD) are directly embedded into the DRAM memory. This integration method allows for a tighter combination of storage and computation, further improving computational efficiency and reducing energy consumption. Its processing flow includes:

[0050] (1) The input binary data is also first converted into a random bit stream by the B2S module.

[0051] (2) The converted random bit stream directly participates in random multiplication operations (Stochastic MUL) within the memory.

[0052] (3) The result of random multiplication is converted back to binary form by the S2B module and the shifter.

[0053] (4) The final binary result is also output from the storage.

[0054] Figure 2 The study revealed how to optimize the performance of random computation by embedding computation modules (specifically binary-to-random number modules and random adders) into memory.

[0055] Figure 3 illustrates the area percentage distribution: (a) in the SCOPE architecture, the binary-to-random (B2S) module accounts for 13.6% of the total chip area; (b) the proposed design reduces the area percentage of both the binary-to-random (B2S) and random-to-binary (S2B) modules to less than 1%. Here, "area percentage" refers to the proportion of the total chip area occupied by a specific functional module in an integrated circuit (IC) design. This is because the chip area directly affects its cost, power consumption, heat dissipation requirements, performance, and reliability. Figure 3 The English terms in the text include:

[0056] B2S - Binary to Random Number Module

[0057] S2B - Random Number to Binary Module

[0058] DRAM Bank – Dynamic Random Access Memory

[0059] Proposed – The architecture proposed in this disclosure

[0060] Shifter

[0061] Figure 3 (a) In the SCOPE architecture, the Binary-to-Random (B2S) module accounts for 13.6% of the area, while the Dynamic Random Access Memory (DRAM) module accounts for 86%. The S2B module accounts for less than 1%. This indicates that the B2S module occupies relatively large hardware resources in the SCOPE architecture design. Because the B2S module occupies a considerable portion of the area, this limits the space available for data storage in the memory, affecting the overall storage density and cost-effectiveness. Figure 3 (b) is the design proposed in this disclosure, in which the area share of the binary-to-random (B2S) module and the random-to-binary (S2B) module is reduced to less than 1%, while the area share of the DRAM memory is increased to 99%. This design significantly reduces the area occupied by the B2S and S2B modules by integrating them into the memory. This integration method greatly improves the memory's storage efficiency because it allows more space to be used for data storage rather than for the conversion modules.

[0062] exist Figure 3The area ratio comparison shows the proportion of random computing modules (B2S and S2B) in the overall chip area in different design schemes. These modules occupy a relatively large area (13.6%) in the SCOPE architecture, while in the proposed design, these modules are integrated into the dynamic random access memory (DRAM) memory, significantly reducing the area occupied (less than 1%). This design improvement can bring higher storage density and potential performance advantages, while reducing cost and power consumption.

[0063] Figure 4 This reveals that data transfer constitutes the main overhead in random computation. Figure 4 The English terms in the text include:

[0064] Latency

[0065] ns — nanosecond (unit of time)

[0066] Data Movement

[0067] Calculation

[0068] GEMV dimension

[0069] Proposed – The proposed (method or architecture)

[0070] Figure 4 This paper reveals a comparison of latency between the existing method (SCOPE) and the method proposed in this disclosure under different GEMV (General Matrix-Vector) dimensional configurations. The GEMV dimension in the figure is defined by three parameters: [m, n] x [n, 1], representing the number of rows and columns of the matrix and the dimension of the vector, respectively. Latency is decomposed into two parts: data movement (blue) and computation (yellow). The vertical axis in the figure represents the operation latency in nanoseconds (ns), with lower latency indicating better performance. The blue bars represent the time required for data movement during computation. The yellow bars represent the time required to actually perform the computation operation. Dashed lines separate the different GEMV dimensions in the figure, and a comparison of latency between the SCOPE method and the method proposed in this disclosure is shown for each dimension.

[0071] 1. When the GEMV dimension is [m=8, n=8], the method proposed in this disclosure is 6.0 times faster than the SCOPE method.

[0072] 2. When the GEMV dimension increases to [m=8, n=16], the method proposed in this disclosure has a speed improvement of 6.8 times.

[0073] 3. When the GEMV dimension is further increased to [m=16, n=16], the method proposed in this disclosure has a speed improvement of 7.7 times.

[0074] 4. When the GEMV dimension is [m=16, n=32], the method proposed in this disclosure has an 8.5x speedup.

[0075] 5. When the GEMV dimension is at most [m=32, n=32], the method proposed in this disclosure has a speed improvement of 9.1 times.

[0076] therefore, Figure 4 This study reveals that data transfer (movement) constitutes the main overhead in stochastic computation, and that the proposed method significantly outperforms existing methods (SCOPE) under different GEMV dimension configurations. This demonstrates that the proposed method can more effectively reduce latency and improve computational efficiency when handling large-scale matrix-vector multiplications.

[0077] This disclosure, through analysis of existing solutions, summarizes the following problems with existing solutions:

[0078] 1. High area cost.

[0079] Binary-to-random (B2S) modules have a large area overhead. B2S modules are crucial for converting binary values ​​into random bit streams, and in random computing (SC) systems, they account for up to 80% of the hardware cost[4]. For example, in the SCOPE architecture (Figure 3), B2S modules occupy 13.6% of the circuit area, which is about one-sixth of a dynamic random access memory (DRAM) block[3].

[0080] 2. Frequent data movement.

[0081] In the SCOPE architecture (Figure 2(a)), the computation process requires multiple data transfers: (1) transferring random data to the Dynamic Random Access Memory (DRAM) core for multiplication (MUL); (2) transferring intermediate results for random-to-binary (S2B) conversion; (3) returning the data to the DRAM memory for binary addition (ADD); and (4) transferring the final result. As shown in Figure 4, these frequent data transfers significantly increase latency and power consumption.

[0082] 3. Limited scalability.

[0083] Traditional comparators are difficult to integrate directly into DRAM core arrays, which limits the deep integration and performance improvement of SC in DRAM-PIM.

[0084] Existing DRAM architectures mainly include the following units:

[0085] (1) Storage cell array

[0086] Each DRAM memory cell consists of one transistor and one capacitor (1T1C structure). The transistor acts as an access switch, and the capacitor is used to store data.

[0087] The memory cells are arranged in rows and columns to form a memory array. The gate of the transistor in each row of memory cells is connected to the word line, and the memory cells in each column are connected to the bit line. Access to the memory cells in a specific row is controlled by the word line, and data is read or written via the bit line.

[0088] (2) Auxiliary circuit

[0089] The sense amplifier (SA) is used to detect minute voltage changes on the bit lines to read data from the memory cells. In a standard read operation, the bit line BL and its complementary bit line BLB are first pre-charged to VDD / 2. Then, the word line WL is opened, and the storage capacitor and the BL capacitor share charge. If the storage capacitor stores a "1", the BL voltage increases from VDD / 2, while the BLB potential remains at VDD / 2. The SA compares the two potentials and raises the BL voltage further to "1", thus reading "1". If the storage capacitor stores a "0", the BL voltage decreases from VDD / 2, while the BLB potential remains at VDD / 2. The SA compares the two potentials and pulls the BL voltage lower to "0", thus reading "0".

[0090] According to one or more embodiments, the method proposed in this disclosure utilizes a charge-sharing process between a storage capacitor and a bit line (BL) capacitor. For example... Figure 5 As shown in (a), the charge sharing process is completed gradually, rather than instantaneously. Therefore, the industry typically limits this charge sharing time to ensure sufficient charge sharing. For example, Micron DDR5's t_RCD is 16 nanoseconds.

[0091] When comparing two binary numbers (two 8-bit INT8 numbers), they are stored bit-by-bit from high to low on the same BL / BLB in 8 rows of WL, such as... Figure 5As shown, the two numbers are stored in BL and BLB respectively. Then, the control transistors in rows 8 are turned on for charge sharing. It's important to note that the weight of the bits stored under different WLs (Whole Levels) is different for the binary number. Therefore, the on-time of the 8 WLs is weighted incrementally, with higher-order bits having a greater impact, i.e., allocated more time. Finally, the DRAM's sense amplifiers (SAs) compare and amplify the voltage after charge sharing, creating a time-weighted comparator for comparing the two binary values ​​without additional hardware.

[0092] This completes one comparison operation, yielding the B2S result. Figure 1 (a) generates one bit of the bit stream. The hardware required for the above operation is one SA corresponding to a pair of BL / BLB and 8 rows of WL inside the DRAM. At the same time, the DRAM structure supports many SAs to perform parallel operations. For example, 256 of the above structures can be performed at the same time to complete one conversion of INT8 number to 256 bit random bit stream.

[0093] Figure 5 includes (a) the dynamic charging and discharging process of the capacitor and (b) the time-weighted comparator in the proposed dynamic random access memory (DRAM). Figure 5 The Chinese and English terms include:

[0094] Voltage, Time [ns], V_charge(t), charging voltage (t)

[0095] V_discharge(t) — Discharge voltage(t), C — Capacitance, t — Time, RC — RC time constant, V_0 — Initial voltage, t_8 — Time 8, t_1 — Time 1,

[0096] SA—Sensing Amplifier

[0097] WL – Word Line

[0098] BL / BLB — Bit Line / Bit Line Bar

[0099] A time-weighted comparator was proposed.

[0100] Binary Number

[0101] Random Number

[0102] Figure 5(b) illustrates the circuit structure of a charge-sharing process in a DRAM memory array. Wherein,

[0103] 1. The control signal for selecting a specific memory array is obtained through the memory array address selector. In DRAM, data is stored in a matrix composed of rows and columns, and the memory array address selector is responsible for selecting a specific column for read or write operations.

[0104] 2. A word line (WL) is a wire that connects to a memory cell and is used to transmit data. In the diagram, WL represents 8 rows of WL, with each row corresponding to one memory cell.

[0105] 3. During charge sharing, as shown in the figure, two binary numbers are stored in different rows (WL) on the same BL or BLB. For example, one binary number (8 bits) is stored in WL1-WL8 on the BL, and another binary number (8 bits) is stored in WL1-WL8 on the BLB (this is not limited to WL1-WL8; it could be WLn-WLn+8 / if the original binary number is 4 bits, then WLn-WLn+4 is sufficient). By turning on the control transistor (usually controlled by the row address selector), the bits stored in these rows are made to share charge with the BL capacitor. Since the bits stored in different WLs have different weights for the binary number, with higher-order bits having a greater weight, this method allocates more time to higher-order bits during charge sharing to ensure more charge sharing.

[0106] 4. Sensing Amplifier (SA): After charge sharing is completed, the DRAM's sensing amplifier compares and amplifies the shared voltage, thereby enabling the comparison of two binary values ​​and creating a time-weighted comparator without additional hardware.

[0107] In this way, a comparison operation can be completed to obtain B2S ( Figure 1 (a) generates one bit of the bitstream. The required hardware includes a pair of BL / BLBs and a memory array address selector within the DRAM, as well as 8 rows of WL. Furthermore, the DRAM structure of this embodiment supports the parallel operation of many memory array address selectors; for example, 256 of the above structures can be operated simultaneously to complete one conversion of an INT8 number to a 256-bit random bitstream. Therefore, Figure 5 (b) demonstrates a circuit design for binary number comparison using the internal structure of DRAM. Through a combination of charge sharing and a sense amplifier, efficient binary number comparison operations can be achieved without adding additional hardware.

[0108] Figure 5(a) Reveals the voltage change over time during the charging and discharging of the capacitor. The figure shows two key times: t8 and t1, which correspond to specific time points in the charging and discharging processes, respectively.

[0109] The charging process takes time t8, during which the capacitor voltage gradually increases from its initial value V0 until it approaches 1V. This process can be described by the formula... The discharge process is described by the formula, where C is the capacitance value (~140fF) and RC is the RC time constant. After time t1, the capacitor begins to discharge, and the voltage gradually decreases from close to 1V. The discharge process can be described by the formula... To describe.

[0110] This disclosure further verifies the reliability of the embodiments. This disclosure uses the TSMC 65nm process design library (PDK) for SPICE simulation with the following simulation parameters: Ccell = 15fF, CBL = 140fF, tbit1 = 8ns, tbit2 = 7ns, up to tbit8 = 1ns, and rise / fall times Tr = Tf = 0.1ns. This disclosure evaluates three of the most stringent test scenarios to assess the accuracy of SA, where the values ​​in BL and BLB are very close, differing by only one bit: (1) Near minimum: BLB stores “0000 0001”, BL stores “0000 0010” or “0000 0000”, testing low value difference; (2) Median: BLB stores “0101 0101”, BL stores “0101 0110” or “0101 0100”, testing intermediate precision; (3) Near maximum: BLB stores “1111 1110”, BL stores “1111 1111” or “1111 1101”, testing robustness to high values.

[0111] Figure 6 shows the SPICE simulation results of the sense amplifier (SA) performance under three 8-bit bit line (BL) and complementary bit line (BLB) configurations. Figure 6 The English terms in the text include:

[0112] BL Voltage — Bit Line Voltage

[0113] Time [ns] — Time [nanosecond]

[0114] BLB_stores — Complementary Bitline Storage

[0115] BL_stores — Bitline storage

[0116] Figure 6Simulation results of the sense amplifier (SA) performance under three different 8-bit bit line (BL) and complementary bit line (BLB) configurations are disclosed. These simulation results are used to verify the reliability of the sense amplifier in all scenarios, ensuring that it can accurately compare 8-bit binary values ​​in the bit line (BL) and complementary bit line (BLB). The simulation results confirm the reliability of the SA in three of the most demanding scenarios, accurately comparing 8-bit binary values ​​in the BL and BLB. For 8-bit input, the design generates an n-bit random bit stream through parallel comparisons among n SAs, enabling probabilistic outputs without the need for additional comparators. This disclosure verifies the performance of the sense amplifier under various conditions by showing voltage variation curves under different bit line configurations. The curves show how the voltage on the bit line changes over time during readout and how weighted comparisons of different binary bits are achieved by controlling the timing. This design utilizes the native structure of DRAM, significantly reducing the need for additional hardware and improving efficiency. These test scenarios ensure the reliability and accuracy of the B2S conversion implemented in the sense amplifier.

[0117] Further through Figure 3 and Figure 4 This verifies that the proposed solution not only saves B2S hardware space but also significantly reduces data transfer costs.

[0118] This disclosure presents a time-weighted B2S conversion method: time-weighted voltage comparison is implemented through the Sense Amplifier (SA) within the DRAM, avoiding the use of an additional comparator module. By using the time-weighted SA voltage comparison method for B2S conversion, and implementing B2S conversion within the DRAM, existing resources within the DRAM are utilized to replace traditional hardware. This enables direct random computation in memory, reducing data transfer and computational overhead. Therefore, the beneficial effects of this disclosure specifically include:

[0119] 1. Reduce hardware costs.

[0120] Traditional B2S converters typically require additional comparator modules, increasing hardware complexity and area overhead. In contrast, the time-weighted internal B2S converter utilizes the Sense Amplifier (SA) within the DRAM for voltage comparison, eliminating the need for additional comparator modules and significantly reducing hardware overhead. This approach fully leverages the native structure of DRAM, enabling B2S conversion without adding extra hardware.

[0121] 2. Improve energy efficiency.

[0122] Since no external hardware is needed to perform the B2S conversion, the entire process takes place within the DRAM. This reduces the energy consumption of unnecessary external circuitry and data transmission, thereby improving the overall energy efficiency of the system. In traditional designs, frequent data movements and external computations consume significant amounts of energy, while internal conversion avoids these problems.

[0123] 3. Reduce data transmission latency.

[0124] Traditional B2S conversion requires transferring data from DRAM to an external computing unit for processing, which not only increases latency but also leads to higher energy consumption. In contrast, a time-weighted internal B2S converter integrates the conversion process entirely within DRAM, reducing the need for data movement and thus significantly lowering latency. This is particularly important for high-performance computing and real-time processing tasks.

[0125] 4. Improve system reliability.

[0126] Traditional B2S converters may introduce additional points of failure or instability due to the complexity of external hardware. However, by implementing the conversion directly within the DRAM, the entire process does not rely on additional external modules, thus enhancing the overall stability and reliability of the system. Utilizing the DRAM's own voltage comparison mechanism and time-weighted characteristics enables more stable operation.

[0127] 5. Saves chip area.

[0128] Significant chip area savings are achieved by eliminating the need for an additional B2S hardware module. In traditional designs, the B2S module occupies a considerable portion of the DRAM architecture area, which can become a bottleneck under resource constraints. The time-weighted internal B2S converter performs the conversion internally, greatly saving chip area and improving system area efficiency.

[0129] 6. Compatibility and scalability.

[0130] Because this converter utilizes existing resources within the DRAM (such as the Sense Amplifier and BL / BLB capacitors), it is easily compatible with existing DRAM architectures without any hardware modifications. This makes this approach highly scalable and applicable to memory systems of different sizes and types.

[0131] Therefore, this disclosure addresses this challenge by utilizing sense amplifiers (SAs) in dynamic random access memory (DRAM) to achieve efficient in-memory binary-to-random (B2S) conversion. By leveraging the voltage comparison mechanism inherent in the sense amplifiers (SAs), the method of this disclosure eliminates the need for conventional comparator modules, achieving seamless integration of B2S functionality within dynamic random access memory (DRAM).

[0132] In summary, this disclosure provides an efficient and feasible solution for modern DRAM-PIM architecture by reducing hardware overhead, improving energy efficiency, reducing latency, enhancing system reliability, saving chip area, and improving compatibility and scalability.

[0133] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0134] It is worth noting that although the spirit and principles of this invention have been described with reference to several specific embodiments, it should be understood that this invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that the features in these aspects cannot be combined; such division is merely for the convenience of description. This invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A numerical comparator, characterized in that, The comparator includes a memory cell array, wherein the memory cells of the memory cell array are connected by word lines and bit lines to form an array. The first number to be compared is stored sequentially in the storage units of different word lines on the same bit line, according to bit order. The different word lines on the same bit line form the first word line group. The second number involved in the comparison is stored sequentially in the order of its bits in the storage units of word lines that are different from any word line in the first word line group on the same complementary bit line corresponding to the bit line. The word lines that are different from any word line in the first word line group form the second word line group. The bit line and the complementary bit line are connected to the input terminal of the sensing amplifier corresponding to the bit line. When the comparator compares the first number and the second number, it turns on the control transistor of the word line to perform charge sharing; it also increases the weighting of the word line turn-on time and allocates more time to the higher bits. The sensing amplifier compares and amplifies the voltage after charge sharing, realizing a time-weighted comparison of two binary numbers.

2. The numerical comparator according to claim 1, characterized in that, The memory unit is a DRAM memory unit.

3. The numerical comparator according to claim 1, characterized in that, The first and second numbers are binary numbers.

4. The numerical comparator according to claim 3, characterized in that, The character lines of the first character line group and the character lines of the second character line group form a continuous sequence.

5. The numerical comparator according to claim 3, characterized in that, The source or drain of the transistor corresponding to the first bit is connected in parallel to the bit line, and the source or drain of the transistor corresponding to the second bit is connected in parallel to the complementary bit line.

6. The numerical comparator according to claim 5, characterized in that, The storage unit has a 1T1C structure.

7. The numerical comparator according to claim 6, characterized in that, The storage unit also includes a pre-charging circuit.

8. A B2S converter, characterized in that, The B2S converter includes a numerical comparator as described in claim 1, wherein the first number is the input binary number and the second number is a random number.

9. A random computing integrated circuit, characterized in that, Includes the B2S converter as described in claim 8.

10. A method for designing a numerical comparator, characterized in that, Includes the following steps: Based on a DRAM memory cell array, the memory cells of this array are connected by word lines and bit lines to form an array. The first number to be compared is input and stored in storage units on different word lines on the same bit line according to bit order. These different word lines on the same bit line form the first word line group. The second number to be compared is input and stored in the memory cell of the word line that is different from any word line in the first word line group on the same complementary bit line corresponding to the bit line, according to bit order. The word lines that are different from any word line in the first word line group form the second word line group. Connect the bit line and the complementary bit line to the input terminal of the sensing amplifier corresponding to the bit line. When the comparator compares the first number and the second number, it turns on the control transistor of the word line to perform charge sharing; it also increases the weighting of the word line turn-on time and allocates more time to the higher bits. The sensing amplifier compares and amplifies the voltage after charge sharing, realizing a time-weighted comparison of two binary numbers.

Images