Compensation circuit, display panel and display device

Abstract

This application provides a compensation circuit, a display panel, and a display device, relating to the field of display technology. The compensation circuit includes at least one driving module and a control module. Each driving module corresponds to multiple output channels, and each output channel provides data voltage to different pixel units within the same column. The control module is used to acquire delay information for each output channel corresponding to any one of the multiple driving modules. The control module is also used to compensate for the time at which each output channel outputs data voltage in the second frame, based on the data voltage of the pixel units in the same row in the first and second frames, and the delay information of each output channel. The first and second frames are adjacent frames. The technical solution provided by this application can optimize the delay time between different output channels, thereby reducing the impact of incorrect charging on the display panel.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and more particularly to a compensation circuit, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, the demand for large-size, high-refresh-rate LCD monitors has also increased significantly. These display devices place increasingly stringent requirements on circuit driving performance and charging efficiency, especially in high-resolution and high-refresh-rate applications, where the larger driving area and higher refresh rate drastically reduce the available charging time per row of pixels.

[0003] In current display panels, due to the chip-on-film (COF) manufacturing process, the data lines connecting to the thin-film transistors (TFTs) vary in distance and length. This causes a delay when the output channels connected to the COF charge the pixels by outputting data through the data lines. Furthermore, the data rise rate may differ between output channels of different COF types. With increasingly shorter charging times, this makes it more likely that when an output channel charges a row of pixels, it will incorrectly charge other rows. Summary of the Invention

[0004] In view of this, this application provides a compensation circuit, a display device, and a display panel for compensating for the timing of the output data voltage of the output channel, so as to solve the problem of incorrect charging.

[0005] To achieve the above objectives, in a first aspect, embodiments of this application provide a compensation circuit applied to a display panel, the display panel including N rows × M columns of pixel units. The circuit includes: at least one driving module and a control module, each driving module corresponding to multiple output channels, each output channel being used to provide data voltage to different pixel units within the same column. The control module is used to acquire delay information of each output channel corresponding to any one of the multiple driving modules. The control module is further used to compensate for the time at which each output channel outputs data voltage in the second frame, based on the data voltage of the pixel units in the same row in the first and second frames, and the delay information of each output channel. The first and second frames are adjacent frames.

[0006] In this application, the compensation circuit includes at least one driving module and a control module. Each driving module corresponds to multiple output channels, and each output channel is used to provide data voltage to different pixel units within the same column. Since each output channel is located differently, different delays occur when outputting data voltage, which can easily lead to incorrect charging. Therefore, the control module in the compensation circuit acquires the delay information of each output channel corresponding to any one of the multiple driving modules, and then compensates for the time when each output channel outputs data voltage in the second frame based on the data voltage of the pixel units in the same row in the first and second frames, and the delay information of each output channel. This optimizes the output delay time between different output channels, thereby reducing the impact of incorrect charging on the display panel.

[0007] In one possible implementation of the first aspect, the circuit further includes: a detection module and an analog-to-digital converter (ADC), the ADC being connected between the detection module and the control module. The detection module is used to detect the data voltage output by each output channel corresponding to any driving module. It is also used to determine the voltage difference between each output channel and the first output channel based on the data voltage output by each output channel. Furthermore, it is used to determine delay information for each output channel based on the voltage difference between each output channel and the first output channel. The ADC is used to convert the delay information into a digital signal.

[0008] As an optional implementation of this application, the data voltage of each output channel can be collected by the detection module, and the delay information of each output channel can be calculated.

[0009] In one possible implementation of the first aspect, the detection module is specifically used to detect the data voltage of each output channel corresponding to any driving module during the time period from a first time point to a second time point. The first time point is the moment when the first output channel begins to output data voltage, and the second time point is the moment when the first output channel stops outputting data voltage.

[0010] As an optional implementation of this application, the first moment and the second moment are determined by the time of the first output channel, so that the delay information of each output channel can be determined based on the time of the data voltage output by the reference first output channel.

[0011] In one possible implementation of the first aspect, the control module is further configured to determine the compensation time for each output channel based on the difference in data voltage between the first and second frames of pixel units in the same row, and the delay information of each output channel. The control module is also configured to compensate for the time at which each output channel outputs data voltage in the second frame based on the compensation time.

[0012] As an optional implementation of this application, the control module can determine the compensation time of each output channel by combining the difference in data voltage between adjacent frames, thereby eliminating the mischarging phenomenon caused by excessive difference in data voltage between adjacent frames.

[0013] In one possible implementation of the first aspect, the plurality of driving modules includes a first driving module and a second driving module. The detection module is further configured to detect, during a first time period as the data voltage transitions from 0 to a common voltage, the linear integral of the data voltage output by the second output channel of the first driving module and the linear integral of the data voltage output by the second output channel of the second driving module, and to determine the linear integral difference. The control module is further configured to compensate the data voltage output by the second output channel of the first driving module or the second driving module based on the linear integral difference.

[0014] As an optional implementation of this application, for the same output channel of different drive modules, the control module can also reduce the impact of the difference in rise time of different output channels on the charging time by compensating for the data voltage.

[0015] In one possible implementation of the first aspect, the start time of the first time period is when the data voltage rises to a first voltage threshold, and the end time of the first time period is when the data voltage rises to a second voltage threshold. The first voltage threshold is less than the second voltage threshold, and both the first and second voltage thresholds are determined by a common voltage.

[0016] As an optional implementation of this application, this allows for control over the duration of the first time period.

[0017] In one possible implementation of the first aspect, when the linear integral difference is greater than 0, the control module compensates for the data voltage output by the second output channel of the second drive module. When the linear integral difference is less than 0, the control module compensates for the data voltage output by the second output channel of the first drive module.

[0018] As an optional implementation method of this application, the data voltage of the output channel in different driving modules can be flexibly compensated.

[0019] In one possible implementation of the first aspect, the control module is further configured to determine a compensation voltage based on the linear integral difference. The control module is also configured to compensate the data voltage output by the second output channel of the first drive module or the second drive module based on the compensation voltage.

[0020] As an optional implementation of this application, the linear integral difference can indicate the difference in the rise rate of the output data voltage of different output channels, thereby compensating for the output data voltage of the output channels according to the difference in rise rate.

[0021] Secondly, embodiments of this application provide a display panel, which includes the circuitry described in the first aspect.

[0022] Thirdly, embodiments of this application provide a display device, which includes the display panel described in the second aspect.

[0023] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0025] Figure 2 A schematic diagram of the data voltage curves of SOUT at different locations in the same COF provided in this application embodiment;

[0026] Figure 3 A schematic diagram of the data voltage curve of SOUT at the same location in different COFs is provided for an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of a compensation circuit provided in an embodiment of this application;

[0028] Figure 5 A schematic diagram of the output data voltage curves of the same driving module SOUT0 and SOUTn provided for an embodiment of this application;

[0029] Figure 6 A schematic diagram of the SOUT0 output data voltage of different driving modules provided in an embodiment of this application;

[0030] Figure 7 A schematic diagram of the circuit layout of a display panel provided in an embodiment of this application;

[0031] Figure 8 This is a circuit diagram of a display panel provided in an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 401, Driver Module; 401a, First Driver Module; 401b, Second Driver Module;

[0034] 402. Control module; 403. Detection module; 404. Analog-to-digital conversion module. Detailed Implementation

[0035] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0036] Before providing a detailed explanation of the embodiments of this application, the application scenarios of these embodiments will be described first.

[0037] With the iterative upgrades of display technology, high refresh rates, high resolutions, and large-size display panels have gradually become the market mainstream. However, these display panels have some impact on the sensitivity to charging time and charging efficiency. For example, a high refresh rate means a shorter frame period is required, which significantly compresses the available charging time for each row of pixels in the display panel. Furthermore, a large-size display panel lengthens the signal transmission path, further exacerbating the decline in charging efficiency.

[0038] In display panels, chip-on-film (COF) technology is a key technology for data transmission, primarily outputting data voltage through an output channel (SOUT). For example... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel includes multiple COFs. Each COF is used to provide a data voltage to multiple columns of pixel units through multiple SOUTs, wherein each SOUT corresponds to one column of pixel units. Figure 1 Taking the intermediate transmission channel SOUT0 and the farthest transmission channel SOUTn as examples, the gate driver provides a driving voltage to each row of pixel units to turn on the switches connected to the pixel units. For example, each pixel unit can be connected to a thin-film transistor (TFT) as its switch. For instance, when the gate driver provides a driving voltage to the first row of pixel units, the gate of the thin-film transistor (TFT) connected to each pixel unit in the first row receives the driving voltage, turning on the TFT. At this time, each pixel unit in the first row receives the data voltage from SOUT through the TFT to drive the pixel unit.

[0039] In one possible scenario of this application, for a COF, due to the COF manufacturing process, there will be a delay in the output voltage between different SOUT positions, such as... Figure 2 As shown, Figure 2 Solid line 1 in the diagram represents the data voltage output curve of SOUT (denoted as SOUT0) located in the middle of the COF, while dashed line 1 represents the data voltage output curve of SOUT (denoted as SOUTn) located at the farthest end of the COF. Because SOUTn has the longest trace, it experiences a delay in outputting data voltage compared to SOUT0. Ideally, the TFT gate should stop receiving data voltage the instant it is turned off. However, in reality, after the TFT gate is turned off, the gate voltage undergoes a non-ideal, slow decline, such as... Figure 2 The gate voltage curve (solid line 2) is shown in the figure. Thus, when the gate of the next row of TFTs is turned on, SOUTn is still outputting data voltage, resulting in a charging error.

[0040] In one possible scenario of this application, for different COFs, the rise rate of the data voltage output at the same location of SOUT may also be different, such as... Figure 3 As shown, Figure 3 In the diagram, solid line 1 represents the data voltage curve output by SOUT1 of COF1, and dashed line 1 represents the data voltage curve output by SOUT1 of COFn. Because the rise rate of the data voltage output by SOUT1 of COFn is lower than that of SOUT1 of COF1, the charging efficiency is reduced when COFn's SOUT1 outputs a data voltage for charging. Furthermore, the fall time of the data voltage output by SOUT1 of COFn is also longer. Therefore, when the gate of the next row of TFTs is turned on, SOUTn will also output a data voltage, resulting in incorrect charging.

[0041] To address this, embodiments of this application provide a compensation circuit, a display panel, and a display device. This compensation circuit can detect and calculate the output of the SOUT (Signal Outlet) to compensate for the timing of the SOUT output, thereby optimizing the impact of output delays between different SOUTs on charging time. Alternatively, it can detect and calculate the output of the SOUTs of different COFs (Chip Frames) to compensate for the output data voltage, reducing the impact on charging time.

[0042] The following is a detailed explanation of a compensation circuit, display panel, and display device provided in the embodiments of this application.

[0043] like Figure 4 As shown, Figure 4 This is a schematic diagram of a compensation circuit provided in an embodiment of this application. The circuit is applied to a display panel, which includes N rows × M columns of pixel units. The circuit includes: at least one driving module 401 (e.g., such as...). Figure 4 The driving module 401a, driving module 401b) and control module 402 are included.

[0044] Each driving module 401 corresponds to multiple output channels, and each output channel is used to provide data voltage to different pixel units in the same column.

[0045] For example, driver module 401a corresponds to SOUT0 to SOUTn, and SOUT0 to SOUTn are used to provide data voltages to the pixel units in columns A0 to An, respectively. Driver module 401b corresponds to SOUT0 to SOUTn, and SOUT0 to SOUTn are used to provide data voltages to the pixel units in columns B0 to Bn, respectively. In other words, different driver modules are used to provide data voltages to different pixel units.

[0046] In one possible embodiment, the multiple output channels corresponding to different drive modules 401 can be positioned one-to-one.

[0047] For example, SOUT0 of driver module 401a and SOUT0 of driver module 401b are located in the same position within their respective driver modules; for instance, they are both intermediate output channels within the driver modules. Similarly, SOUTn of driver module 401a and SOUTn of driver module 401b are located in the same position within their respective driver modules; for instance, they are both the furthest output channels within the driver modules.

[0048] In one possible embodiment, the driving module 401 may be a driving chip. The driving chip uses COF technology to connect the output pins to multiple output channels. The driving chip can output data voltage through multiple output channels to charge the pixel unit.

[0049] As an example, the number of output channels is the same as the number of columns of pixel units, and each output channel is used to provide data voltage to the corresponding column of pixel units.

[0050] In the embodiments of this application, for ease of description, the driving module 401 can be represented by COF, that is, COF can be understood as a module. For example, driving module 401a can be COF1, and driving module 401b can be COFn.

[0051] The control module 402 is used to acquire the delay information of each output channel corresponding to any one of the multiple drive modules.

[0052] In one possible embodiment, the delay information for each output channel is used to indicate the time difference when each output channel outputs data voltage.

[0053] As an example, taking the time of the output data voltage of the first output channel of the drive module 401a as a reference, the time difference between the time of the output data voltage of each of the remaining output channels and the time of the output data voltage of the first output channel is the delay information of each of the remaining output channels.

[0054] For example, the driver module 401a has n+1 output channels, namely SOUT0 to SOUTn, with SOUT0 being the first output channel. Assuming SOUT0 outputs data voltage at time t0, then SOUT1 outputs data voltage at time t0+Δt1, where Δt1 is the time difference between the output times of SOUT0 and SOUT1, representing the delay information when SOUT1 outputs data voltage; similarly, SOUTn outputs data voltage at time t0+Δtn, where Δtn is the time difference between the output times of SOUT0 and SOUTn, representing the delay information when SOUTn outputs data voltage.

[0055] The control module 402 is further configured to compensate for the timing of each output channel's output data voltage in the second frame based on the data voltages of the pixel units in the same row in the first and second frames, and the delay information of each output channel. The first and second frames are adjacent frames.

[0056] In one possible embodiment, the data voltage of adjacent frames includes the data voltage dataN of the Nth frame and the data voltage dataN+1 of the (N+1)th frame.

[0057] In one possible implementation, the control module 402 can first determine the initial compensation time for the output data voltage of each output channel based on the delay information of each output channel. Since the difference in data voltage between adjacent frames affects the charging time, the control module 402 then determines an additional compensation time based on the difference in data voltage between adjacent frames. The initial compensation time and the additional compensation time can determine the final compensation time.

[0058] As an example, when the difference in data voltage between adjacent frames is large, the required additional compensation time also increases; when the difference in data voltage between adjacent frames is small, the required additional compensation time decreases, or no additional compensation time may be required.

[0059] In one possible embodiment, the final compensation time can satisfy the formula: Δt_total = Δt + k * ΔD. Where Δt is the delay information for each output channel, ΔD is the difference in data voltage between adjacent frames, and k is the compensation coefficient.

[0060] As an example, the output channels of the drive module 401a include SOUT0 to SOUTn. The control module 402 can acquire the delay information of SOUT0 to SOUTn, thereby determining the initial compensation time of each transmission channel as Δt0 to Δtn. When the difference in data voltage between adjacent frames is 0, the final compensation times for the output data voltages of SOUT0 to SOUTn are Δt0 to Δtn, respectively. When the difference in data voltage between adjacent frames is ΔD, the final compensation times for the output data voltages of SOUT0 to SOUTn are Δt0 + k*ΔD to Δtn + k*ΔD, respectively.

[0061] For example, the delay time of the SOUTn output data voltage of the driver module 401a is Δtn = 0.6μs, the difference in data voltage between adjacent frames is ΔD = 4V, and k is taken as 0.1. Then the final compensation time for the SOUTn output data voltage is 0.6 + 0.1 * 4 = 1μs, that is, the time of the SOUTn output data voltage is advanced by 1μs.

[0062] In this application, the compensation circuit includes at least one driving module and a control module. Each driving module corresponds to multiple output channels, and each output channel is used to provide data voltage to different pixel units within the same column. Since each output channel is located differently, different delays occur when outputting data voltage, which can easily lead to incorrect charging. Therefore, the control module in the compensation circuit acquires the delay information of each output channel corresponding to any one of the multiple driving modules, and then compensates for the time when each output channel outputs data voltage in the second frame based on the data voltage of the pixel units in the same row in the first and second frames, and the delay information of each output channel. This optimizes the output delay time between different output channels, thereby reducing the impact of incorrect charging on the display panel.

[0063] In one possible embodiment of this application, the circuit further includes a detection module 403 and an analog-to-digital converter module 404. The analog-to-digital converter module 404 is connected between the detection module 403 and the control module 402.

[0064] The detection module 403 is used to detect the data voltage output by each output channel corresponding to any driving module. It is also used to determine the voltage difference between each output channel and the first output channel based on the data voltage output by each output channel. Furthermore, it is used to determine the delay information of each output channel based on the voltage difference between each output channel and the first output channel.

[0065] In one possible embodiment, the first output channel is the intermediate output channel of any driving module. Since the intermediate output channel is located in the middle of the driving module, the first output channel has the least output delay when outputting data voltage. In this embodiment, the intermediate output channel is considered to have no delay.

[0066] In one possible embodiment of this application, the detection module 403 is specifically used to detect the data voltage of each output channel corresponding to any driving module during the time period from a first time moment to a second time moment. The first time moment is the moment when the first output channel starts outputting data voltage, and the second time moment is the moment when the first output channel stops outputting data voltage.

[0067] For example, taking driver module 401a as an example, SOUT0 is the first output channel of driver module 401a. Figure 5 As shown, Figure 5 The curves show the output data voltages of SOUT0 and SOUTn of the drive module 401a. Here, t1 is the moment when SOUT0 begins outputting data voltage, and t2 is the moment before the gate is turned off.

[0068] In one possible embodiment, since the output data voltage of each output channel is output at different times, the voltage change from the first moment to the second moment is also different.

[0069] For example, such as Figure 5 As shown, the voltage change of SOUT0 from 0 to V0 during time t1 to t2; the voltage change of SOUTn from 0 to Vn during time t1 to t2. Therefore, the voltage difference ΔV between SOUTn and SOUT0 is V0 - Vn.

[0070] In one possible implementation, the delay information of each output channel is determined by the voltage difference between each output channel and the first output channel, as well as the rate of voltage change of the output of each output channel.

[0071] As an example, the delay information for each output channel is the time difference Δtn between the output data voltage of the output channel and the output data voltage of the first output channel. Here, Δtn can be determined by the voltage change rate (dVn / dt) of the output channel and the voltage difference between the output channel and the first output channel.

[0072] For example, such as Figure 5As shown, the voltage change of SOUT0 from 0 to V0 during time t1 to t2; the voltage change of SOUTn from 0 to Vn during time t1 to t2. Therefore, the voltage difference between SOUT0 and SOUTn is ΔVn = V0 - Vn. Based on the voltage change rate of SOUTn (dVn / dt) and the voltage difference ΔVn, the delay information of SOUTn is determined as Δtn = ΔVn / (dVn / dt). For example, if the voltage change rate of SOUTn is 0.5V / μs, and the voltage difference between SOUT0 and SOUTn is 0.25V, then the delay information of SOUTn is 0.25 / 0.5 = 0.5μs.

[0073] The analog-to-digital converter module 404 is used to convert delay information into digital signals.

[0074] In one possible embodiment, the input terminal of the analog-to-digital converter module 404 is connected to the output terminal of the detection module 403. The output terminal of the analog-to-digital converter module 404 is connected to the input terminal of the control module 402.

[0075] For example, the analog-to-digital conversion module 404 can be an analog-to-digital converter (ADC). An ADC can convert continuous analog signals (e.g., voltage, current) into discrete digital signals, facilitating processing and storage by the control module 402. The number of ADCs can be one or more, and this embodiment is not limited.

[0076] In one possible embodiment, the control module 402 is a timing controller (TCON). The input of the TCON is connected to the analog-to-digital converter module 404, and the output of the TCON is connected to the driver module 401. The TCON first acquires the data voltage to be output, receives the digital signal corresponding to the delay information of each output channel, and then controls the timing of the data voltage according to the delay information to send the data voltage to the driver module 401.

[0077] In one possible embodiment of this application, the control module 402 is further configured to determine the compensation time for each output channel based on the difference in data voltage between the first and second frames of pixel units in the same row, and the delay information of each output channel. The control module 402 is also configured to compensate for the time at which each output channel outputs data voltage in the second frame based on the compensation time.

[0078] In one possible embodiment, the control module 402 determines the initial compensation time for the output data voltage of each output channel based on the digital signal corresponding to the delay information of each output channel. The control module 402 then determines an additional compensation time based on the difference in data voltage between adjacent frames. The compensation time is determined by the initial compensation time and the additional compensation time; for example, the compensation time is the sum of the initial compensation time and the additional compensation time.

[0079] For example, the initial compensation time for the SOUTn output data voltage of the drive module 401a in the Nth frame is Δtn = 0.6μs. The difference in data voltage between adjacent frames is ΔD = 4V, and k is taken as 0.1. Then, the additional compensation time is 0.1 * 4 = 0.4μs. The control module 402 determines the first compensation parameter for the timing of the SOUTn output data voltage as 0.6 + 0.4 = 1μs. The control module 402 controls the SOUTn of the drive module 401a to output the data voltage 1μs earlier in the N+1th frame.

[0080] In one possible embodiment of this application, the plurality of driving modules includes a first driving module and a second driving module.

[0081] For example, the first driving module is driving module 401a, and the second driving module is driving module 401b.

[0082] The detection module 403 is also used to detect the linear integral of the data voltage output by the second output channel of the first drive module and the linear integral of the data voltage output by the second output channel of the second drive module during the first time period when the data voltage changes from 0 to the common voltage, and to determine the linear integral difference.

[0083] In one possible embodiment, the first time period begins when the data voltage rises to a first voltage threshold, and ends when the data voltage rises to a second voltage threshold. The first voltage threshold is less than the second voltage threshold, and both the first and second voltage thresholds are determined by a common voltage.

[0084] As an example, the first voltage threshold is the voltage value when the data voltage output by the output channel is A% of the common voltage, and the second voltage threshold is the voltage value when the data voltage output by the output channel is B% of the common voltage. Where A is less than B.

[0085] For example, the first voltage threshold is the voltage value when the data voltage output by the output channel is 10% of Vcom, and the second voltage threshold is the voltage value when the data voltage output by the output channel is 90% of Vcom.

[0086] For example, the second output channel is SOUT0, the first driver module is driver module 401a, and the second driver module is driver module 401b, such as... Figure 6 As shown, the time required for the data voltage output from SOUT0 of drive module 401a to change from V1 to V2 is tr0(t0~t1), and the time required for the data voltage output from SOUT0 of drive module 401b to change from V1 to V2 is trn(t2~t3). Here, V1 is 10% of Vcom, and V2 is 90% of Vcom.

[0087] The linear integral is the integration of the voltage waveform over a certain time interval. For example, if the start time of the first time interval is t0 and the end time of the first time interval is t1, the linear integral is the integration calculation of the waveform from the first voltage threshold to the second voltage threshold within the interval from t0 to t1.

[0088] For example, the first driving module is driving module 401a, and the second driving module is driving module 401b. The linear integral of SOUT0 of driving module 401a over tr0 (t0~t1) is: The linear integral of SOUT0 of the drive module 401b over trn (t2~t3) is The difference between the linear integrals of SOUT0 of drive module 401a and SOUT0 of drive module 401b is Integral 0 - Integral n.

[0089] The control module 402 is also used to compensate the data voltage output by the second output channel of the first drive module or the second drive module according to the linear integral difference.

[0090] In one possible embodiment of this application, when the linear integral difference is greater than 0, the control module 402 is used to compensate the data voltage output by the second output channel of the second drive module. When the linear integral difference is less than 0, the control module 402 is used to compensate the data voltage output by the second output channel of the first drive module.

[0091] As an example, when the thrust of the data voltage output by the second output channel of the first driving module is greater than the thrust of the data voltage output by the second output channel of the second driving module, the data voltage output by the second output channel of the second driving module needs to be compensated. When the thrust of the data voltage output by the second output channel of the first driving module is less than the thrust of the data voltage output by the second output channel of the second driving module, the data voltage output by the second output channel of the first driving module needs to be compensated.

[0092] For example, when the difference between the linear integrals of SOUT0 of drive module 401a and SOUT0 of drive module 401b, Integral 0 - Integral n, is greater than 0, it means that the thrust of the output data voltage of SOUT0 of drive module 401a is greater than that of SOUT0 of drive module 401b. Therefore, the output data voltage of SOUT0 of drive module 401b is compensated based on the difference in linear integrals.

[0093] Similarly, when the difference between the linear integrals of SOUT0 of drive module 401a and SOUT0 of drive module 401b, Integral0-Integraln, is less than 0, it indicates that the thrust of the output data voltage of SOUT0 of drive module 401b is greater than that of SOUT0 of drive module 401a. Therefore, the output data voltage of SOUT0 of drive module 401a is compensated based on the linear integral difference.

[0094] In one possible embodiment of this application, the control module 402 is further configured to determine a compensation voltage based on the linear integral difference. The control module 402 is also configured to compensate the data voltage output by the second output channel of the first drive module or the second drive module based on the compensation voltage.

[0095] In one possible embodiment, the compensation voltage is determined by a compensation coefficient and state information. For example, the compensation voltage is the product of the compensation coefficient and the state information.

[0096] The compensation coefficient is determined by the common voltage and the linear integral difference. For example, when the actual common voltage is greater than the preset common voltage, the compensation coefficient is decreased; when the actual common voltage is less than the preset common voltage, the compensation coefficient is increased.

[0097] As an example, the compensation coefficient A = Db / α, where α is the ratio of the actual common voltage Vcom to the preset common voltage Vcom'. When Vcom is greater than Vcom', α is greater than 1, and the compensation coefficient A will decrease; when Vcom is less than Vcom', α is less than 1, and the compensation coefficient A will increase.

[0098] For example, the first driving module is driving module 401a, the second driving module is driving module 401b, and the control module 404 determines the linear integral difference Db between the time information of SOUT0 on driving module 401a and SOUT0 on driving module 401b. Then the compensation voltage is A*Db.

[0099] In one possible embodiment, the control module 404 compensates for the data voltage output by the second output channel of the second drive module in the Nth frame.

[0100] For example, if the control module 402 receives data(n) from the drive module 401b at the Nth frame of SOUT0, then according to the compensation voltage A*Db, the data voltage compensation of SOUTn at the Nth frame is data(n)+A*Db.

[0101] like Figure 7 The diagram shows a circuit layout of a display panel. The driving module 401 is a COF, including COF1 and COFn. Each COF1 corresponds to multiple SOUTs (only SOUT0 of COF1, SOUT0 and SOUTn of COFn are shown in the figure). The control module 402 is a TCON, and the analog-to-digital converter 404 is an ADC (ADC1 and ADC2 are set in the figure due to the position relationship of COF, and each ADC has the same function).

[0102] The following is combined with Figure 7 The specific implementation of the embodiments of this application is described, including two cases: one is for SOUT on the same COF, and the other is for SOUT on different COFs.

[0103] Case 1: For SOUT on the same COF, take COFn as an example.

[0104] Step 1: Detection module 403 detects the voltage difference between each SOUT on COFn from the first time to the second time.

[0105] Wherein, the first moment t0 is the moment when SOUT0 starts outputting data voltage, and the second moment t1 is the moment when SOUT0 stops outputting data voltage.

[0106] For example, the detection module 403 detects the voltage of SOUTn during the time period from t0 to t1. The voltage of SOUTn is 0 at t0 and Vn at t1. Therefore, the voltage of SOUTn during the time period from t0 to t1 is Vn-0=Vn.

[0107] Step 2: The detection module 403 determines the delay information of each SOUT based on the data voltage output by each SOUT and the data voltage output by SOUT0.

[0108] As an example, the detection module 403 determines the voltage difference between each SOUT and SOUT0 based on the data voltage output by each SOUT and the data voltage output by SOUT0. Then, based on the voltage difference between each SOUT and SOUT0 and the rate of change of the voltage output by each SOUT, it determines the delay information.

[0109] For example, the voltage difference of SOUT0 during the time interval t0 to t1 is V0 - 0 = V0. The voltage difference of SOUTn during the time interval t0 to t1 is known to be Vn. Therefore, the voltage difference between SOUT0 and SOUTn is ΔVn = V0 - Vn. Based on the voltage change rate of SOUTn (dVn / dt) and the voltage difference ΔVn, the delay information of SOUTn is determined as Δtn = ΔVn / (dVn / dt).

[0110] Step 3: The detection module 403 sends the delay information for each SOUT to the ADC. Correspondingly, the ADC receives the delay information for each SOUT from the detection module 403.

[0111] For example, the detection module 403 sends delay information for each SOUT to the ADC2.

[0112] Step 4: The ADC converts the analog signal corresponding to the delay information into a digital signal and sends the digital signal to the TCON. Correspondingly, the TCON receives the digital signal from the ADC.

[0113] For example, the detection module 403 receives digital signals from the ADC2.

[0114] Step 5: TCON compensates for the time when each SOUT outputs data voltage in the second frame based on the data voltage of the pixel units in the same row in the first and second frames, as well as the delay information of each SOUT.

[0115] In this context, the first and second frames are adjacent frames; for example, the first frame is frame N, and the second frame is frame N+1. The data difference between adjacent frames is the difference between the data of frame N and the data of frame N+1. The following description assumes that the data difference between adjacent frames is 0.

[0116] In one possible implementation, TCON determines the compensation time for each SOUT based on the digital signal corresponding to the delay information of each SOUT.

[0117] As an example, time compensation for the SOUT output data voltage can be achieved by either enabling the SOUT to output data voltage earlier or by delaying the SOUT to output data voltage.

[0118] For example, SOUT0 outputs a data voltage at time t0, and controls SOUTn to output a data voltage at time t0-Da. Alternatively, SOUTn outputs a data voltage at time t0, and controls SOUT0 to output a data voltage at time t0+Da.

[0119] In one possible implementation, maximum time compensation is applied to SOUTn, and the time for output data voltage from SOUT0 to SOUTn gradually increases.

[0120] As an example, the compensation for the time when SOUTn outputs data voltage in the N+1th frame is t0-Da, and the compensation for the time when SOUTn-1 outputs data voltage in the N+1th frame is t0-Da(n-1) / n, and so on.

[0121] For example, SOUT0 is the middle SOUT of COF, and SOUT5 is the farthest SOUT of COF. The compensation for the time when SOUT5 outputs data voltage in the N+1 frame is t0-5ns. The compensation for the time when SOUT4 outputs data voltage in the N+1 frame is t0-5(5-1) / 5=t0-4ns. The compensation for the time when SOUT3 outputs data voltage in the N+1 frame is t0-5(5-2) / 5=t0-3ns. The compensation for the time when SOUT2 outputs data voltage in the N+1 frame is t0-5(5-3) / 5=t0-2ns. The compensation for the time when SOUT1 outputs data voltage in the N+1 frame is t0-5(5-4) / 5=t0-1ns.

[0122] Case 2: For SOUT on different COFs, take COF1 and COFn as examples.

[0123] Step 1: During the first time period of the data voltage from 0 to the common voltage, the detection module 403 detects the linear integral of the SOUT0 output data voltage of COF1 and the linear integral of the SOUT0 output data voltage of COFn, and determines the difference between the linear integrals.

[0124] In one possible embodiment, the detection module 403 determines the linear integral based on the first time point obtained from the timing.

[0125] The first time period begins when the data voltage rises to a first voltage threshold, and ends when the data voltage rises to a second voltage threshold. The first voltage threshold is lower than the second voltage threshold, and both the first and second voltage thresholds are determined by a common voltage.

[0126] For example, during the process of the output voltage of SOUT0 on COF1 rising from 0 to the common voltage Vcom, timing begins when the voltage rises to 10% of Vcom, at which point the time is t0, and the corresponding voltage is the first voltage threshold; timing ends when the voltage rises to 90% of Vcom, at which point the time is t1, and the corresponding voltage is the second voltage threshold. The first time interval from t0 to t1 is denoted as tr0.

[0127] Similarly, as the output voltage of SOUT0 on COFn rises from 0 to the common voltage Vcom, timing begins when the voltage reaches 10% of Vcom, at which point the time is t2, and the corresponding voltage is the first voltage threshold. Timing ends when the voltage reaches 90% of Vcom, at which point the time is t3, and the corresponding voltage is the second voltage threshold. The time interval from t2 to t3 is denoted as trn.

[0128] The linear integral is determined by the voltage waveform from the first voltage threshold to the second voltage threshold and the first time period.

[0129] For example, the time required for the data voltage output by COFn's SOUT0 to change from the first voltage threshold to the second voltage threshold is the time interval t2 to t3, and the waveform from the first voltage to the second voltage satisfies V n (t), where t is the time variable. Then the linear integral of the time information of SOUT0 on COFn is:

[0130] Similarly, the time required for the voltage at SOUT0 on COF1 to change from the first voltage to the second voltage is the time interval from t0 to t1. The waveform from the first voltage to the second voltage satisfies V1(t), where t is a time variable. Therefore, the linear integral of the time information of SOUT0 on COF1 is: Therefore, the linear integral difference of SOUT0 on COFn is Db = Integral 0 - Integral n.

[0131] Step 2: The detection module 403 sends the linear integral difference between the SOUTs of different COFs to the ADC. Correspondingly, the ADC receives the linear integral difference between the SOUTs of different COFs from the detection module 403.

[0132] For example, the detection module 403 sends the linear integral difference Db between SOUT0 of COF1 and SOUT0 of COFn to the ADC.

[0133] Step 3: The ADC converts the linear integral difference into a digital signal and sends the digital signal to the TCON. Correspondingly, the TCON receives the digital signal from the ADC.

[0134] For example, the ADC sends a digital signal with a linear integral difference Db to the TCON.

[0135] Step 4: TCON determines the compensation voltage based on the linear integral difference between the SOUT values ​​of different COF values.

[0136] In one possible embodiment, the compensation voltage is determined by a compensation coefficient and a linear integral difference. For example, the compensation voltage is A*Db, where A is the compensation coefficient and Db is the state information.

[0137] For example, the control module 404 uses the linear integral difference Db between the time information of SOUT0 on COF1 and SOUT0 on COFn as the reference value of the compensation voltage, and the compensation voltage is A*Db.

[0138] Step 5: TCON compensates the data voltage output by COF's SOUT in the Nth frame based on the compensation voltage.

[0139] For example, if TCON receives data(n) from SOUT0 of COFn in the Nth frame, then according to the compensation voltage A*Db, the voltage compensation of the data from SOUT0 of COFn in the Nth frame is data(n) + A*Db.

[0140] Case 1 and Case 2 above describe the compensation for SOUT on the same COF and the compensation for SOUT on different COFs, respectively. Combining Case 1 and Case 2, TCON can first compensate for SOUT on multiple COFs, and then compensate for SOUT on each of the multiple COFs; or, TCON can first compensate for SOUT on each COF, and then TCON compensate for SOUT on different COFs.

[0141] The following example illustrates how TCON first compensates for the SOUT on multiple COFs, and then compensates for the SOUT on each COF within those multiple COFs. Figure 8 As shown, the drive module 401 includes COF1, COF2, COF3 and COF4, and each COF corresponds to multiple SOUTs (SOUT0 and SOUTn of each COF are shown in the figure).

[0142] The first step is to compensate for the SOUT of different COFs.

[0143] TCON instructs the detection module 402 to detect the SOUT at the same position in different COFs. TCON determines the compensation voltage based on the linear integral difference between the SOUTs of different COFs and compensates the data voltage output by the SOUT of the COF in the Nth frame.

[0144] For example, TCON instructs detection module 402 to detect SOUT0 in COF1, COF2, COF3, and COF4. If TCON receives data (2) of SOUT0 in COF2 in the Nth frame, then according to the compensation voltage, the voltage compensation for the data of SOUT0 in COF2 in the Nth frame is data (2) + A*Db. The specific implementation method is described in Case 2 of the above embodiment and will not be repeated here. The same applies to COF3 and COF4.

[0145] In the implementation of this application, the first step is used to solve the problem of inconsistent charging efficiency and potential cross-line mischarging issues caused by the difference in rising / falling rates of the SOUT at the same position between different COFs, thereby improving the brightness uniformity of the display area corresponding to different COFs.

[0146] The second step is to compensate for the SOUT within each COF.

[0147] TCON instructs the detection module 402 to detect all SOUTs within each COF. TCON compensates for each SOUT of each COF based on the calculated final compensation time.

[0148] For example, TCON instructs the detection module 403 to detect all SOUTs of COF1, and then, based on the calculated final compensation time, to perform timing advance or delay compensation on the time point at which each SOUT in COF1 outputs the data voltage of the N+1th frame. The specific implementation method is described in Case 1 of the above embodiment, and will not be repeated here. COF2, COF3, and COF4 are also compensated in the same way.

[0149] In the implementation of this application, the second step aims to solve the problem of inconsistent signal transmission delay caused by the difference in the length of the output channel traces within the same COF, optimize the charging time window, and effectively reduce the inter-row mischarging phenomenon caused by the delay difference.

[0150] By employing the aforementioned collaborative strategy of first performing cross-COF compensation and then performing internal COF compensation, the problems of insufficient charging efficiency, uneven brightness, and incorrect charging caused by differences in output channels in high refresh rate and large-size display panels can be more comprehensively solved, significantly improving display quality.

[0151] Based on the same inventive concept, this application also provides a display device. Since the display device in this embodiment includes the voltage adjustment circuit in the above embodiment, the display device in this embodiment has all the technical features and effects of the above voltage adjustment circuit embodiment. For details, please refer to the above embodiment, and it will not be repeated here.

[0152] Based on the same inventive concept, this application also provides a display panel. Since the display panel in this embodiment includes the display device in the above embodiment, the display panel in this embodiment has all the technical features and technical effects of the above-mentioned display device embodiments. For details, please refer to the above embodiments, and will not be repeated here.

[0153] It should be understood that in the description of this application and the appended claims, the terms "comprising," "including," "having," and any variations thereof are intended to cover non-exclusive inclusion and mean "including but not limited to," unless otherwise specifically emphasized.

[0154] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is used to describe the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0155] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.

[0156] Furthermore, it should be understood in the description of this application that the terms "longitudinal," "horizontal," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0157] In this application, unless otherwise expressly specified and limited, the terms "connection" and "linkage" should be interpreted broadly. For example, they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise expressly limited, those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0158] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein; features defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0159] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0160] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A compensation circuit, characterized in that, The circuit is applied to a display panel, which includes N rows × M columns of pixel units; the circuit includes: at least one driving module and a control module, each driving module corresponding to multiple output channels, and each output channel being used to provide data voltage to different pixel units in the same column; The control module is used to acquire delay information for each output channel corresponding to any one of the multiple drive modules; The control module is further configured to determine the compensation time Δt_total for each output channel based on the data voltage of the first and second frames of the pixel units in the same row and the delay information of each output channel, where Δt_total = Δt + k * ΔD, Δt is the delay information of each output channel, ΔD is the difference between the data voltage of the first and second frames, and k is the compensation coefficient. The compensation time is used to compensate for the time when each output channel outputs the data voltage in the second frame, so that the time when the data voltage is output in the second frame is advanced by Δt_total. The first frame and the second frame are adjacent frames; The delay information for each output channel is the time difference between the time it takes for the output channel to output data voltage and the time it takes for the reference output channel to output data voltage, wherein the time difference is the ratio of the voltage difference between the output channel and the reference output channel to the rate of change of the voltage output by the output channel.

2. The circuit according to claim 1, characterized in that, The circuit further includes a detection module and an analog-to-digital conversion module, wherein the analog-to-digital conversion module is connected between the detection module and the control module; The detection module is configured to detect the data voltage output by each output channel corresponding to any of the driving modules; and to determine the voltage difference between each output channel and the first output channel based on the data voltage output by each output channel, wherein the time of the output data voltage of the first output channel is a reference time for determining the delay information of each output channel; and to determine the delay information of each output channel based on the voltage difference between each output channel and the first output channel. The analog-to-digital converter module is used to convert the delay information into a digital signal.

3. The circuit according to claim 2, characterized in that, The detection module is specifically used to detect the data voltage of each output channel corresponding to any of the driving modules during the time period from the first moment to the second moment. The first moment is the moment when the first output channel starts outputting the data voltage, and the second moment is the moment when the first output channel stops outputting the data voltage.

4. The circuit according to any one of claims 1 to 3, characterized in that, The control module is further configured to determine the compensation time of each output channel based on the difference in data voltage between the first and second frames of the pixel units in the same row and the delay information of each output channel. The control module is also used to compensate for the time during which each output channel outputs the data voltage in the second frame, based on the compensation time.

5. The circuit according to claim 1, characterized in that, The plurality of drive modules include a first drive module and a second drive module; The detection module is also used to detect the linear integral of the data voltage output by the second output channel of the first driving module and the linear integral of the data voltage output by the second output channel of the second driving module during the first time period of the process of the data voltage from 0 to the common voltage, and to determine the linear integral difference. The second output channel in the first driving module and the second output channel in the second driving module are output channels with corresponding positions in the first driving module and the second driving module. The control module is further configured to compensate the data voltage output by the second output channel of the first drive module or the second drive module based on the linear integral difference.

6. The circuit according to claim 5, characterized in that, The first time period begins when the data voltage rises to a first voltage threshold, and ends when the data voltage rises to a second voltage threshold. The first voltage threshold is less than the second voltage threshold, and both the first voltage threshold and the second voltage threshold are determined by the common voltage.

7. The circuit according to claim 5, characterized in that, When the linear integral difference is greater than 0, the control module is used to compensate the data voltage output by the second output channel of the second drive module; When the linear integral difference is less than 0, the control module is used to compensate the data voltage output by the second output channel of the first drive module.

8. The circuit according to any one of claims 5 to 7, characterized in that, The control module is further configured to determine the compensation voltage based on the linear integral difference. The control module is further configured to compensate the data voltage output by the second output channel of the first drive module or the second drive module according to the compensation voltage.

9. A display panel, characterized in that, The display panel includes a display area and a non-display area, the display area includes a light-emitting layer, and the non-display area is connected to the compensation circuit as described in any one of claims 1 to 8.

10. A display device, characterized in that, The display device includes a power module and a display panel as described in claim 9, wherein the power module is used to provide power to the display panel.

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