Static random access memory and multi-bit multiplication single-bit calculation method and device thereof

Abstract

The application relates to a static random access memory and a multi-bit multiplication single-bit calculation method and device thereof, which comprises a weight storage circuit and an input-output circuit, the control ends of a plurality of weight storage units in the weight storage circuit are connected with corresponding word line ends, the first ends of the plurality of weight storage units are connected with a first bit line, the second ends of the plurality of weight storage units are connected with a second bit line, and the first control signal and the second control signal of the input-output circuit are generated according to corresponding weight values; the input-output circuit comprises a first input-output unit and a second input-output unit, and is used for receiving first input data and second input data; the first input-output unit generates first output data based on the first control signal and the first input data; and the second input-output unit generates second output data based on the second control signal and the second input data. Thus, the problem that the in-memory calculation parallelism is limited is solved, and the area utilization is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor storage and computing technology, and in particular to a static random access memory and a method and apparatus for multiplying multiple bits to a single bit. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of volatile embedded memory that retains data as long as power is applied. It features high access speed but high area overhead. Its traditional basic unit is a 6T structure, such as... Figure 1 As shown. When reading data, the bit line (BL, BLB) voltage is pre-charged to VDD / 2, activating the word line (WL) and sensing the bit line voltage; if the bit line voltage is higher than VDD / 2, the stored value W is 1, and if it is lower than VDD / 2, the stored value W is 0.

[0003] For in-memory computation, the SRAM principle is to store the weights in "W", with WL as the input excitation signal and BL as the output, thus realizing the "1×1" bit calculation of "W×WL=BL".

[0004] Unlike DRAM and Flash, SRAM is integrated with the processor to provide high-speed cache or temporary data storage. Therefore, how to achieve faster logic operations based on a smaller SRAM area is the key to promoting the development of in-memory computing. Summary of the Invention

[0005] This application provides a static random access memory and a method and device for multiplying multiple bits by a single bit, in order to solve the problem of limited parallelism in in-memory computing.

[0006] A first aspect of this application provides a static random access memory (SRAM), comprising: a weighted storage circuit and an input / output circuit. The weighted storage circuit includes multiple weighted storage units, each with a control terminal connected to a corresponding word line terminal. Each weighted storage unit has a first terminal connected to a first bit line and a second terminal connected to a second bit line. The weighted storage circuit generates a first control signal and a second control signal for the input / output circuit based on the weight value stored in each weighted storage unit. The input / output circuit includes a first input / output unit and a second input / output unit. The input / output circuit receives first input data and second input data. The first input / output unit generates first output data based on the first control signal and the first input data. The second input / output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data.

[0007] Optionally, a first MOSFET and a second MOSFET, a first inverter and a second inverter are configured such that the gates of both the first MOSFET and the second MOSFET are connected to the word line, the drain of the first MOSFET is connected to the first bit line, and the source of the first MOSFET is connected to the input of the first inverter and the output of the second inverter, respectively. The first MOSFET is used to read the inverted weight value stored in the corresponding weight storage unit. The source of the second MOSFET is connected to the output of the first inverter and the input of the second inverter, and the drain of the second MOSFET is connected to the second bit line. The second MOSFET is used to read the weight value stored in the corresponding weight storage unit.

[0008] Optionally, the first MOSFET is an NMOS transistor, and the second MOSFET is an NMOS transistor.

[0009] Optionally, the first input / output unit includes a third MOS transistor and a fourth MOS transistor, wherein the gate of the third MOS transistor is connected to the gate of the fourth MOS transistor and the first bit line, respectively; the source of the third MOS transistor and the fourth MOS transistor is used to receive the first input data; and the drain of the third MOS transistor and the fourth MOS transistor is used to generate the first output data by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal based on the first control signal.

[0010] Optionally, the second input / output unit includes a fifth MOS transistor and a sixth MOS transistor, wherein the gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor and the second bit line, respectively; the source of the fifth MOS transistor and the sixth MOS transistor is used to receive second input data; and the drain of the fifth MOS transistor and the sixth MOS transistor is used to generate second output data by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal based on the second control signal.

[0011] Optionally, the input / output circuit is further configured to: generate first output data by multiplying the first input data and the weight value stored in the weight storage unit of the first control signal based on the first control signal; and generate second output data by multiplying the second input data and the weight value stored in the weight storage unit of the second control signal based on the second control signal.

[0012] A second aspect of this application provides a multi-bit multiplication method based on a static random access memory (SRAM), employing the aforementioned SRAM, and includes the following steps: determining whether the input stimulus of the i-th word line of the SRAM is 1; if the input stimulus of the i-th word line is 1, then reading the weight value stored in the i-th weight storage unit and obtaining the N-bit data received by the input / output circuit of the SRAM; when the weight value stored in the i-th weight storage unit is 1, multiplying the weight value stored in the i-th weight storage unit by the N-bit data, and the input / output circuit outputs the result of the N-bit multiplication by the single bit; when the weight value stored in the i-th weight storage unit is 0, the input / output circuit outputs 0.

[0013] Optionally, when the weight value stored in the i-th weight storage unit is 1, the third and fourth MOS transistors in the first input / output unit are turned on, and the fifth and sixth MOS transistors in the second input / output unit are turned on; when the weight value stored in the i-th weight storage unit is 0, the third and fourth MOS transistors in the first input / output unit are turned off, and the fifth and sixth MOS transistors in the second input / output unit are turned off.

[0014] Optionally, after determining whether the input stimulus of the i-th word line of the static random access memory is 1, the method includes: if the input stimulus of the i-th word line is 0, then the weight value stored in the i-th weight storage unit is not read, and the method continues to determine whether the input stimulus of the (i+1)-th word line is 1.

[0015] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor executes the program to implement the multi-bit multiplication-to-single-bit calculation method based on static random access memory as described in the above embodiments.

[0016] A fourth aspect of this application provides a computer program product having a computer program stored thereon, which is executed by a processor to implement the multi-bit multiplication-to-single-bit calculation method based on static random access memory as described in the above embodiments.

[0017] In the above embodiments, the static random access memory (SRAM) includes a weighted storage circuit and an input / output circuit. The weighted storage circuit includes multiple weighted storage units, each with a control terminal connected to a corresponding word line terminal. The first terminal of each weighted storage unit is connected to a first bit line, and the second terminal is connected to a second bit line. This weighted storage unit generates a first control signal and a second control signal for the input / output circuit based on the weight value stored in each weighted storage unit. The input / output circuit includes a first input / output unit and a second input / output unit. The input / output circuit receives first input data and second input data. The first input / output unit generates first output data based on the first control signal and the first input data. The second input / output unit generates second output data based on the second control signal and the second input data, and outputs both the first and second output data. This solves the problem of limited in-memory computational parallelism and improves in-memory computational parallelism and area utilization.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the traditional 6T SRAM structure in related technologies; Figure 2 This is a schematic diagram of a split-word line SRAM structure in related technologies; Figure 3 This is a schematic diagram of a static random access memory provided according to an embodiment of this application; Figure 4 This is a flowchart of a multi-bit multiplication method based on static random access memory according to an embodiment of this application; Figure 5 This is a flowchart of a multi-bit multiplication method based on static random access memory (SRAM) according to an embodiment of this application. Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0021] The following description, with reference to the accompanying drawings, describes a static random access memory (SRAM) and its multi-bit multiplication method and apparatus according to embodiments of this application. Addressing the problem of limited in-memory computation parallelism mentioned in the background art, this application provides a SRAM comprising: a weight storage circuit and an input / output circuit. The weight storage circuit includes multiple weight storage units, each with a control terminal connected to a corresponding word line terminal. The first terminal of each weight storage unit is connected to a first bit line, and the second terminal is connected to a second bit line. This weight storage unit generates a first control signal and a second control signal for the input / output circuit based on the weight value stored in each weight storage unit. The input / output circuit includes a first input / output unit and a second input / output unit. The input / output circuit receives first input data and second input data. The first input / output unit generates first output data based on the first control signal and the first input data. The second input / output unit generates second output data based on the second control signal and the second input data, and outputs the first and second output data. This solves the problem of limited in-memory computation parallelism and improves in-memory computation parallelism and area utilization.

[0022] Regarding improving the in-memory computing speed of SRAM, existing technical solutions mainly involve splitting word lines to achieve parallel computing of multiple "1×1" bits, as shown in the circuit diagram below. Figure 2 As shown. The basic principle is that after the word line is precharged, WL[0] and WL[1] simultaneously provide input excitation, BL senses the voltage, W[0] is read from BL, and W[1] is read from BLB, thus realizing “1×1” bit dual parallelism calculation.

[0023] However, existing technical solutions applied to in-memory computing have two main problems: first, they can only handle "1×1" bit computation problems and cannot handle multiplication operations of multidimensional vectors and data; second, although the parallelism is improved, the area is not reduced, and the parallelism is at most doubled, resulting in limited overall performance improvement.

[0024] further, Figure 3 This is a schematic diagram of a static random access memory 10 provided in an embodiment of this application.

[0025] like Figure 3 As shown, the static random access memory 10 includes: a weighted storage circuit 100 and an input / output circuit 200, wherein, The weight storage circuit 100 includes multiple weight storage units. The control terminals of each weight storage unit are connected to the corresponding word line terminals. The first terminals of each weight storage unit are connected to the first bit line, and the second terminals of each weight storage unit are connected to the second bit line. It is used to generate a first control signal and a second control signal for the input / output circuit 200 based on the weight value stored in each weight storage unit. The input / output circuit 200 includes a first input / output unit and a second input / output unit. The input / output circuit 200 is used to receive first input data and second input data. The first input / output unit generates first output data based on the first control signal and the first input data. The second input / output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data.

[0026] Among them, specifically such as Figure 3 As shown, the word line terminal is WL, such as WL[0], WL[1]... The weight storage circuit 100 includes multiple weight storage units, each weight storage unit has a word line terminal, the first word line is BLB, the second word line is BL, the input data is an N-bit value, the first input data is a part of the N-bit value, and the second input data is another part of the N-bit value.

[0027] It is understandable that when the input stimulus at the word line is 1, that is, WL[i]=1, the weight value stored in the weight storage unit is retrieved. If the weight value is 1, the first control signal generated is 0, and the second control signal generated is 1. The first control signal is the control signal for multiplying the weight value by the first input data, and the second control signal is the control signal for multiplying the weight value by the second input data. At this time, the first output data and the second output data are the result of multiplying multiple bits by a single bit.

[0028] When the input stimulus at the word line is 0, i.e. WL[i]=0, the weight value stored in the weight storage unit is not retrieved, and the determination of whether WL[i+1] is 0 is continued.

[0029] Optionally, in some embodiments, the input / output circuit 200 is further configured to: generate first output data by multiplying the first input data and the weight value stored in the weight storage unit of the first control signal based on the first control signal; and generate second output data by multiplying the second input data and the weight value stored in the weight storage unit of the second control signal based on the second control signal.

[0030] It is understandable that after receiving the first input data, the first input / output unit multiplies the first input data by the weight value in the first control signal to obtain the first output data; after receiving the second input data, the second input / output unit multiplies the second input data by the weight value in the second control signal to obtain the second output data.

[0031] Optionally, in some embodiments, each of the multiple weight storage units includes: a first MOS transistor and a second MOS transistor, a first inverter and a second inverter, wherein the gates of the first MOS transistor and the second MOS transistor are both connected to the word line terminal, the drain of the first MOS transistor is connected to the first bit line, and the source of the first MOS transistor is connected to the input terminal of the first inverter and the output terminal of the second inverter, respectively. The first MOS transistor is used to read out the weight inverse code value stored in the corresponding weight storage unit; the source of the second MOS transistor is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the drain of the second MOS transistor is connected to the second bit line. The second MOS transistor is used to read out the weight value stored in the corresponding weight storage unit.

[0032] In some embodiments, the first MOS transistor is an NMOS transistor, and the second MOS transistor is an NMOS transistor.

[0033] It should be noted that the control terminal of the weighted storage unit is the gate of the first MOS transistor and the second MOS transistor, the first terminal of the weighted storage unit is the drain of the first MOS transistor, and the second terminal of the weighted storage unit is the drain of the second MOS transistor.

[0034] Optionally, in some embodiments, the first input / output unit includes a third MOS transistor and a fourth MOS transistor, wherein the gate of the third MOS transistor is connected to the gate of the fourth MOS transistor and the first bit line, respectively; the source of the third MOS transistor and the fourth MOS transistor are used to receive first input data; and the drain of the third MOS transistor and the fourth MOS transistor are used to generate first output data by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal based on the first control signal.

[0035] Optionally, in some embodiments, the second input / output unit includes a fifth MOS transistor and a sixth MOS transistor, wherein the gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor and the second bit line, respectively; the source of the fifth MOS transistor and the sixth MOS transistor is used to receive second input data; and the drain of the fifth MOS transistor and the sixth MOS transistor is used to generate second output data by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal based on the second control signal.

[0036] The first input / output unit has an input terminal IN (including IN1 and IN3) and an output terminal OUT (including OUT1 and OUT3). The second input / output unit has an input terminal IN (including IN0 and IN2) and an output terminal OUT (including OUT0 and OUT2). The weight value is represented by W, and the weight inverse code value is represented by Wb.

[0037] Understandably, the first input / output unit and the second input / output unit multiply each bit of the input N bits with the weight value in the corresponding first control signal and second control signal based on the corresponding first control signal and second control signal to generate the first output data and the second output data, which is the result of multi-bit multiplication by a single bit.

[0038] For example, as shown in Table 1, when WL[i]=1, the weight value W stored in the i-th weight storage unit is retrieved. If the weight value W=0, then Wb=1. Although the input / output circuit 100 receives the input N bits, the N bits are not multiplied with the weight value, and all output data is 0. When WL[i]=1, the weight value W stored in the i-th weight storage unit is retrieved. If W=1, then Wb=0, the first control signal is 0, and the second control signal is 1. The first output data is obtained by using the weight value W in the first control signal × the input N-bit value IN1=OUT1, and the second output data is obtained by using the weight value W in the second control signal × the input N-bit value IN2=OUT2. If WL[i]=0, then the weight value stored in the i-th weight storage unit is not retrieved, and the determination of whether WL[i+1] is 0 is continued.

[0039] To enable those skilled in the art to further understand the multi-bit multiplication method of the static random access memory 10 in the embodiments of this application, the following detailed description is provided in conjunction with specific embodiments.

[0040] (1) Principle of “N×1” bit calculation Taking N=4 as an example, the principle of multiplying 4 bits by 1 bit is explained. The circuit is as follows: Figure 3 As shown. Consistent with traditional SRAM, the weight value is stored in "W". After the output terminal OUT of the word line and input / output circuit 200 is precharged to VDD / 2, WL[0] is activated. The second word line BL and the first word line BLB will charge or discharge according to the data stored in the weight value "W" and the weight inverse code value "Wb". The charging and discharging results of BL and BLB will determine whether the input data "IN" value can be transmitted to "OUT". In this structure, the input / output circuit 200 realizes "W×IN=OUT". The input activation of the word line terminal WL only determines whether to retrieve the weight value "W" for calculation.

[0041] To ensure logical correctness, the second MOS transistor connected to "W" is an NMOS transistor, and the first MOS transistor connected to "Wb" is also an NMOS transistor. In one calculation cycle, if the input data is 4 bits, then the output data is also 4 bits, meaning that each input bit is multiplied by the single-bit weight "W" to output a 4-bit result.

[0042] (2) Verification of the correctness of computational logic The improved SRAM implementation of "N×1" bit operations is based on the weight value "W" and the weight inverse code value "Wb", and requires Boolean operations to analyze the correctness of its structural logic.

[0043] Let's analyze one specific scenario. If "W" = 1, the BL voltage is greater than VDD / 2, the NMOS transistor is on, IN0 = 0, OUT0 = 0, and W = 1, OUT0 = 1, so "W × IN0 = OUT0" holds true. In this case, "Wb" = 0, the BLB voltage is less than VDD / 2, the PMOS transistor is on, IN1 = 0, OUT1 = 0, and IN1 = 1, OUT1 = 1, so "W × IN1 = OUT1" holds true. The analysis for other scenarios follows the same process, all meeting the calculation requirement of "W × IN = OUT". The specific results are shown in Table 1.

[0044] Table 1

[0045] (3) Calculation process of “N×1” bit SRAM memory The overall calculation process is as follows: Figure 4 As shown. After prefilling the word line, the input stimulus of WL[i] at the word line end determines whether to read out the weight value "W" corresponding to W[i].

[0046] If the input stimulus at word line WL[i] is 1, then the weight value “W” corresponding to the i-th weight storage unit W[i] is read out; otherwise, it is not read out.

[0047] If the weight value "W" = 1, and the first input data is an N-bit IN value, then the generated first control signal is 0, and the generated second control signal is 1. The first input / output unit of the input / output circuit 200 multiplies each bit according to the weight value (i.e., W = 1) in the first control signal and outputs the first output data. The second input / output unit of the input / output circuit 200 multiplies each bit according to the weight value (i.e., W = 1) in the second control signal and outputs the second output data. The first output data and the second output data are the result of multiplying N bits by a single bit. After completion, it continues to determine whether the input excitation of the (i+1)th word line is 1, thereby determining whether to read the weight value stored in the next weight storage unit. If the weight value “W” = 0, then the input / output circuit 200 outputs 0.

[0048] Through the above process, the SRAM structure realizes multi-bit multiplication by single-bit operation within one cycle.

[0049] In summary, the beneficial effects of the embodiments of this application are as follows: This circuit structure achieves N×1 bit multiplication calculations without introducing significant area overhead by adding a small number of additional MOS transistors. Its core lies in utilizing the BLB word line for voltage sensing in the traditional SRAM readout mode, and adding PMOS transistors to ensure logic correctness. Simultaneously, the output result is no longer represented by bit line voltage (because there are at most two bit lines, with a maximum output of 2 bits), but rather by the additional readout transistors, allowing N bits of calculation results to be output within the same cycle. This structure provides a reasonable circuit implementation for fields requiring large-scale matrix calculations, such as deep learning and neural network training, improving in-memory computation efficiency.

[0050] According to the static random access memory (SRAM) proposed in this application, a weighted storage circuit and an input / output circuit are included. The weighted storage circuit comprises multiple weighted storage units, each with a control terminal connected to a corresponding word line terminal. The first terminal of each weighted storage unit is connected to a first bit line, and the second terminal is connected to a second bit line. These units are used to generate a first control signal and a second control signal for the input / output circuit based on the weight value stored in each weighted storage unit. The input / output circuit includes a first input / output unit and a second input / output unit. The input / output circuit receives first input data. The first input / output unit generates first output data based on the first control signal and the first input data. The second input / output unit generates second output data based on the second control signal and the first input data, and then outputs both the first and second output data. This solves the problem of limited in-memory computational parallelism and improves in-memory computational parallelism and area utilization.

[0051] Next, referring to the accompanying drawings, a multi-bit multiplication method based on a static random access memory (SRAM) is described according to an embodiment of this application.

[0052] Figure 5 This is a flowchart illustrating a multi-bit multiplication method based on static random access memory according to an embodiment of this application.

[0053] like Figure 5 As shown, the multi-bit multiplication method based on static random access memory includes the following steps: In step S501, it is determined whether the input stimulus of the i-th word line of the static random access memory is 1.

[0054] In step S502, if the input stimulus of the i-th word line is 1, then the weight value stored in the i-th weight storage unit is read, and the N bits of data received by the input / output circuit of the static random access memory are obtained.

[0055] In step S503, when the weight value stored in the i-th weight storage unit is 1, the input-output circuit outputs the result of multiplying the weight value stored in the i-th weight storage unit by N bits of data. When the weight value stored in the i-th weight storage unit is 0, the input-output circuit outputs 0.

[0056] Optionally, in some embodiments, the third and fourth MOS transistors in the first input / output unit are turned on, and the fifth and sixth MOS transistors in the second input / output unit are turned on; when the weight value stored in the i-th weight storage unit is 0, the third and fourth MOS transistors in the first input / output unit are turned off, and the fifth and sixth MOS transistors in the second input / output unit are turned off.

[0057] Optionally, in some embodiments, after determining whether the input stimulus of the i-th word line of the static random access memory is 1, the method includes: if the input stimulus of the i-th word line is 0, then the weight value stored in the i-th weight storage unit is not read, and the method continues to determine whether the input stimulus of the (i+1)-th word line is 1.

[0058] It should be noted that the foregoing explanation of the static random access memory embodiment also applies to the multi-bit multiplication of single-bit calculation method based on static random access memory in this embodiment, and will not be repeated here.

[0059] According to the multi-bit multiplication method based on static random access memory (SRAM) proposed in this application, it is determined whether the input stimulus of the i-th word line of the SRAM is 1. If the input stimulus of the i-th word line is 1, the weight value stored in the i-th weight storage unit is read, and the N-bit data received by the input / output circuit of the SRAM is obtained. When the weight value stored in the i-th weight storage unit is 1, the input / output circuit outputs the result of the N-bit multiplication by the single bit operation based on the multiplication of the weight value stored in the i-th weight storage unit with the N-bit data. When the weight value stored in the i-th weight storage unit is 0, the input / output circuit outputs 0. This solves the problem of limited parallelism in in-memory computation and improves the parallelism and area utilization of in-memory computation.

[0060] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include: The memory 601, the processor 602, and the computer program stored on the memory 601 and capable of running on the processor 602.

[0061] When the processor 602 executes the program, it implements the multi-bit multiplication method based on static random access memory provided in the above embodiments.

[0062] Furthermore, electronic devices also include: Communication interface 603 is used for communication between memory 601 and processor 602.

[0063] The memory 601 is used to store computer programs that can run on the processor 602.

[0064] The memory 601 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0065] If the memory 601, processor 602, and communication interface 603 are implemented independently, then the communication interface 603, memory 601, and processor 602 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0066] Optionally, in a specific implementation, if the memory 601, processor 602, and communication interface 603 are integrated on a single chip, then the memory 601, processor 602, and communication interface 603 can communicate with each other through an internal interface.

[0067] The processor 602 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0068] This application also provides a computer program product on which a computer program is stored. When the program is executed by a processor, it implements the above-described multi-bit multiplication-to-single-bit calculation method based on static random access memory.

[0069] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0071] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0072] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequential list of executable instructions for implementing logical functions, and can be specifically implemented in any computer program product for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer program product" can be any means that can contain, store, communicate, propagate, or transmit a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples of computer program products (a non-exhaustive list) include the following: an electrical connection having one or N wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, the computer program product can even be paper or other suitable medium on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0073] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0074] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer program product, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0075] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer program product.

[0076] The computer program product mentioned above may be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A static random access memory, characterized in that, include: Weight storage circuit and input / output circuit, wherein, The weight storage circuit includes multiple weight storage units. The control terminals of the multiple weight storage units are all connected to the corresponding word line terminals. The first terminals of the multiple weight storage units are all connected to the first bit line, and the second terminals of the multiple weight storage units are all connected to the second bit line. The weight storage circuit is used to generate the first control signal and the second control signal of the input-output circuit according to the weight value stored in each weight storage unit. The input / output circuit includes a first input / output unit and a second input / output unit. The input / output circuit is used to receive first input data and second input data. The first input / output unit generates first output data based on the first control signal and the first input data. The second input / output unit generates second output data based on the second control signal and the second input data, and outputs the first output data and the second output data. The first input / output unit includes: a third MOSFET and a fourth MOSFET, wherein, The gate of the third MOS transistor is connected to the gate of the fourth MOS transistor and the first bit line, respectively. The source of the third MOS transistor and the fourth MOS transistor are used to receive the first input data. The drain of the third MOS transistor and the fourth MOS transistor are used to generate the first output data by multiplying the first input data and the weight value stored in the weight storage unit in the first control signal based on the first control signal. The second input / output unit includes: a fifth MOSFET and a sixth MOSFET, wherein, The gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor and the second bit line, respectively. The source of the fifth MOS transistor and the sixth MOS transistor are used to receive the second input data. The drain of the fifth MOS transistor and the sixth MOS transistor are used to generate the second output data by multiplying the second input data and the weight value stored in the weight storage unit in the second control signal based on the second control signal.

2. The static random access memory according to claim 1, characterized in that, Each of the plurality of weighted storage units includes: The first MOSFET and the second MOSFET, the first inverter and the second inverter, wherein... The gates of the first MOS transistor and the second MOS transistor are both connected to the word line terminal. The drain of the first MOS transistor is connected to the first bit line. The source of the first MOS transistor is connected to the input terminal of the first inverter and the output terminal of the second inverter, respectively. The first MOS transistor is used to read out the weight inverse code value stored in the corresponding weight storage cell. The source of the second MOS transistor is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the drain of the second MOS transistor is connected to the second bit line. The second MOS transistor is used to read the weight value stored in the corresponding weight storage cell.

3. The static random access memory according to claim 2, characterized in that, The first MOS transistor is an NMOS transistor, and the second MOS transistor is an NMOS transistor.

4. The static random access memory according to claim 1, characterized in that, The input / output circuit is also used for: Based on the first control signal, the first output data is generated by multiplying the first input data and the weight value stored in the weight storage unit of the first control signal. Based on the second control signal, the second output data is generated by multiplying the second input data and the weight value stored in the weight storage unit of the second control signal.

5. A method for multiplying multiple bits into a single bit based on static random access memory, characterized in that, Using a static random access memory as described in any one of claims 1-4, wherein the method comprises the following steps: Determine whether the input stimulus of the i-th word line of the static random access memory is 1; If the input stimulus of the i-th word line is 1, then the weight value stored in the i-th weight storage unit is read, and the N bits of data received by the input / output circuit of the static random access memory are obtained. When the weight value stored in the i-th weight storage unit is 1, the input-output circuit outputs the result of multiplying the weight value stored in the i-th weight storage unit by the N-bit data. When the weight value stored in the i-th weight storage unit is 0, the input-output circuit outputs 0.

6. The method according to claim 5, characterized in that, When the weight value stored in the i-th weight storage unit is 1, the third and fourth MOS transistors in the first input / output unit are turned on, and the fifth and sixth MOS transistors in the second input / output unit are turned on; when the weight value stored in the i-th weight storage unit is 0, the third and fourth MOS transistors in the first input / output unit are turned off, and the fifth and sixth MOS transistors in the second input / output unit are turned off.

7. The method according to claim 5, characterized in that, After determining whether the input stimulus of the i-th word line of the static random access memory is 1, the process includes: If the input stimulus of the i-th word line is 0, then the weight value stored in the i-th weight storage unit is not read, and the input stimulus of the (i+1)-th word line is determined to be 1.

8. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the multi-bit multiplication-to-single-bit calculation method based on static random access memory as described in any one of claims 5-7.

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