Manufacturing method of TGBT device
By covering the photoresist on the second polysilicon layer and etching during the TGBT device production process, the etching process is optimized, and the void problem on the top of the deep trench polysilicon layer is solved, improving the reliability and yield of the device.
Patent Information
- Application Number
- CN202510477130.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-08-12
AI Technical Summary
Existing TGBT devices are prone to voids on the top circumference of the deep-trench polysilicon layer, resulting in low reliability and yield problems.
After forming a second polysilicon layer filled with deep trench, a photoresist is covered thereon and etched is performed to remove the photoresist and polysilicon layer outside the deep trench, and then the isolation layer on the top circumference of the second polysilicon layer is removed until the substrate is exposed, and the etching process is optimized by dry and wet etching processes.
The top depressions and sharp angles of the deep trench polysilicon layer are reduced, the generation of voids is reduced, and the reliability and yield of the device are improved.
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Figure CN120475728A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for manufacturing a TGBT device. Background Art
[0002] Using a trident-gate bipolar transistor (TGBT) device with a double shield gate trench (SGT) structure to replace a trench metal-oxide-semiconductor field-effect transistor (trench MOS) device can achieve smaller device capacitance, faster switching speed, and lower switching loss, thus gaining widespread application.
[0003] refer to Figures 1 to 3 , which shows a schematic diagram of the filling process of the gate of the TGBT device provided in the related art. Figure 1 , which shows a cross-sectional schematic diagram after forming a polysilicon layer filling a deep trench, for example, Figure 1 As shown, a trench 1010 is formed in the substrate 110, which includes a deep trench 1011 and shallow trenches 1012 and 1013 located on both sides of the deep trench 1011 and connected to the deep trench 1011, first polysilicon layers 1411 and 1412 are formed in the shallow trenches 1012 and 1013, and a first isolation layer 121 is formed between the shallow trenches 1012 and 1013 and the first polysilicon layers 1411 and 1412. A second isolation layer 122 is formed on the surface of the substrate 110, the first polysilicon layers 1411 and 1412, and the deep trench 1011, and a second polysilicon layer 1310 can be deposited to fill the deep trench 1011.
[0004] refer to Figure 2 , which shows a cross-sectional schematic diagram after etching the second polysilicon layer 1310. For example, Figure 2 As shown, after the second polysilicon layer 1310 is etched by a dry etching process, the second polysilicon layer 1310 in other areas except the deep trench 1011 is removed, as shown in FIG. Figure 2 As shown in the area circled by the middle dotted line, the top of the second polysilicon layer 1310 in the deep trench 1011 has a V-shaped recessed morphology.
[0005] refer to Figure 3 , which shows a cross-sectional schematic diagram after the isolation layer on the substrate surface is removed. Figure 3As shown, the second isolation layer 122 can be etched by a dry etching process to remove the second isolation layer 122 in other areas outside the trench 1010. Since a V-shaped depression exists on the top of the second polysilicon layer 1310 after etching, the V-shaped depression on the top of the second polysilicon layer 1310 becomes sharper after this etching (as shown in FIG. Figure 3 In addition, voids are easily generated around the recessed area during the subsequent insulation layer filling process. As a result, after the subsequent insulation layer filling and contact holes (CT) are formed, the metal constituting the contact holes has a certain probability of penetrating into the voids, causing the source and gate to be connected when the device is working, thereby affecting the reliability and yield of the device product. Summary of the Invention
[0006] The present application provides a method for manufacturing a TGBT device, which can solve the problem of low reliability and yield caused by the generation of gaps around the top side of the polysilicon layer of the deep trench in the manufacturing method of the TGBT device provided in the related art. The method comprises:
[0007] A substrate is provided, wherein a trench is formed in the substrate, the trench including a deep trench and shallow trenches located on both sides of the deep trench and connected thereto, a first polysilicon layer is formed in the shallow trench, a first isolation layer is formed between the shallow trench and the first polysilicon layer, and a second isolation layer is formed on surfaces of the substrate, the first polysilicon layer, and the deep trench;
[0008] forming a second polysilicon layer on the second isolation layer, wherein the second polysilicon layer fills the deep trench;
[0009] covering the second polysilicon layer with a photoresist;
[0010] Performing etching to remove the photoresist and the second polysilicon layer in areas other than the deep trench, with the top of the remaining second polysilicon layer being lower than the top of the second isolation layer;
[0011] performing etching to remove the second isolation layer in a predetermined area around the top of the second polysilicon layer;
[0012] Etching is performed until the substrate in areas other than the trench is exposed.
[0013] In some embodiments, the etching to remove the photoresist and the second polysilicon layer in areas other than the deep trench includes:
[0014] A dry etching process is performed to remove the photoresist and the second polysilicon layer in areas other than the deep trench.
[0015] In some embodiments, the etching to remove the second isolation layer in a predetermined area around the top of the second polysilicon layer includes:
[0016] The second isolation layer in a predetermined area around the top of the second polysilicon layer is removed by etching using a wet etching process.
[0017] In some embodiments, etching until other areas of the substrate outside the trench are exposed includes:
[0018] Etching is performed using a dry etching process until the substrate in other areas outside the trench is exposed.
[0019] In some embodiments, the first isolation layer and the second isolation layer include silicon dioxide layers.
[0020] The technical solution of this application has at least the following advantages:
[0021] In the process of manufacturing the TGBT device, after forming a second polysilicon layer filling the deep trench, the second polysilicon layer is first covered with a photoresist and then etched, so that the depression of the top of the second polysilicon layer in the deep trench is smaller after etching. At the same time, by removing part of the isolation layer on the peripheral side of the top of the second polysilicon layer in the deep trench, the sharp corner of the top of the second polysilicon layer can be cut off in the subsequent etching process, thereby reducing the generation of gaps on the peripheral side and improving the reliability and yield of the device product. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0023] Figures 1 to 3 It is a schematic diagram of the gate filling process of the TGBT device;
[0024] Figure 4 is a flow chart of a method for manufacturing a TGBT device provided by an exemplary embodiment of the present application;
[0025] Figures 5 to 9 It is a schematic diagram of a manufacturing process of a TGBT device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0026] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0027] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0028] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0029] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0030] refer to Figure 4 , which shows a flow chart of a method for manufacturing a TGBT device provided by an exemplary embodiment of the present application, as shown in FIG. Figure 4 As shown, the method includes:
[0031] Step S1, providing a substrate, in which a groove is formed, the groove including a deep groove and shallow grooves located on both sides of the deep groove and connected to the deep groove, a first polysilicon layer is formed in the shallow groove, a first isolation layer is formed between the shallow groove and the first polysilicon layer, and a third isolation layer is formed on the substrate, the first polysilicon layer and the surface of the deep groove.
[0032] Step S2 , forming a second polysilicon layer on the second isolation layer, wherein the second polysilicon layer fills the deep trench.
[0033] refer to Figure 5 , which shows a cross-sectional schematic diagram after forming the second polysilicon layer. Figure 5As shown, a trench 2010 is formed in the substrate 210, which includes a deep trench 2011 and shallow trenches 2012 and 2013 located on both sides of the deep trench 2011 and connected thereto (the depths of the shallow trenches 2012 and 2013 are less than the depth of the deep trench 2011), a first polysilicon layer is formed in the shallow trench (a first polysilicon layer 2411 is formed in the shallow trench 2012, and a first polysilicon layer 2412 is formed in the shallow trench 2013), a first isolation layer is formed between the shallow trench and the first polysilicon layer (a first isolation layer 221 is formed between the trench 2012 and the first polysilicon layer 2411, and a first isolation layer 221 is formed between the shallow trench 2013 and the first polysilicon layer 2412), and a second isolation layer 222 is formed on the substrate 210, the first polysilicon layer and the surface of the deep trench. The second polysilicon layer 2310 may be formed by a chemical vapor deposition process in a furnace.
[0034] The first polysilicon layers 2411 and 2412 may be formed by depositing polysilicon layers and then etching them in the same process; the first isolation layer 221 and the second isolation layer 222 include silicon dioxide (SiO 2 ) layers.
[0035] Step S3: covering the second polysilicon layer with a photoresist.
[0036] Step S4 , performing etching to remove the photoresist and the second polysilicon layer in areas other than the deep trench, with the top of the remaining second polysilicon layer being lower than the top of the second isolation layer.
[0037] refer to Figure 6 , which shows a cross-sectional schematic diagram after covering the second polysilicon layer with photoresist; Figure 7 , which shows a cross-sectional schematic diagram after etching away the photoresist and the second polysilicon layer in areas other than the deep trench. Figure 6 and Figure 7 As shown, the photoresist 301 can be covered on the second polysilicon layer 2310 by spin coating, and the photoresist 301 and the second polysilicon layer 2310 in other areas except the deep trenches 2011 and 2012 can be removed by dry etching. Figure 7 As shown in the area circled by the middle dotted line, after etching through the covering photoresist 301, the top of the second polysilicon layer 2310 in the deep trenches 2011 and 2012 has a smaller depression and a better morphology, so that the sharp corners formed in the subsequent etching will have smaller sharpness.
[0038] Step S5 , performing etching to remove the second isolation layer in a predetermined area around the top of the second polysilicon layer.
[0039] refer to Figure 8 , which shows a cross-sectional schematic diagram after etching away the second isolation layer in a predetermined area around the top of the second polysilicon layer. Figure 8 As shown, a wet etching process can be used to remove the second isolation layer 222 in a predetermined area around the top of the second polysilicon layer 2310 , so that the top of the second polysilicon layer 2310 is higher than the second isolation layer 222 around it.
[0040] Step S6: performing etching until the substrate in areas other than the trench is exposed.
[0041] refer to Figure 9 , which shows a cross-sectional schematic diagram of the substrate after etching until the substrate other than the trench is exposed. Figure 9 As shown, etching is performed by a dry etching process until the substrate 210 in other areas outside the trench 2010 is exposed. After the second polysilicon layer is etched after covering the photoresist in steps S3 and S4, the top of the remaining second polysilicon layer 2310 is less concave, and the sharpness of the sharp corner formed in the etching process of step S6 is less. In step S5, the top of the remaining second polysilicon layer 2310 is made higher than the second isolation layer 222 on the peripheral side, so that the sharp corner on the top of the second polysilicon layer can be more thoroughly cut off in the etching process of step S6, reducing the generation of gaps on the peripheral side (such as Figure 9 (shown in the area circled by the dotted line).
[0042] To sum up, in the embodiment of the present application, during the manufacturing process of the TGBT device, after forming the second polysilicon layer filling the deep trench, the second polysilicon layer is first covered with a photoresist and then etched, so that the depression of the top of the second polysilicon layer in the deep trench is smaller after etching. At the same time, by removing part of the isolation layer on the peripheral side of the top of the second polysilicon layer in the deep trench, the sharp corners of the top of the second polysilicon layer can be cut off in the subsequent etching process, thereby reducing the generation of gaps on its peripheral side and improving the reliability and yield of the device product.
[0043] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for manufacturing a TGBT device, characterized in that: include: A substrate is provided, wherein a trench is formed in the substrate, the trench including a deep trench and shallow trenches located on both sides of the deep trench and connected thereto, a first polysilicon layer is formed in the shallow trench, a first isolation layer is formed between the shallow trench and the first polysilicon layer, and a second isolation layer is formed on surfaces of the substrate, the first polysilicon layer, and the deep trench; forming a second polysilicon layer on the second isolation layer, wherein the second polysilicon layer fills the deep trench; covering the second polysilicon layer with a photoresist; Performing etching to remove the photoresist and the second polysilicon layer in areas other than the deep trench, with the top of the remaining second polysilicon layer being lower than the top of the second isolation layer; performing etching to remove the second isolation layer in a predetermined area around the top of the second polysilicon layer; Etching is performed until the substrate in areas other than the trench is exposed.
2. The method according to claim 1, characterized in that The etching to remove the photoresist and the second polysilicon layer in areas other than the deep trench includes: A dry etching process is performed to remove the photoresist and the second polysilicon layer in areas other than the deep trench.
3. The method according to claim 2, characterized in that The etching to remove the second isolation layer in a predetermined area around the top of the second polysilicon layer includes: The second isolation layer in a predetermined area around the top of the second polysilicon layer is removed by etching using a wet etching process.
4. The method according to claim 3, characterized in that The etching is performed until the substrate in other areas outside the trench is exposed, comprising: Etching is performed using a dry etching process until the substrate in other areas outside the trench is exposed.
5. The method according to any one of claims 1 to 4, characterized in that: The first isolation layer and the second isolation layer include silicon dioxide layers.