Method for improving gate oxide morphology

Abstract

The application provides a method for improving the morphology of a gate oxide layer, which comprises the following steps: providing a semiconductor structure, which comprises a substrate, a trench formed in the substrate, a field oxide layer formed on the bottom and sidewall of the trench and extending to the surface of the substrate, and the field oxide layer is an ONO layer structure, which comprises a bottom oxide layer, an intermediate nitride layer and a top oxide layer from bottom to top; forming a source polysilicon layer in the trench, and the thickness of the source polysilicon layer is less than the depth of the trench; etching to remove the exposed part of the top oxide layer above the source polysilicon layer; forming a tunneling oxide layer in the trench, and the sum of the thickness of the tunneling oxide layer and the polysilicon layer is less than the depth of the trench; etching to remove the exposed remaining thickness of the top oxide layer above the tunneling oxide layer and the intermediate nitride layer and the bottom oxide layer below the top oxide layer; and forming a gate oxide layer on the surface of the tunneling oxide layer and the sidewall of the trench. The application solves the problem of defects in the morphology of the gate oxide layer formed by the existing method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for improving the morphology of gate oxide layers. Background Technology

[0002] SGT (Shielded Gate Transistor) MOSFETs are primarily used in medium and low voltage applications. Some SGT processes require a relatively thick ONO layer (approximately...). It can be used as field oxygen to improve the pressure resistance level.

[0003] When removing the ONO layer and regenerating the gate oxide layer, a three-step wet etching process is required to remove the field oxygen near the top of the trench. During this process, the wet etching time is limited because if the etching time is too short (below 8 minutes), the field oxygen at the top cannot be completely removed, resulting in a stepped morphology of the subsequently formed gate oxide layer (e.g., ...). Figure 1 As shown), this results in the inability to meet mass production requirements; if the etching time is too long (more than 9 minutes), the thickness of the tunneling oxide layer formed on the surface of the polysilicon layer will be too thin (thickness less than...). This can lead to the failure of the device's IGSS parameters. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the morphology of the gate oxide layer, so as to solve the problem of defects in the morphology of the gate oxide layer formed by the existing method.

[0005] To achieve the above and other related objectives, the present invention provides a method for improving the morphology of a gate oxide layer, the method comprising:

[0006] A semiconductor structure is provided, including a substrate, a trench formed in the substrate, a field oxide layer formed at the bottom and sidewalls of the trench and extending to the surface of the substrate, wherein the field oxide layer is an ONO stacked structure and includes a bottom oxide layer, an intermediate nitride layer and a top oxide layer from bottom to top.

[0007] A source polysilicon layer is formed within the trench, and the thickness of the source polysilicon layer is less than the depth of the trench;

[0008] Etching removes the portion of the top oxide layer exposed above the source polysilicon layer;

[0009] A tunneling oxide layer is formed in the trench, and the sum of the thicknesses of the tunneling oxide layer and the polysilicon layer is less than the depth of the trench;

[0010] The remaining thickness of the top oxide layer exposed above the tunneling oxide layer and the intermediate nitride layer and the bottom oxide layer below it are removed by step etching.

[0011] A gate oxide layer is formed on the surface of the tunneling oxide layer and the sidewalls of the trench.

[0012] Optionally, the thickness of the bottom oxide layer includes The thickness of the intermediate nitriding layer includes The thickness of the top oxide layer includes

[0013] Optionally, the thickness of the bottom oxide layer is The thickness of the intermediate nitriding layer is The thickness of the top oxide layer is

[0014] Optionally, a wet etching process can be used to remove a portion of the thickness of the top oxide layer.

[0015] Optionally, the thickness of the removed top oxide layer is

[0016] Optionally, the remaining thickness of the top oxide layer, the intermediate nitrided layer, and the bottom oxide layer is removed by wet process.

[0017] Optionally, the top oxide layer and the bottom oxide layer are made of silicon oxide; the intermediate nitride layer is made of silicon nitride.

[0018] Optionally, the thickness of the tunneling oxide layer is

[0019] Optionally, the top oxide layer is formed using a sub-atmospheric pressure chemical vapor deposition process.

[0020] Optionally, the bottom oxide layer, the tunneling oxide layer, and the gate oxide layer are formed using a thermal oxidation process.

[0021] Optionally, the method further includes the step of forming a gate polysilicon layer in the trench, wherein the gate polysilicon layer is formed on the surface of the gate oxide layer.

[0022] As described above, the method for improving the gate oxide morphology of the present invention adds a wet etching process before the formation of the tunnel oxide layer to pre-clean the area. The top oxide layer on the left and right sides is used to shorten the etching time of the remaining thickness of the top oxide layer after the tunneling oxide layer is formed. This method reduces the etching of the tunneling oxide layer during the removal of the ONO stack structure, ensuring that the thickness of the tunneling oxide layer meets the requirements (approximately...). Furthermore, it can improve the morphology of the gate oxide layer while ensuring the IGSS parameters. Attached Figure Description

[0023] Figure 1 The image shown is an electron microscope image of the semiconductor structure of the existing stepped gate oxide layer.

[0024] Figure 2 The diagram shows a cross-sectional view of a semiconductor structure with trenches.

[0025] Figure 3 The diagram shows a cross-sectional view of the semiconductor structure after the formation of the source polycrystalline silicon layer.

[0026] Figure 4 The diagram shows a cross-sectional view of the semiconductor structure after removing a portion of the top oxide layer.

[0027] Figure 5 The diagram shows a cross-sectional view of the semiconductor structure after the formation of the tunnel oxide layer.

[0028] Figure 6 The diagram shows a cross-sectional view of the semiconductor structure after the ONO stack-up structure has been removed.

[0029] Figure 7 The diagram shows a cross-sectional view of the semiconductor structure after the gate oxide layer has been formed.

[0030] Figure 8 The diagram shows a cross-sectional view of the semiconductor structure after the formation of the gate polysilicon layer.

[0031] Figure 9 The flowchart shown is a method for improving the morphology of the gate oxide layer according to the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] like Figure 9 As shown, this embodiment provides a method for improving the morphology of a gate oxide layer, the method comprising:

[0035] A semiconductor structure is provided, including a substrate, a trench formed in the substrate, a field oxide layer formed at the bottom and sidewalls of the trench and extending to the surface of the substrate, wherein the field oxide layer is an ONO stacked structure and includes a bottom oxide layer, an intermediate nitride layer and a top oxide layer from bottom to top.

[0036] A source polysilicon layer is formed within the trench, and the thickness of the source polysilicon layer is less than the depth of the trench;

[0037] Etching removes the portion of the top oxide layer exposed above the source polysilicon layer;

[0038] A tunneling oxide layer is formed in the trench, and the sum of the thicknesses of the tunneling oxide layer and the polysilicon layer is less than the depth of the trench;

[0039] The remaining thickness of the top oxide layer exposed above the tunneling oxide layer and the intermediate nitride layer and the bottom oxide layer below it are removed by step etching.

[0040] A gate oxide layer is formed on the surface of the tunneling oxide layer and the sidewalls of the trench.

[0041] Specifically, the thickness of the bottom oxide layer includes The thickness of the intermediate nitriding layer includes The thickness of the top oxide layer includes

[0042] More specifically, the thickness of the bottom oxide layer is The thickness of the intermediate nitriding layer is The thickness of the top oxide layer is

[0043] Specifically, the top oxide layer and the bottom oxide layer are made of silicon oxide; the intermediate nitride layer is made of silicon nitride.

[0044] Specifically, the top oxide layer is formed using a sub-atmospheric pressure chemical vapor deposition process.

[0045] Specifically, the bottom oxide layer, the tunneling oxide layer, and the gate oxide layer are formed using a thermal oxidation process.

[0046] Specifically, a wet etching process is used to remove a portion of the top oxide layer.

[0047] More specifically, the thickness of the removed top oxide layer is like Figure 4As shown, in this embodiment, the thickness of the top oxide layer removed by wet method is...

[0048] Specifically, the thickness of the tunneling oxide layer is like Figure 5 As shown, in this embodiment, the thickness of the tunneling oxide layer is...

[0049] Specifically, the remaining thickness of the top oxide layer, the intermediate nitrided layer, and the bottom oxide layer is removed by wet process.

[0050] In this embodiment, the time used to remove the remaining thickness of the top oxide layer by wet etching is 8 minutes and 10 seconds.

[0051] Specifically, the method further includes the step of forming a gate polysilicon layer in the trench, wherein the gate polysilicon layer is formed on the surface of the gate oxide layer.

[0052] In summary, the method for improving the gate oxide morphology of the present invention adds a wet etching process before the formation of the tunneling oxide layer to pre-clean the area. The top oxide layer on the left and right sides is used to shorten the etching time of the remaining thickness of the top oxide layer after the tunneling oxide layer is formed. This method reduces the etching of the tunneling oxide layer during the removal of the ONO stack structure, ensuring that the thickness of the tunneling oxide layer meets the requirements (approximately...). Furthermore, it can improve the morphology of the gate oxide layer while maintaining the IGSS parameters. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the morphology of a gate oxide layer, characterized in that, The method includes: A semiconductor structure is provided, including a substrate, a trench formed in the substrate, a field oxide layer formed at the bottom and sidewalls of the trench and extending to the surface of the substrate, wherein the field oxide layer is an ONO stacked structure and includes a bottom oxide layer, an intermediate nitride layer and a top oxide layer from bottom to top. A source polysilicon layer is formed within the trench, and the thickness of the source polysilicon layer is less than the depth of the trench; Etching removes the portion of the top oxide layer exposed above the source polysilicon layer; A tunneling oxide layer is formed in the trench, and the sum of the thicknesses of the tunneling oxide layer and the polysilicon layer is less than the depth of the trench; The remaining thickness of the top oxide layer exposed above the tunneling oxide layer and the intermediate nitride layer and the bottom oxide layer below it are removed by step etching. A gate oxide layer is formed on the surface of the tunneling oxide layer and the sidewalls of the trench.

2. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The thickness of the bottom oxide layer includes The thickness of the intermediate nitriding layer includes The thickness of the top oxide layer includes 3. The method for improving the morphology of the gate oxide layer according to claim 2, characterized in that, The thickness of the bottom oxide layer is The thickness of the intermediate nitriding layer is The thickness of the top oxide layer is 4. The method for improving the morphology of the gate oxide layer according to claim 2, characterized in that, A portion of the top oxide layer is removed using a wet etching process.

5. The method for improving the morphology of the gate oxide layer according to claim 4, characterized in that, The thickness of the removed top oxide layer is 6. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The remaining thickness of the top oxide layer, the intermediate nitrided layer, and the bottom oxide layer is removed by wet process.

7. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The top oxide layer and the bottom oxide layer are made of silicon oxide; the intermediate nitride layer is made of silicon nitride.

8. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 9. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The top oxide layer is formed using a sub-atmospheric pressure chemical vapor deposition process.

10. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The bottom oxide layer, the tunneling oxide layer, and the gate oxide layer are formed using a thermal oxidation process.

11. The method for improving the morphology of the gate oxide layer according to claim 1, characterized in that, The method further includes the step of forming a gate polysilicon layer in the trench, wherein the gate polysilicon layer is formed on the surface of the gate oxide layer.

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