Floating ground generation circuit in high voltage applications and control method thereof

Abstract

This invention discloses a floating ground generation circuit and its control method for high-voltage applications. The circuit includes a coarse-adjustment ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, a regulating transistor NM1, and a current adaptive regulation circuit. The coarse-adjustment ground generation circuit generates a voltage HVSS based on the power supply voltage VDD. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and voltage HVSS. The non-inverting input of the low-voltage error amplifier EA is connected to the reference voltage VREF, and the inverting input of the low-voltage error amplifier EA is connected to the output of the feedback resistor network. The output of the error amplifier EA is connected to the gate of the regulating transistor NM1 and the input of the current adaptive regulation circuit. The output of the current adaptive regulation circuit generates an output voltage VOUT. This invention's floating ground generation circuit simultaneously meets the design requirements of small area and low power consumption.

Description

Technical Field

[0001] This invention relates to a floating ground generation circuit and its control method, particularly a floating ground generation circuit and its control method for high voltage applications, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In applications such as automotive electronics and industrial control, systems typically need to handle high input voltages (e.g., 12V or 48V DC power supplies). However, the internal functional modules of a chip often cannot operate directly within such a high voltage range, making power supply voltage conversion circuits particularly important. Depending on the specific requirements, there are two approaches to power supply voltage conversion: one is to generate a lower power supply voltage, denoted as LVDD, with the internal module operating between LVDD and system ground; the other is to generate a ground voltage with a fixed voltage difference from the power supply voltage, denoted as HVSS, with the internal module operating between the system power supply and HVSS. Taking a high-side switch application as an example, when the switch is on, the output voltage is close to the power supply voltage. If the internal module uses a low power supply voltage, there will still be withstand voltage issues. In this case, it is necessary to convert the operating voltage range of the internal circuit to the higher rail, i.e., between the power supply voltage and internal ground. Therefore, using a floating reference ground generation circuit is more efficient.

[0003] Figure 3 This is an existing high-voltage ground voltage generation circuit, derived from a low-dropout linear regulator (LDO). The input voltage VDD is typically the high-voltage power supply voltage, VREF is a temperature-independent reference voltage generated by the reference, M0 is the high-voltage regulating transistor, and EA is the error amplifier, operating between VDD and GND. The output voltage VOUT is determined by feedback resistors R1 and R2. While this structure is simple to implement, because VDD is a high-voltage power supply with a wide input range, the reference and bias circuits, as well as the error amplifier, require many high-voltage components, significantly increasing the area required. To reduce the use of high-voltage components, a more efficient approach can be adopted... Figure 4 The circuit shown is used in this circuit. The error amplifier operates between VDD and VOUT, thus eliminating the need for high-voltage components and significantly saving space. NM1 is the regulating transistor, and NM4 is a high-voltage transistor whose drain-source voltage withstands is higher than the maximum voltage of VDD. NM2 and NM3 are current mirrors; NM3 is n times the size of NM2. If the current flowing through NM2 is I0, theoretically the current flowing through NM3 is n*I0. Although this circuit is similar to... Figure 3 Compared to the previous circuit, the number of high-voltage transistors used is significantly reduced. However, when the load circuit is not working, the current on NM3 is still equal to n*I0, which will generate a lot of power consumption, which contradicts the current low-power design of the circuit.

[0004] Therefore, in order to meet the design requirements of small area and low power consumption at the same time, there is a need for a high-voltage floating ground generation circuit that requires less high-voltage transistors and whose power consumption can be adjusted with the load current. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a floating ground generation circuit and its control method in high voltage applications, which simultaneously meets the design requirements of small area and low power consumption.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A floating ground generation circuit for high-voltage applications includes a coarse ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, a regulating transistor NM1, and a current adaptive regulation circuit. The coarse ground generation circuit generates a voltage HVSS based on the power supply voltage VDD. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and the voltage HVSS. The non-inverting input of the low-voltage error amplifier EA is connected to the reference voltage VREF, and the inverting input of the low-voltage error amplifier EA is connected to the output of the feedback resistor network. The output of the error amplifier EA is connected to the gate of the regulating transistor NM1 and the input of the current adaptive regulation circuit. The drain of the regulating transistor NM1 is connected to the power supply voltage VDD, and the source of the regulating transistor NM1 is connected to the output of the current adaptive regulation circuit to generate an output voltage VOUT. The feedback resistor network divides the power supply voltage VDD and the output voltage VOUT for output.

[0007] Furthermore, the coarse ground generation circuit includes PMOS transistors PM2 and PM3, NMOS transistor NM6, high-voltage NMOS transistors NM7 and NM8, current source I1, and current source I2. The source of PMOS transistor PM2 and the drain of NMOS transistor NM6 are connected to the power supply voltage VDD. The gate of PMOS transistor PM2 is connected to the drain of PMOS transistor PM2 and the source of PMOS transistor PM3. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3. The gate of NMOS transistor NM6 is connected to the drain of high-voltage NMOS transistor NM7. The source of NMOS transistor NM6 is connected to the drain of high-voltage NMOS transistor NM8 and generates a voltage HVSS. The gates of high-voltage NMOS transistor NM7 and NM8 are connected to the enable signal EN. The source of high-voltage NMOS transistor NM7 is connected to one end of current source I1. The source of high-voltage NMOS transistor NM8 is connected to one end of current source I2. The other ends of current sources I1 and I2 are grounded.

[0008] Furthermore, the current adaptive regulation circuit includes an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5, and a current source I0. One end of the current source I0 is connected to the power supply voltage VDD, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 serves as the input terminal of the current adaptive regulation circuit and is connected to the output terminal of the low-voltage error amplifier EA and the gate of the regulating transistor NM1. The source of the NMOS transistor NM2... The high-voltage NMOS transistor NM5 is connected to its drain and serves as the output terminal of the current adaptive regulation circuit to generate the output voltage VOUT. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage HVSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of NMOS transistor NM3, the gate of NMOS transistor NM3, and the gate of NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of NMOS transistor NM4. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.

[0009] Furthermore, the width-to-length ratio of the adjustment tube NM1 and the NMOS tube NM2 is m:1.

[0010] Furthermore, the width-to-length ratio of the NMOS transistors NM4 and NMOS transistors NM3 is n:1.

[0011] Furthermore, the feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VDD, and the other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the feedback resistor network. The other end of resistor R2 is connected to the output voltage VOUT.

[0012] A control method for a floating ground generation circuit in a high-voltage application includes the following steps: The coarse adjustment ground generation circuit provides ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, NMOS transistors NM7 and NM8 are turned on, the gate-source voltage of PMOS transistor PM2 is |VGS1|, the gate-source voltage of PMOS transistor PM3 is |VGS2|, and the gate-source voltage of NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS = VDD - |VGS1| - |VGS2| - VGS3; The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. VREF is connected to the non-inverting input of EA and, through a feedback resistor network consisting of resistors R1 and R2 and the regulating transistor NM1, yields a precise output voltage VOUT. The output voltage VOUT is expressed as: ; When the power supply voltage VDD is powered on, the enable signal EN becomes high. First, the coarse adjustment generates the circuit output voltage HVSS. The voltage HVSS provides the ground voltage for the reference voltage circuit. Then, the feedback resistor network, low-voltage error amplifier EA, regulating transistor NM1 and current adaptive adjustment circuit start to work. Finally, the output voltage VOUT is the precise floating reference ground voltage with a fixed voltage difference from the power supply voltage VDD. The operating range of the reference voltage circuit is from the power supply voltage VDD to the voltage HVSS, and the operating range of the low-voltage error amplifier EA is from the power supply voltage VDD to the output voltage VOUT. The voltage difference between the operating ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, and no high-voltage transistor is required. The current I0 generated by the current source I0 is divided into two paths, flowing to NMOS transistor NM2 and high-voltage PMOS transistor PM1 respectively. Let the current flowing through NMOS transistor NM2 be I1 and the current flowing through high-voltage PMOS transistor PM1 be I2, then I0 = I1 + I2. Since the width-to-length ratio of the regulating transistor NM1 and NMOS transistor NM2 is m:1, the current flowing through the regulating transistor NM1 is m*I1. The current flowing through NMOS transistor NM3 is equal to the current I2 flowing through high-voltage PMOS transistor PM1. At the same time, since the width-to-length ratio of NMOS transistor NM4 and NMOS transistor NM3 is n:1, the current flowing through NMOS transistor NM4 is n*I2. The load operates between the power supply voltage VDD and the output voltage VOUT. The load current is IL. The current flowing through NMOS transistor NM4 is equal to the sum of the current I1 flowing through NMOS transistor NM2, the current m*I1 flowing through regulating transistor NM1, and the load current IL. Therefore, the current flowing through NMOS transistor NM4 can be expressed as: ; If the load current increases, the current flowing through the NMOS transistor NM4 increases, i.e., I2 increases. Since I0 = I1 + I2, the current I1 flowing through the NMOS transistor NM2 decreases, thus realizing that the power consumption changes with the load current. When the load is not working, i.e., the load current IL = 0, the current on the NMOS transistor NM4 is only: .

[0013] Compared with the prior art, the present invention has the following advantages and effects: 1. This invention provides a floating ground generation circuit and its control method for high voltage applications, which simultaneously meets the design requirements of small area and low power consumption. 2. The operating range of the reference voltage circuit and the low-voltage error amplifier EA in this invention is between VDD and HVSS and between VDD and VOUT, which is a low-voltage domain. Therefore, high-voltage transistors are not required, thus reducing the area. 3. The circuit of this invention has a current adaptive adjustment circuit, so the power consumption of the circuit can change with the current consumed by the external load. When the load is not working, the power consumption is reduced. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a floating ground generation circuit in a high-voltage application of the present invention.

[0015] Figure 2 This is a schematic diagram of the coarse ground generation circuit of the present invention.

[0016] Figure 3 This is a schematic diagram of a high-voltage ground voltage generation circuit in the prior art.

[0017] Figure 4 This is a schematic diagram of another high-voltage ground voltage generation circuit in the prior art. Detailed Implementation

[0018] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 As shown, a floating ground generation circuit for high-voltage applications of the present invention includes a coarse ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment transistor NM1, and a current adaptive regulation circuit. The coarse ground generation circuit generates a voltage HVSS based on the power supply voltage VDD. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and the voltage HVSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF, and the inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistor network. The output terminal of the error amplifier EA is connected to the gate of the adjustment transistor NM1 and the input terminal of the current adaptive regulation circuit. The drain of the adjustment transistor NM1 is connected to the power supply voltage VDD, and the source of the adjustment transistor NM1 is connected to the output terminal of the current adaptive regulation circuit and generates an output voltage VOUT. The feedback resistor network divides the power supply voltage VDD and the output voltage VOUT for output.

[0020] like Figure 2As shown, the coarse ground generation circuit includes PMOS transistors PM2 and PM3, NMOS transistor NM6, high-voltage NMOS transistors NM7 and NM8, current sources I1 and I2. The source of PMOS transistor PM2 and the drain of NMOS transistor NM6 are connected to the power supply voltage VDD. The gate of PMOS transistor PM2 is connected to the drain of PMOS transistor PM2 and the source of PMOS transistor PM3. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3 and NM6. The gate of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7. The source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage HVSS. The gates of the high-voltage NMOS transistors NM7 and NM8 are connected to the enable signal EN. The source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1. The source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2. The other ends of the current sources I1 and I2 are grounded.

[0021] The current adaptive regulation circuit includes NMOS transistor NM2, high-voltage PMOS transistor PM1, NMOS transistor NM3, NMOS transistor NM4, high-voltage NMOS transistor NM5, and current source I0. One end of current source I0 is connected to the power supply voltage VDD, and the other end of current source I0 is connected to the drain of NMOS transistor NM2 and the source of high-voltage PMOS transistor PM1. The gate of NMOS transistor NM2 serves as the input terminal of the current adaptive regulation circuit and is connected to the output terminal of the low-voltage error amplifier EA and the gate of the regulating transistor NM1. The source of NMOS transistor NM2 is connected to the high-voltage PMOS transistor PM1. The drain of NMOS transistor NM5 is connected and serves as the output terminal of the current adaptive regulation circuit to generate the output voltage VOUT. The gate of high-voltage PMOS transistor PM1 is connected to the voltage HVSS. The drain of high-voltage PMOS transistor PM1 is connected to the drain of NMOS transistor NM3, the gate of NMOS transistor NM3, and the gate of NMOS transistor NM4. The gate of high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of high-voltage NMOS transistor NM5 is connected to the drain of NMOS transistor NM4. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.

[0022] The width-to-length ratio of the regulating transistor NM1 and the NMOS transistor NM2 is m:1. The width-to-length ratio of the NMOS transistor NM4 and the NMOS transistor NM3 is n:1.

[0023] The feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VDD, and the other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the feedback resistor network. The other end of resistor R2 is connected to the output voltage VOUT.

[0024] A control method for a floating ground generation circuit in a high-voltage application includes the following steps: The coarse adjustment ground generation circuit provides ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, NMOS transistors NM7 and NM8 are turned on, the gate-source voltage of PMOS transistor PM2 is |VGS1|, the gate-source voltage of PMOS transistor PM3 is |VGS2|, and the gate-source voltage of NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS=VDD-|VGS1|-|VGS2|-VGS3.

[0025] The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. VREF is connected to the non-inverting input of EA and, through a feedback resistor network consisting of resistors R1 and R2 and the regulating transistor NM1, yields a precise output voltage VOUT. The output voltage VOUT is expressed as: .

[0026] When the power supply voltage VDD is powered on, the enable signal EN becomes high. First, the coarse adjustment generates the circuit output voltage HVSS. The voltage HVSS provides the ground voltage for the reference voltage circuit. Then, the feedback resistor network, low-voltage error amplifier EA, regulating transistor NM1 and current adaptive adjustment circuit start to work. Finally, the output voltage VOUT is the precise floating reference ground voltage with a fixed voltage difference from the power supply voltage VDD.

[0027] The operating range of the reference voltage circuit is from the power supply voltage VDD to the voltage HVSS, and the operating range of the low-voltage error amplifier EA is from the power supply voltage VDD to the output voltage VOUT. The voltage difference between the operating ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, eliminating the need for high-voltage transistors and greatly saving space.

[0028] The current I0 generated by the current source I0 is divided into two paths, flowing to NMOS transistor NM2 and high-voltage PMOS transistor PM1 respectively. Let the current flowing through NMOS transistor NM2 be I1 and the current flowing through high-voltage PMOS transistor PM1 be I2, then I0 = I1 + I2. Since the width-to-length ratio of the regulating transistor NM1 and NMOS transistor NM2 is m:1, the current flowing through the regulating transistor NM1 is m*I1. The current flowing through NMOS transistor NM3 is equal to the current I2 flowing through high-voltage PMOS transistor PM1. At the same time, since the width-to-length ratio of NMOS transistor NM4 and NMOS transistor NM3 is n:1, the current flowing through NMOS transistor NM4 is n*I2.

[0029] The load operates between the power supply voltage VDD and the output voltage VOUT. The load current is IL. The current flowing through NMOS transistor NM4 is equal to the sum of the current I1 flowing through NMOS transistor NM2, the current m*I1 flowing through regulating transistor NM1, and the load current IL. Therefore, the current flowing through NMOS transistor NM4 can be expressed as: .

[0030] If the load current increases, the current flowing through the NMOS transistor NM4 increases, i.e., I2 increases. Since I0 = I1 + I2, the current I1 flowing through the NMOS transistor NM2 decreases, thus realizing that the power consumption changes with the load current.

[0031] When the load is not working, i.e., the load current IL = 0, the current on the NMOS transistor NM4 is only: .

[0032] Compared to Figure 4 The current in the circuit structure is reduced This reduces circuit power consumption when the load is not in operation.

[0033] This invention provides a floating ground generation circuit and its control method for high-voltage applications, which simultaneously meets the design requirements of small area and low power consumption. The operating range of the reference voltage circuit and the low-voltage error amplifier EA of this invention is between VDD and HVSS and between VDD and VOUT, which is a low-voltage domain. Therefore, high-voltage transistors are not required, reducing the area. The circuit of this invention has a current adaptive adjustment circuit, so the power consumption of the circuit can change with the current consumed by the external load. When the load is not working, the power consumption is reduced.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention, and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A floating ground generating circuit in a high voltage application, characterized by: It includes a coarse ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, a regulating transistor NM1, and a current adaptive regulation circuit. The coarse ground generation circuit generates a voltage HVSS based on the power supply voltage VDD. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and the voltage HVSS. The non-inverting input of the low-voltage error amplifier EA is connected to the reference voltage VREF. The inverting input of the low-voltage error amplifier EA is connected to the output of the feedback resistor network. The output of the error amplifier EA is connected to the gate of the regulating transistor NM1 and the input of the current adaptive regulation circuit. The drain of the regulating transistor NM1 is connected to the power supply voltage VDD. The source of the regulating transistor NM1 is connected to the output of the current adaptive regulation circuit and generates an output voltage VOUT. The feedback resistor network divides the power supply voltage VDD and the output voltage VOUT for output.

2. A floating ground generating circuit for high voltage applications according to claim 1, characterized in that: The coarse ground generation circuit includes PMOS transistors PM2 and PM3, NMOS transistor NM6, high-voltage NMOS transistors NM7 and NM8, current source I1, and current source I2. The source of PMOS transistor PM2 and the drain of NMOS transistor NM6 are connected to the power supply voltage VDD. The gate of PMOS transistor PM2 is connected to the drain of PMOS transistor PM2 and the source of PMOS transistor PM3. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3 and NMOS transistor NM8. The gate of the S-channel transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7. The source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage HVSS. The gates of the high-voltage NMOS transistors NM7 and NM8 are connected to the enable signal EN. The source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1. The source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2. The other ends of the current sources I1 and I2 are grounded.

3. The floating ground generating circuit for high voltage applications according to claim 1, characterized in that: The current adaptive regulation circuit includes an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5, and a current source I0. One end of the current source I0 is connected to the power supply voltage VDD, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 serves as the input terminal of the current adaptive regulation circuit and is connected to the output terminal of the low-voltage error amplifier EA and the gate of the regulating transistor NM1. The source of the NMOS transistor NM2 is connected to the high-voltage PMOS transistor PM1. The drain of NMOS transistor NM5 is connected and serves as the output terminal of the current adaptive regulation circuit to generate the output voltage VOUT. The gate of high-voltage PMOS transistor PM1 is connected to the voltage HVSS. The drain of high-voltage PMOS transistor PM1 is connected to the drain of NMOS transistor NM3, the gate of NMOS transistor NM3, and the gate of NMOS transistor NM4. The gate of high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of high-voltage NMOS transistor NM5 is connected to the drain of NMOS transistor NM4. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.

4. A floating ground generating circuit for high voltage applications according to claim 3, characterized in that: The width-to-length ratio of the regulating transistor NM1 and the NMOS transistor NM2 is m:

1.

5. The floating ground generating circuit for high voltage applications according to claim 3, characterized in that: The width-to-length ratio of the NMOS transistors NM4 and NMOS transistors NM3 is n:

1.

6. The floating ground generating circuit for high voltage applications according to claim 1, characterized in that: The feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VDD, and the other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the feedback resistor network. The other end of resistor R2 is connected to the output voltage VOUT.

7. A control method of a floating ground generating circuit in a high voltage application according to any one of claims 1 to 6, characterized in that Includes the following steps: The coarse adjustment ground generation circuit provides ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, NMOS transistors NM7 and NM8 are turned on, the gate-source voltage of PMOS transistor PM2 is |VGS1|, the gate-source voltage of PMOS transistor PM3 is |VGS2|, and the gate-source voltage of NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS = VDD - |VGS1| - |VGS2| - VGS3; The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. VREF is connected to the non-inverting input of EA and, through a feedback resistor network consisting of resistors R1 and R2 and the regulating transistor NM1, yields a precise output voltage VOUT. The output voltage VOUT is expressed as: ； When the power supply voltage VDD is powered on, the enable signal EN becomes high. First, the coarse adjustment generates the circuit output voltage HVSS. The voltage HVSS provides the ground voltage for the reference voltage circuit. Then, the feedback resistor network, low-voltage error amplifier EA, regulating transistor NM1 and current adaptive adjustment circuit start to work. Finally, the output voltage VOUT is the precise floating reference ground voltage with a fixed voltage difference from the power supply voltage VDD. The operating range of the reference voltage circuit is from the power supply voltage VDD to the voltage HVSS, and the operating range of the low-voltage error amplifier EA is from the power supply voltage VDD to the output voltage VOUT. The voltage difference between the operating ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, and no high-voltage transistor is required. The current I0 generated by the current source I0 is divided into two paths, flowing to NMOS transistor NM2 and high-voltage PMOS transistor PM1 respectively. Let the current flowing through NMOS transistor NM2 be I1 and the current flowing through high-voltage PMOS transistor PM1 be I2, then I0 = I1 + I2. Since the width-to-length ratio of the regulating transistor NM1 and NMOS transistor NM2 is m:1, the current flowing through the regulating transistor NM1 is m*I1. The current flowing through NMOS transistor NM3 is equal to the current I2 flowing through high-voltage PMOS transistor PM1. At the same time, since the width-to-length ratio of NMOS transistor NM4 and NMOS transistor NM3 is n:1, the current flowing through NMOS transistor NM4 is n*I2. The load operates between the power supply voltage VDD and the output voltage VOUT. The load current is IL. The current flowing through NMOS transistor NM4 is equal to the sum of the current I1 flowing through NMOS transistor NM2, the current m*I1 flowing through regulating transistor NM1, and the load current IL. Therefore, the current flowing through NMOS transistor NM4 can be expressed as: ； If the load current increases, the current flowing through the NMOS transistor NM4 increases, i.e., I2 increases. Since I0 = I1 + I2, the current I1 flowing through the NMOS transistor NM2 decreases, thus realizing that the power consumption changes with the load current. When the load is not working, i.e., the load current IL = 0, the current on the NMOS transistor NM4 is only: 。

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