Touch screen system, touch screen method, and program product

Abstract

This application relates to the field of screen dot-mapping testing technology, and in particular to a screen dot-mapping system, screen dot-mapping method, and program product. The screen dot-mapping system includes a first electronic device and a plurality of second electronic devices each connected to the first electronic device. The first electronic device is used to segment initial image data into a plurality of sub-image data and send the plurality of sub-image data to the plurality of second electronic devices respectively. It is also used to send a control signal containing a first clock frequency to each of the second electronic devices, and to send a synchronization signal to each of the second electronic devices at the same time. Each second electronic device, upon receiving the synchronization signal, sends the received sub-image data to different display areas of a display module according to the same data format and the first clock frequency.

Description

Technical Field

[0001] This application relates to the field of display screen dot detection technology, and in particular to a dot detection system, dot detection method and program product. Background Technology

[0002] Display products are at the forefront of human-computer interaction. With the upgrading of display technology and consumption, people's demands for resolution and refresh rate are increasing. Currently, for TVs, 4K resolution displays have become mainstream, and even 8K resolution displays are being offered by some high-end manufacturers. For gaming monitors, people often flock to high refresh rates.

[0003] These ultra-high resolution, ultra-high refresh rate display modules typically use VBO (V-by-One) signals or EDP extended signals as their signal sources. Due to the high resolution, high refresh rate, and large amount of image data, the required video transmission bandwidth is very large. 8K resolution display modules typically use 32-lane (data channels) or 64-lane VBO signals and 8-lane or 16-lane EDP signals, while 10K resolution display modules use 64-lane VBO signals or 16-lane EDP signals, and 5K resolution 240Hz display modules use 16-lane EDP signals.

[0004] In the research and development and production of ultra-high resolution and ultra-high refresh rate display modules, VBO image signal source equipment or EDP image signal source equipment with static image display function are generally used to perform screen display operations, so as to determine whether the module is qualified by the display quality.

[0005] In related technologies, signal source devices employ VBO transmission and use a one-to-many method to multiply and extend the VBO, i.e., low refresh rate transmission and high refresh rate output. However, this implementation method requires ensuring that the outputs of each expansion device originate from the same source. The rate of its image output signal is limited by the rate of the image input signal. Furthermore, a complete image is often transmitted between the signal source device and the expansion device before the corresponding output image is captured at the expansion device. For certain types of screens, multi-functional cutting cannot be achieved; cutting can only be performed at the back end of transmission, not before. For some multi-lane EDP display modules, there are higher requirements for data synchronization, often requiring the use of an FPGA chip with multiple high-speed interfaces for synchronous output to the screens, which is costly. Summary of the Invention

[0006] In view of this, this application proposes a screen tapping system, screen tapping method, and program product.

[0007] In a first aspect, a dot-screen system is proposed, including a first electronic device and a plurality of second electronic devices each connected to the first electronic device. The first electronic device is used to divide initial image data into a plurality of sub-image data and send the plurality of sub-image data to the plurality of second electronic devices respectively. It is also used to send a control signal containing a first clock frequency to each of the second electronic devices and to send a synchronization signal to each of the second electronic devices at the same time.

[0008] Each of the second electronic devices is used to send the received sub-image data to different display areas of the display module in the same data format and the first clock frequency when it receives the synchronization signal.

[0009] In some possible implementations, the second electronic device includes:

[0010] A storage chip for storing the sub-image data received from the first electronic device;

[0011] Clock chip;

[0012] The read and output module includes a buffer connected to the storage chip, used to read the sub-image data from the storage chip into the buffer, and, with the help of the clock chip, send the sub-image data in the buffer to the corresponding display area of ​​the display module at the first clock frequency.

[0013] In some possible implementations, the read and output module sends the sub-image data in the cache separately to multiple display areas of the display module in a data remapping manner according to the partitioning requirements of the display module.

[0014] In some possible implementations, the first electronic device includes:

[0015] An image data generation module is used to generate the initial image data;

[0016] An image data segmentation module is used to segment the initial image data into the plurality of sub-image data;

[0017] An image data output module is used to send the sub-image data to the second electronic device;

[0018] An LVDS output module is used to send the control signal and the synchronization signal in LVDS format to the second electronic device.

[0019] The second electronic device includes:

[0020] The LVDS parsing module is used to receive the control signal and the synchronization signal from the LVDS output module, and to parse the control signal and the synchronization signal.

[0021] In some possible implementations, the target electronic device in the plurality of second electronic devices includes a plurality of FPGA units and a plurality of memory chips not included in the FPGAs, each of the FPGA units including a respective read and output module and a respective image data receiving module;

[0022] In the target electronic device, each of the image data receiving modules is used to receive one of the plurality of sub-image data from the first electronic device and store the sub-image data in a different memory chip. Each of the read and output modules is used to read the sub-image data from the memory chip into the buffer and, with the help of the same clock chip, read the sub-image data from a different memory chip at the first clock frequency.

[0023] In some possible implementations, the first electronic device includes:

[0024] An LVDS output module is used to send the control signal and the synchronization signal in LVDS format to the second electronic device.

[0025] In the target electronic device, each FPGA unit includes its own LVDS parsing module for receiving the control signal and the synchronization signal from the LVDS output module, and parsing the control signal and the synchronization signal, and only one LVDS parsing module is connected to the same clock chip.

[0026] Secondly, a screen tapping method is proposed, including:

[0027] The first electronic device divides the initial image data into multiple sub-image data, sends the multiple sub-image data to multiple second electronic devices respectively, sends a control signal containing a first clock frequency to each second electronic device, and sends a synchronization signal to each second electronic device at the same time.

[0028] Upon receiving the synchronization signal, each of the second electronic devices sends the received sub-image data to different display areas of the display module in the same data format and at the first clock frequency.

[0029] In some possible implementations, each of the second electronic devices includes a buffer, a memory chip, and a clock chip, and each of the second electronic devices stores the sub-image data it receives in the memory chip of the second electronic device;

[0030] Upon receiving the synchronization signal, each of the second electronic devices transmits the received sub-image data to different display areas of the display module according to the same data format and the first clock frequency, specifically including:

[0031] Upon receiving the synchronization signal, each of the second electronic devices reads the sub-image data from the storage chip into the buffer, and with the help of the clock chip, sends the sub-image data in the buffer to different display areas of the display module according to the first clock frequency.

[0032] In some possible implementations, the target electronic device in the plurality of second electronic devices includes a plurality of FPGA units and a plurality of memory chips not included in the FPGA units, wherein the plurality of FPGA units include a plurality of caches corresponding to the plurality of memory chips respectively;

[0033] Upon receiving the synchronization signal, each of the second electronic devices transmits the received sub-image data to different display areas of the display module according to the same data format and the first clock frequency, specifically including:

[0034] In the target electronic device, each FPGA unit receives one of the plurality of sub-image data from the first electronic device and stores the sub-image data in a different memory chip. Upon receiving the synchronization signal, the sub-image data is read from the memory chip into the buffer, and with the help of the same clock chip, the sub-image data in the memory chip is sent to the corresponding display area of ​​the display module at the first clock frequency.

[0035] Thirdly, a computer program product is proposed, comprising a computer program that, when executed by a computer device, implements the method described in the second aspect.

[0036] According to the screen dotting system, screen dotting method and program product proposed in this application, even if the first electronic device sends each sub-image data to the second electronic device at different clock frequencies, these second electronic devices can still perform high-resolution and high-refresh-rate synchronous screen dotting on different display areas of the display module at the same clock frequency. That is, the sub-image data obtained by each second electronic device does not need to be completely from the same source. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this application, and are not intended to limit this application.

[0038] Figure 1 This is a structural block diagram of the dot-screen system provided in the embodiments of this application.

[0039] Figure 2 This is a schematic diagram showing the connection between the storage chip and the read and output module in the dot-screen system provided in this application embodiment.

[0040] Figure 3 This is a structural block diagram of the dot-screen system provided in the embodiments of this application.

[0041] Figure 4 This is a structural block diagram of the dot-screen system provided in the embodiments of this application.

[0042] Figure 5 This is a flowchart illustrating the screen tapping method provided in the embodiments of this application.

[0043] Explanation of reference numerals in the attached figures:

[0044] 10 - First electronic device;

[0045] 20 - Second electronic device; 20A - Target electronic device;

[0046] 30 - Display module. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the described embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It is understood that, without conflict, some technical means of the various embodiments described herein can be substituted for or combined with each other.

[0048] In the description of this application, the terms "first," "second," etc., are used only to distinguish the described objects and have no sequential or technical meaning. Therefore, objects specified with "first," "second," etc., may explicitly or implicitly include one or more of those objects. Furthermore, the words "one" or "a" do not indicate a quantity limitation, but rather indicate the presence of at least one, while "multiple" indicates at least two.

[0049] In the description of this application, the terms "based on" or "according to" are used to describe one or more factors that influence the determination. This term does not exclude additional factors influencing the determination. That is, the determination may be based solely on these factors or at least partially on them. For example, the phrase "based on A to determine B" means that A is a factor influencing the determination of B, and this phrase does not exclude the possibility that the determination of B may also be based on C.

[0050] In the description of this application, references to "one embodiment" or "some embodiments" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0051] The following is combined with Figure 1 The present application describes a dot-screen system according to an embodiment of the present application. The dot-screen system includes a first electronic device 10 and two (in one example of a plurality of) second electronic devices 20 each connected to the first electronic device 10. The second electronic devices 20 can be connected to the first electronic device 10 via conductive cables. The first electronic device 10 can be referred to as a signal source device, and the second electronic devices 20 can be referred to as extension devices.

[0052] The first electronic device 10 is used to generate initial image data, divide the initial image data into two (or more) sub-image data, and send the two sub-image data to two second electronic devices 20 respectively. The first electronic device 10 is also used to send a control signal containing a first clock frequency to each second electronic device 20, and to send a synchronization signal to each second electronic device 20 at the same time.

[0053] Each second electronic device 20 is used to send the received sub-image data to different display areas of the display module 30 in the same data format (such as VBO format or EDP format) and a first clock frequency when a synchronization signal is received.

[0054] Specifically, the first electronic device 10 includes an image data generation module, an image data segmentation module, an image data output module, an image data output module, and an LVDS output module.

[0055] The image data generation module can generate initial image data based on the configuration parameters obtained from the host computer or other devices. The initial image data can correspond to a complete test image.

[0056] The image data segmentation module is used to segment the initial image data into two sub-image data. In one implementation, the initial image data is in VBO (V-by-One) format, and correspondingly, the sub-image data is also in VBO format.

[0057] Two image data output modules are configured, each connected to one of two second electronic devices 20. Each image data output module is used to obtain one of two sub-image data from the image data segmentation module and send that sub-image data to the connected second electronic device 20. Figure 1 In this embodiment, the image data output module is used to send sub-image data in VBO format, therefore, it can also be called a VBO output module.

[0058] The LVDS output module is used to send LVDS format control signals and LVDS format synchronization signals to the second electronic device 20. That is, the control signals and synchronization signals sent by the first electronic device 10 to each second electronic device 20 are in LVDS format. Since the bandwidth of LVDS can reach more than 1Gbps, it can transmit a relatively large number of control signals to meet the increasingly diverse screen requirements. As mentioned above, the control signal includes a first clock frequency, which can be any value selected according to the operator's operation, and this value is adapted to the display module 30 of the screen being touched. For example, the operator can input characteristic information such as the resolution and refresh rate of the current display module 30 to the first electronic device 10, and the first electronic device 10 can automatically determine the value of the first clock frequency based on this characteristic information.

[0059] The second electronic device 20 includes an image data parsing module, an LVDS parsing module, a storage chip, a clock chip, and a read and output module.

[0060] The image data parsing module receives sub-image data from the image data output module, parses the sub-image data, and transmits the parsed sub-image data to the storage chip. Figure 1 In this embodiment, the image data parsing module is used to receive and parse VBO format sub-image data, and therefore can also be called the VBO parsing module.

[0061] The memory chip is used to store sub-image data received from the first electronic device 10, which is also transmitted from the image data parsing module.

[0062] The LVDS parsing module receives LVDS format control and synchronization signals from the LVDS output module, parses these signals, and transmits the first clock frequency obtained from the parsed control signals to the clock chip. Since the LVDS output module outputs the synchronization signal and the LVDS parsing module receives it, the LVDS output module can be called the synchronization signal output module, and the LVDS parsing module can be called the synchronization signal receiving module.

[0063] The clock chip receives the first clock frequency from the LVDS parsing module and operates at that first clock frequency.

[0064] Please combine them together Figure 2 The read and output module includes a buffer connected to the memory chip, used to read sub-image data from the memory chip into the buffer, and, with the help of a clock chip, send the sub-image data in the buffer to the corresponding display area of ​​the display module 30 at a first clock frequency. Since the first clock frequency is selected to a value adapted to the parameter characteristics of the display module 30, the corresponding display area of ​​the display module 30 can normally display the sub-image data at this first clock frequency. The read and output module can also be referred to as an image data read and output module or a sub-image data read and output module.

[0065] exist Figure 1 In this configuration, the second electronic device 20's read and output module includes a VBO read and output module and an EDP read and output module. The VBO read and output module sends sub-image data to the corresponding display area of ​​the display module 30 in VBO format, and the EDP read and output module sends sub-image data to the corresponding display area of ​​the display module 30 in EDP format. Thus, when the display module 30 being tapped supports the VBO format, the second electronic device 20's VBO read and output module can provide sub-image data to the display module 30; when the display module 30 being tapped supports the EDP format, the second electronic device 20's EDP read and output module can provide sub-image data to the display module 30. The VBO read and output module and the EDP read and output module can each include the aforementioned buffer, or they can share the same aforementioned buffer.

[0066] Please continue reading Figure 1 ,exist Figure 1In one application example of the dot-screen system shown, the display module 30 under test is an 8K resolution 60Hz (7680*4320@60Hz) display module that supports 32 lanes and two-area VBO (V-by-One) signals. The data generation module of the first electronic device 10 generates initial image data in 8K (7680*4320) resolution and VBO format based on the configuration data obtained from the host computer. The image data segmentation module divides the initial image data into two sub-image data with a resolution of 3840*4320, and these two sub-image data correspond to the left and right display areas of the initial image data on the display module 30, respectively. The two 3840*4320 resolution sub-image data are sent to the two image data parsing modules of the second electronic device 20 by the two image data output modules, respectively. The two image data parsing modules of the second electronic device 20 respectively receive 3840*4320 resolution sub-image data from the two image data output modules, and parse the sub-image data. The parsed sub-image data is then passed to the storage chip via the buffer of the read and output module. The storage chip then stores the sub-image data passed from the image data parsing module via the buffer.

[0067] On the other hand, the LVDS output module of the first electronic device 10 sends an LVDS format control signal to the second electronic device 20. The control signal contains a first clock frequency adapted to the display module 30. The value of the first clock frequency can be selected by the operator or the processor according to the parameter characteristics of the display module 30. The LVDS parsing module of the second electronic device 20 receives the control signal from the LVDS output module, parses the control signal, and transmits the first clock frequency obtained from the control signal to the clock chip. The clock chip operates at the first clock frequency based on the first clock frequency signal obtained from the LVDS parsing module. Furthermore, the LVDS output module of the first electronic device 10 simultaneously sends an LVDS format synchronization signal to both second electronic devices 20 at a set time point. When the second electronic device 20 receives the synchronization signal, in response, each read and output module reads sub-image data from the storage chip and, with the help of the clock chip, sends the VBO format sub-image data to the corresponding display area of ​​the display module 30 at 16 lanes and 2.97Gbps according to the first clock frequency. Since the first electronic device 10 simultaneously sends LVDS format synchronization signals to the two second electronic devices 20, the two second electronic devices 20 will receive the synchronization signals at the same time. Consequently, the two second electronic devices 20 simultaneously send their respective sub-image data to different display areas of the display module 30. As a result, the two second electronic devices 20 synchronously light up the two display areas of the 7680*4320@60Hz display module. Furthermore, the read and output module can also read sub-image data from the storage chip into the buffer at the first clock frequency with the help of the clock chip.

[0068] And in Figure 1 In this embodiment, each second electronic device 20 includes an FPGA unit, which comprises the image data parsing module, the LVDS parsing module, and the read and output module. That is, the aforementioned image data parsing module, LVDS parsing module, and read and output module (including their respective buffers) of the second electronic device 20 are integrated into a single FPGA unit. Furthermore, the memory chip and clock chip are not included in the FPGA unit; therefore, the memory chip and clock chip are also referred to as external memory chip and external clock chip, respectively. An FPGA unit can be constructed from a single FPGA chip.

[0069] It is understandable that, since the first clock frequency is provided to the second electronic device 20 by the first electronic device 10 via a control signal, and the value of this first clock frequency is not limited by the transmission frequency (clock frequency) of the control signal to the second electronic device 20, nor by the transmission frequency (clock frequency) of the sub-image data to the second electronic device 20, even if the first electronic device 10 sends the sub-image data to the second electronic device 20 at a relatively low clock frequency, the second electronic device 20 can still provide the sub-image data to the display module 30 at a high clock frequency (first clock frequency), thereby achieving high-resolution and high-refresh-rate screen operation on the display module 30. Furthermore, even if the first electronic device 10 sends each sub-image data to the second electronic device 20 at different clock frequencies, these second electronic devices 20 can still synchronously perform screen operation on different display areas of the display module 30 at the same first clock frequency; that is, the sub-image data obtained by each second electronic device 20 does not need to be completely from the same source.

[0070] Next, please see Figure 3 , Figure 3 This application illustrates a dot-screen system according to another embodiment of the present application, which has Figure 1 The dot-screen system of the illustrated embodiment has a similar structure and can be referred to for further details. Figure 1 The description is intended to be understood by way of reference, and for simplicity, identical or similar components are given the same or similar reference numerals, and repetitive detailed descriptions of their identical parts are omitted. The following focuses on describing this embodiment and... Figure 1 Differences in the implementation examples.

[0071] exist Figure 3 The tested display module 30 is an 8K resolution 120Hz (7680*4320@120Hz) display module that supports 64 lanes and four-zone VBO (V-by-One) signals.

[0072] exist Figure 3 In this configuration, three second electronic devices 20 are provided, and one of these second electronic devices 20 (for ease of explanation, it is referred to as target electronic device 20A; specifically...) Figure 2 The second electronic device 20 on the right side of the middle section and two other second electronic devices 20 (specifically: Figure 2 The two second electronic devices 20 on the left and in the middle are different. Specifically, the structures of the other two second electronic devices 20 are different. Figure 1The various second electronic devices 20 are identical, each consisting of only one FPGA unit, and therefore will not be described in detail. For clarity, the middle second electronic device 20 is depicted in a simplified manner. The difference lies in the target electronic device 20A on the right, which includes two FPGA units, two memory chips not included in the FPGA units, and a clock chip not included in the FPGA units. Each FPGA unit includes its own image data parsing module, LVDS parsing module, and read / output module. In the target electronic device 20A, the two memory chips are connected via a buffer (not shown in the diagram) (which can be combined with...). Figure 2 (To understand) The image data receiving module is connected to two FPGA units, and the clock chip is connected to the LVDS parsing module and the read and output module of each FPGA unit. In implementation, each image data parsing module is used to receive one of multiple sub-image data from the first electronic device 10 and store the sub-image data in a different memory chip. Each read and output module is used to read the sub-image data from the memory chip into a buffer (not shown), and send the sub-image data in the buffer to the corresponding display area of ​​the display module 30 at a first clock frequency with the help of the same clock chip.

[0073] For ease of understanding, the following is given: Figure 3 A specific application example. In the first electronic device 10, the image data segmentation module segments the initial 8K resolution image data into four 4K (3840*2160) resolution sub-image data, and the four image data output modules send these four 4K resolution sub-image data to three second electronic devices 20 respectively. More specifically, two sub-image data are sent to the two FPGA units of the target electronic device 20A respectively, and the other two sub-image data are sent to the other two second electronic devices 20 respectively. The two FPGA units of the target electronic device 20A store the two received sub-image data into two external memory chips respectively. When the LVDS parsing module of the target electronic device 20A receives the synchronization signal, the two read and output modules of the two FPGA units read the two sub-image data from the two memory chips into the buffers of the read and output modules respectively, and with the help of the same clock chip, send the two sub-image data in the two buffers to the two display areas of the display module 30 at the first clock frequency. For the other two second electronic devices 20 that are not the target electronic device 20A, the data of the other two sub-images is sent to the other two display areas of the display module 30, thereby realizing the four-zone high refresh rate screen display of the 8K display module 30.

[0074] Next, please see Figure 4 , Figure 4 This application illustrates a dot-screen system according to another embodiment of the present application, which has Figures 1 to 3 The dot-screen system of the illustrated embodiment has a similar structure and can be referred to for further details. Figures 1 to 3 The description is intended to be understood by way of reference, and for simplicity, identical or similar components are given the same or similar reference numerals, and repetitive detailed descriptions of their identical parts are omitted. The following focuses on describing this embodiment and... Figures 1 to 3 Differences in the implementation examples.

[0075] exist Figure 4 The tested display module 30 is a 5K resolution 240Hz (5120*2880@240Hz) display module that supports 16 lanes and four-zone EDP signals.

[0076] exist Figure 4 In this configuration, only one second electronic device 20 is provided, and it is constructed to have the same structure as the aforementioned target electronic device 20A. Therefore, for ease of explanation, this... Figure 3 The second electronic device 20 of the center screen system is also called the target electronic device 20A.

[0077] For ease of understanding, the following is given: Figure 4 A specific application example. In the first electronic device 10, the image data segmentation module segments the initial image data with a resolution of 5K (5120*2880) into two sub-image data with a resolution of 2560*2880, and the two image data output modules send the two sub-image data with a resolution of 2560*2880 to the target electronic device 20A respectively. Specifically, the two sub-image data are sent to the two FPGA units of the target electronic device 20A respectively. The two FPGA units of the target electronic device 20A store the two received sub-image data into two external memory chips respectively. When the LVDS parsing module of the target electronic device 20A receives the synchronization signal, the two read and output modules of the two FPGA units, with the help of the same clock chip, read the two sub-image data from the two memory chips respectively according to the first clock frequency. According to the four-area requirements of the display module 30, each 2560*2880 resolution sub-image data is converted into two 1280*2880 resolution secondary sub-image data in the form of data remapping and sent separately to the two display areas of the display module. In this way, the target electronic device 20A sends the four secondary sub-image data to the four display areas of the display module 30 respectively in the 16-lane, 8.1Gbps EDP signal format, thereby realizing the four-area high refresh rate screen display of the 5K display module 30.

[0078] Although the above only describes the cases where the number of second electronic devices 20 is one, two, and three, it should be understood that the number of second electronic devices 20 can also be more, such as four or eight. Furthermore, although the above only describes the case where the target electronic device 20A has two FPGA units, it should be understood that the target electronic device 20A can also be configured with more FPGA units, such as four, thereby providing dot-screen support for four display areas of the display module 30. A single target electronic device 20A can provide high-resolution and high-refresh-rate dot-screen support for multiple display areas of the display module, and can achieve higher screen-end synchronization while saving on the number of clock chips. Additionally... Figure 3 In the corresponding embodiment, since the display module 30 is divided into four regions, the read and output module of the FPGA unit of the second electronic device 20A also needs to perform data remapping of the sub-image data in two regions. However, the amount of image data entering and exiting the FPGA unit of the second electronic device 20A remains unchanged. Therefore, it should be understood that the entire dot-screen system can flexibly configure the number of image segments of the first electronic device 10 and the sub-image data remapping of the read and output module of the second electronic device 20 according to the partitioning requirements of the display module.

[0079] Next, please see Figure 5 , Figure 5 This application illustrates a screen dotting method according to an embodiment of the present application, which can be used to... Figure 1 or Figure 2 The screen-based system shown in the diagram, in conjunction with the discussion above, includes the following methods:

[0080] S501, the first electronic device 10 divides the initial image data into multiple sub-image data, sends the multiple sub-image data to multiple second electronic devices 20 respectively, sends a control signal containing a first clock frequency to each second electronic device 20, and sends a synchronization signal to each second electronic device 20 at the same time.

[0081] S502, when each second electronic device 20 receives the synchronization signal, it sends the received sub-image data to different display areas of the display module 30 in the same data format and with the first clock frequency.

[0082] Specifically, step S502 includes: upon receiving a synchronization signal, each second electronic device 20, with the assistance of a clock chip, reads sub-image data from a storage chip at a first clock frequency, and sends the sub-image data to different display areas of the display module 30 according to the same data format and the first clock frequency. Additionally, in Figure 4 Or with Figure 4In similar application scenarios, the second electronic device 20 can also send the sub-image data it obtains to different display areas of the display module separately according to the first clock frequency, based on the partitioning requirements of the display module and in the form of data remapping.

[0083] And when this method is Figure 3 When the display system shown is executed, step S502 more specifically includes: in the target electronic device 20A, each FPGA unit receives one of the multiple sub-image data from the first electronic device 10, stores the sub-image data in a different memory chip, and when a synchronization signal is received, reads the sub-image data from the memory chip into a buffer, and sends the sub-image data in the buffer to the corresponding display area of ​​the display module at a first clock frequency with the help of the same clock chip.

[0084] This application also provides a computer program product, including a computer program that, when executed by a computer device, implements the above-described screen tapping method.

Claims

1. A dot-screen system, comprising a first electronic device and a plurality of second electronic devices each connected to the first electronic device, characterized in that, The first electronic device is used to divide the initial image data into multiple sub-image data and send the multiple sub-image data to the multiple second electronic devices respectively. It is also used to send a control signal containing a first clock frequency to each of the second electronic devices and to send a synchronization signal to each of the second electronic devices at the same time. The first clock frequency is adapted to the display module of the screen being touched. The first electronic device is also used to automatically determine the value of the first clock frequency based on the resolution and refresh rate feature information of the display module input by the operator. Each of the second electronic devices is used to send the received sub-image data to different display areas of the display module in the same data format and the first clock frequency when receiving the synchronization signal; wherein, the clock frequency at which the first electronic device sends the sub-image data to the second electronic device is less than the first clock frequency, and the first electronic device sends multiple sub-image data to multiple second electronic devices at different clock frequencies so that the multiple second electronic devices can adapt to sub-image data from different sources; The second electronic device includes: A storage chip for storing the sub-image data received from the first electronic device; Clock chip; The read and output module includes a buffer connected to the storage chip, used to read the sub-image data from the storage chip into the buffer, and, with the help of the clock chip, send the sub-image data in the buffer to the corresponding display area of ​​the display module at the first clock frequency.

2. The system according to claim 1, characterized in that, The read and output module is used to send the sub-image data in the cache separately to multiple display areas of the display module in a data remapping manner according to the partitioning requirements of the display module.

3. The system according to claim 1, characterized in that, The first electronic device includes: An image data generation module is used to generate the initial image data; An image data segmentation module is used to segment the initial image data into the plurality of sub-image data; An image data output module is used to send the sub-image data to the second electronic device; An LVDS output module is used to send the control signal and the synchronization signal in LVDS format to the second electronic device. The second electronic device includes: The LVDS parsing module is used to receive the control signal and the synchronization signal from the LVDS output module, and to parse the control signal and the synchronization signal.

4. The system according to claim 1, characterized in that, The target electronic device in the plurality of second electronic devices includes a plurality of FPGA units and a plurality of memory chips not included in the FPGA units. Each FPGA unit includes its own read and output module and its own image data receiving module. In the target electronic device, each of the image data receiving modules is used to receive one of the plurality of sub-image data from the first electronic device and store the sub-image data in a different storage chip. Each of the read and output modules is used to read the sub-image data from the storage chip into the buffer and, with the help of the same clock chip, send the sub-image data in the buffer to the corresponding display area of ​​the display module at the first clock frequency.

5. The system according to claim 4, characterized in that, The first electronic device includes: An LVDS output module is used to send the control signal and the synchronization signal in LVDS format to the second electronic device. In the target electronic device, each FPGA unit includes its own LVDS parsing module for receiving the control signal and the synchronization signal from the LVDS output module, and parsing the control signal and the synchronization signal, and only one LVDS parsing module is connected to the same clock chip.

6. A screen tapping method, applied to the screen tapping system as described in any one of claims 1 to 5, characterized in that, The method includes: The first electronic device divides the initial image data into multiple sub-image data, sends the multiple sub-image data to multiple second electronic devices respectively, sends a control signal containing a first clock frequency to each second electronic device, and sends a synchronization signal to each second electronic device at the same time. When each of the second electronic devices receives the synchronization signal, it sends the received sub-image data to different display areas of the display module in the same data format and the first clock frequency; wherein, the first clock frequency is adapted to the display module of the screen being touched, and the first electronic device automatically determines the value of the first clock frequency based on the resolution and refresh rate feature information of the display module input by the operator. In this process, the clock frequency at which the first electronic device sends the sub-image data to the second electronic device is lower than the first clock frequency. The first electronic device sends multiple sub-image data to multiple second electronic devices at different clock frequencies, so that the multiple second electronic devices can adapt to sub-image data from different sources.

7. The method according to claim 6, characterized in that, Each of the second electronic devices includes a buffer, a memory chip, and a clock chip, and each of the second electronic devices stores the sub-image data it receives in the memory chip of the second electronic device; Upon receiving the synchronization signal, each of the second electronic devices transmits the received sub-image data to different display areas of the display module according to the same data format and the first clock frequency, specifically including: Upon receiving the synchronization signal, each of the second electronic devices reads the sub-image data from the storage chip into the buffer, and with the help of the clock chip, sends the sub-image data in the buffer to different display areas of the display module according to the first clock frequency.

8. The method according to claim 7, characterized in that, The target electronic device in the plurality of second electronic devices includes a plurality of FPGA units and a plurality of memory chips not included in the FPGA units, wherein the plurality of FPGA units include a plurality of caches corresponding to the plurality of memory chips respectively; Upon receiving the synchronization signal, each of the second electronic devices transmits the received sub-image data to different display areas of the display module according to the same data format and the first clock frequency, specifically including: In the target electronic device, each FPGA unit receives one different of the plurality of sub-image data from the first electronic device and stores the sub-image data in a different memory chip. Upon receiving the synchronization signal, the sub-image data is read from the memory chip into the buffer, and within the same... With the help of the clock chip, the sub-image data in the buffer is sent to the corresponding display area of ​​the display module according to the first clock frequency.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a computer device, it implements the method as described in any one of claims 6 to 8.

Images