Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel, by providing fan-out connecting lines that connect to first-type data lines, and by providing first-type and second-type control transistors between signal input lines and corresponding two second-type data lines, can reduce the bezel size. Furthermore, by electrically connecting the second-type data lines connected to the first sub-pixel units to the first-type control transistors, and the second-type data lines connected to the second sub-pixel units to the second-type control transistors, the interference experienced by the second-type data lines connected to the first sub-pixel units from adjacent second-type data lines is similar or even identical, improving display uniformity and avoiding display abnormalities.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the development of display technology, the refresh rate of display devices is increasing, and correspondingly, the number of signal lines required in display devices is also increasing. However, the number of channels in the driver chip is limited. Increasing the number of signal lines requires increasing the number of driver chips, leading to increased costs and larger bezels. To solve these problems, existing display devices have proposed a mux (multiplexing) technology. This technology connects two signal lines to a single driver chip channel under the control of a multiplexed line. This allows for increased signal line counts with increased frequency without the need for additional driver chips, reducing costs and bezel size. Furthermore, to further reduce bezel size, display devices often employ FIAA (FanoutIn AA) technology. However, in practical use, it has been found that when display devices use a Real RGB array, simultaneously employing mux and FIAA technologies can cause display anomalies.

[0003] Therefore, existing display devices using Real RGB arrangement may experience display abnormalities when employing both mux and FIAA technologies. Summary of the Invention

[0004] This application provides a display panel and a display device to alleviate the technical problem of display abnormalities that occur when existing display devices using Real RGB arrangement simultaneously employ mux technology and FIAA technology.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel comprising a plurality of pixel units, each pixel unit comprising a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit of different emitting colors, wherein the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are sequentially arranged along a first direction within each pixel unit; the display panel comprises:

[0006] Multiple scan lines;

[0007] Multiple data lines, each of which is connected to a sub-pixel unit of the same luminous color, and the multiple data lines include multiple first-type data lines and multiple second-type data lines;

[0008] Multiple fan-out connecting lines are electrically connected to the first type of data lines, and the multiple data lines and the multiple fan-out connecting lines are arranged at intervals along a first direction;

[0009] Multiple signal input lines are provided. Some of the signal input lines are electrically connected to two second-type data lines, and some of the signal input lines are electrically connected to two fan-out connection lines. A first-type control transistor and a second-type control transistor are respectively provided between each signal input line and the corresponding two second-type data lines. A first-type control transistor and a second-type control transistor are respectively provided between each signal input line and the corresponding two fan-out connection lines. The gate of the first-type control transistor is connected to a first signal control line, and the gate of the second-type control transistor is connected to a second signal control line. The input time period of the effective level of the first signal control line does not overlap with the input time period of the effective level of the scan line, while the input time period of the effective level of the second signal control line overlaps with the input time period of the effective level of the scan line.

[0010] Wherein, the second type of data line connected to the first sub-pixel unit is electrically connected to the first type of control transistor, and the second type of data line connected to the second sub-pixel unit is electrically connected to the second type of control transistor.

[0011] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.

[0012] This application provides a display panel and a display device. The display panel, by providing fan-out connecting lines that connect to first-type data lines, and by providing first-type and second-type control transistors between signal input lines and corresponding two second-type data lines, can reduce the bezel size. Furthermore, by electrically connecting the second-type data lines connected to the first sub-pixel units to the first-type control transistors, and the second-type data lines connected to the second sub-pixel units to the second-type control transistors, the interference experienced by the second-type data lines connected to the first sub-pixel units from adjacent second-type data lines is similar or even identical, improving display uniformity and avoiding display abnormalities.

[0013] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0016] Figure 1 This is a plan view of the display panel provided in an embodiment of this application.

[0017] Figure 2 This is a first schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in the embodiments of this application.

[0018] Figure 3 for Figure 2 A schematic diagram showing the pixel arrangement of the display panel and the connection relationship between signal lines and transistors.

[0019] Figure 4 This is a second schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in the embodiments of this application.

[0020] Figure 5 for Figure 4 A schematic diagram showing the pixel arrangement of the display panel and the connection relationship between signal lines and transistors.

[0021] Figure 6 A timing diagram of some signal lines in a display panel provided in an embodiment of this application.

[0022] Figure 7 This is a schematic diagram of a contrast display device provided in an embodiment of this application.

[0023] Figure 8 This is a schematic diagram of another contrast display device provided in an embodiment of this application.

[0024] Figure 9 This is a schematic diagram of another contrast display device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connection" and "electrical connection" should be interpreted broadly. For example, it can refer to a direct connection or an indirect connection through an intermediate medium, or it can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0027] To illustrate the principle behind the technical problems in the embodiments of this application, some comparative display devices are provided. It should be understood that these comparative display devices are not considered prior art in the embodiments of this application. To reduce bezels and lower costs, these comparative display devices employ both mux and FIAA technologies. The pixel arrangement of the comparative display devices is designed using SPR (Sub Pixel Rendering) (e.g.) Figure 7 In the case where red sub-pixel 311 and blue sub-pixel 313 are in the same column, and green sub-pixel 312 is in a separate column, such as... Figure 7 As shown, the data trace DL and the fan-out trace FL can be designed in a 1:1 ratio. Two multiplexed lines (i.e., the first multiplexed line Mux01 and the second multiplexed line Mux02) and the control transistor T001 are used to control the signal input of the data trace DL, and the adjacent fan-out traces FL are connected to the same multiplexed line, so that the comparison display device can display normally.

[0028] When comparing a display device with a Real RGB pixel arrangement (red sub-pixels 311, blue sub-pixels 313, and green sub-pixels 312 are located in a separate column, and the red sub-pixels 311, green sub-pixels 312, and blue sub-pixels 313 are arranged sequentially), taking a data trace DL to fan-out trace FL ratio of 2:1 and using two multiplexed lines (i.e., the first multiplexed line Mux01 and the second multiplexed line Mux02) to control the signal input of the data traces as an example, Figure 8 As shown, if the control transistor T001 connected to the data trace DL is still sequentially and alternately connected to different multiplexed lines, it will result in the control transistor T001 connected to the data trace of the sub-pixel with the same emission color being connected to different multiplexed lines. For example... Figure 8Both the first data line DL and the fourth data line DL drive the red sub-pixel 311. However, the control transistor T001 connected to the first data line DL and the fourth data line DL are electrically connected to different multiplexing lines. The turn-on time of the different multiplexing lines is not the same as that of the scanning lines. This causes the data line DL connected to the same control transistor T001 as the first multiplexing line Mux01 to be pre-charged, while the data line DL connected to the same control transistor T001 as the second multiplexing line Mux02 to be directly charged. This results in different charging voltages for the first data line DL and the fourth data line DL, leading to inconsistent brightness of sub-pixels of the same emitting color and causing display abnormalities.

[0029] In response to the above problems, such as Figure 9 As shown, some other contrast display devices would connect the control transistor of the data trace DL connected to the red subpixel 311 to the same multiplexed line (e.g., Figure 9 The control transistors connected to the data trace DL of the red sub-pixel 311 are all electrically connected to the first multiplexed line Mux01, so that the control transistor T001 connected to the data trace DL of the green sub-pixel 312 is electrically connected to different multiplexed lines (e.g., ...). Figure 9 The control transistor T001 connected to the second data trace DL of the green sub-pixel 312 is electrically connected to the first multiplexing line Mux01, and the control transistor T001 connected to the fifth data trace DL of the green sub-pixel 312 is connected to the second multiplexing line Mux02. This causes the control transistor T001 connected to the data trace DL of the blue sub-pixel 313 to be electrically connected to a different multiplexing line, and causes the control transistor T001 connected to the fan-out trace FL adjacent to the data trace DL of the red sub-pixel 311 to be connected to a different multiplexing line (for example, the control transistor T001 connected to the fan-out trace FL to the left of the fourth data trace DL is connected to the second multiplexing line Mux02, and the control transistor T001 connected to the fan-out trace FL to the left of the tenth data trace DL is connected to the first multiplexing line Mux01). This will cause inconsistent interference to the different data traces connected to the red sub-pixel, resulting in display abnormalities. Therefore, existing display devices using Real RGB arrangement and simultaneously employing mux and FIAA technologies will experience display abnormalities.

[0030] This application provides a display panel and a display device to address the aforementioned technical problems.

[0031] Figure 1 This is a plan view of the display panel provided in an embodiment of this application. Figure 2 This is a first schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in the embodiments of this application. Figure 3 for Figure 2A schematic diagram showing the pixel arrangement of the display panel and the connection relationship between signal lines and transistors. Figure 4 This is a second schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in the embodiments of this application. Figure 5 for Figure 4 A schematic diagram showing the pixel arrangement of the display panel and the connection relationship between signal lines and transistors. Figure 6 A timing diagram of some signal lines in a display panel provided in an embodiment of this application.

[0032] like Figures 1 to 6 As shown, this application embodiment provides a display panel 1, which includes a plurality of pixel units 11. Each pixel unit 11 includes a first sub-pixel unit 111, a second sub-pixel unit 112, and a third sub-pixel unit 113 with different emission colors. In each pixel unit, the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 are arranged sequentially along a first direction X.

[0033] Specifically, for ease of explanation, the following embodiments use the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 as examples, where the light emission colors are red, green, and blue, respectively. However, the embodiments of this application are not limited to this, and the light emission colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit can be green, red, and blue, respectively.

[0034] Specifically, such as Figure 1 As shown, the display panel 1 includes multiple scan lines SCL and multiple data lines Data. Each scan line SCL controls the writing of data signals to a row of pixel units, and each data line inputs data signals to a column of sub-pixel units to make the sub-pixel units display or not display.

[0035] Specifically, such as Figure 1 As shown, in order to reduce the bezel, the data line Data includes a first type of data line Data1 and a second type of data line Data2. The display panel 1 also includes a fan-out connection line FIAA, which is connected to the first type of data line Data1. The first type of data line Data1 is connected to the driver chip through the fan-out connection line FIAA, so that it is not necessary to wrap the wires from both sides of the display panel 1 to the bottom bezel, thereby reducing the bezel of the display panel 1.

[0036] In some embodiments, such as Figures 1 to 6As shown, the display panel 1 includes multiple pixel units 11, each pixel unit 11 including a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged sequentially. Within each pixel unit, the red sub-pixel, green sub-pixel, and blue sub-pixel are arranged sequentially along a first direction X. The display panel 1 includes multiple scan lines SCL, multiple data lines Data, multiple fan-out connection lines FIAA, and multiple signal input lines SL. Each data line Data is connected to a sub-pixel unit with the same emission color, and the multiple data lines Data include multiple first-type data lines Data1 and multiple second-type data lines Data2. The multiple fan-out connection lines FIAA are electrically connected to the first-type data lines Data1, and the multiple data lines Data and the multiple fan-out connection lines FIAA are arranged at intervals along the first direction X. The multiple signal input lines SL, some of which are connected to two second-type data lines SCL. The signal input line SL is electrically connected to two fan-out connection lines FIAA. A first-class control transistor T01 and a second-class control transistor T02 are respectively provided between the signal input line SL and the two corresponding second-class data lines Data2. A first-class control transistor T01 and a second-class control transistor T02 are respectively provided between the signal input line SL and the two corresponding fan-out connection lines FIAA. The gate of the first-class control transistor T01 is connected to the first signal control line Mux1, and the gate of the second-class control transistor T02 is connected to the second signal control line Mux2. The input time period of the effective level of the first signal control line Mux1 does not overlap with the input time period of the effective level of the scan line SCL. The input time period of the effective level of the second signal control line Mux2 overlaps with the input time period of the effective level of the scan line SCL.

[0037] Specifically, the second type of data line Data2 connected to the red sub-pixel is electrically connected to the first type of control transistor T01, and the second type of data line Data2 connected to the green sub-pixel is electrically connected to the second type of control transistor T02.

[0038] This application provides a display panel that uses a fan-out connection line FIAA to connect to a first type of data line Data1. A first type of control transistor T01 and a second type of control transistor T02 are respectively provided between the signal input line SL and the two corresponding second type of data lines Data2. The first type of control transistor T01 and the second type of control transistor T02 are also provided between the signal input line SL and the two corresponding fan-out connection lines FIAA, which can reduce the bezel.

[0039] Meanwhile, in this embodiment, the second type of data line Data2 connected to the red sub-pixel is electrically connected to the first type of control transistor T01, so that all the second type of data lines Data2 connected to the red sub-pixel are controlled by the first signal control line Mux1. The second type of data line Data2 connected to the green sub-pixel is electrically connected to the second type of control transistor T02, so that all the second type of data lines Data2 connected to the green sub-pixel are controlled by the second signal control line Mux2. Since the red sub-pixel and the green sub-pixel are arranged adjacent to each other, the second type of data line Data2 connected to each red sub-pixel is interfered with by the second type of data line Data2 controlled by the second signal control line Mux2. This makes the interference of the second type of data lines connected to each red sub-pixel similar or even the same as that of the adjacent second type of data lines, thereby improving display uniformity and avoiding display abnormalities.

[0040] For example, such as Figure 3 As shown, the first second-class data line Data31, the fourth second-class data line Data34, the seventh second-class data line Data37, and the tenth second-class data line Data40 are all connected to the red sub-pixels, and these second-class data lines are all connected to the first-class control transistor T01. The first-class control transistor T01 is controlled by the same signal control line (i.e., the first signal control line Mux1). The signal input of each red sub-pixel is synchronized, thereby avoiding uneven display caused by asynchronous signal input, and making the display uniformity of each red sub-pixel better. Similarly, the display uniformity of each green sub-pixel is better.

[0041] At the same time, such as Figure 6 As shown, taking the scan line SCL, which includes the first scan line Pscan1 and the second scan line Pscan2, as an example, from... Figure 6 As can be seen, the effective level of the first signal control line Mux1 is staggered with the effective levels of the first scan line Pscan1 and the second scan line Pscan2, while the effective level of the second signal control line Mux2 overlaps with the effective level of the second scan line Pscan2. Therefore, when the data line is written by controlling the first signal control line Mux1 and the second signal control line Mux2, the control transistor is first turned on through the first signal control line Mux1 to input voltage to the data line. When the switching transistor in the pixel driving circuit is turned on by the first scan line Pscan1, the voltage stored on the data line is written, that is, the data line controlled by the first signal control line Mux1 is pre-charged. When the control transistor is turned on by the second signal control line Mux2 to write the data signal, the switching transistor of the second scan line Pscan2 will be turned on at the same time to complete the data writing, that is, the data line controlled by the second signal control line Mux2 is directly charged.

[0042] Because the data lines controlled by the second signal control line Mux2 are directly charged, they are less affected by interference from other signal lines, or even unaffected. However, the data lines controlled by the first signal control line Mux1 are pre-charged and are more susceptible to interference from other signal lines. Therefore, the data lines controlled by the first signal control line Mux1 can be affected by interference from the data lines controlled by the second signal control line Mux2 or the fan-out connection lines of the second signal control line Mux2. When the signal control lines electrically connected to the signal lines on both sides of the data lines controlled by the first signal control line Mux1 are different, it can lead to differences in data writing, resulting in vertical lines.

[0043] In the embodiments of this application, from Figure 3 As can be seen in the embodiments of this application, by making the second type data lines to the right of the first second type data line Data31, the fourth second type data line Data34, the seventh second type data line Data37, and the tenth second type data line Data40 all controlled by the second signal control line Mux2, the interference of the first second type data line Data31, the fourth second type data line Data34, the seventh second type data line Data37, and the tenth second type data line Data40 on the right side of the signal lines is similar or even the same, thereby improving the uniformity of display and avoiding display abnormalities.

[0044] Specifically, the first type of control transistor T01 includes the first subtype control transistor T1 and the second subtype control transistor T3, and the second type of control transistor T02 includes the third subtype control transistor T2 and the fourth subtype control transistor T4.

[0045] Specifically, such as Figure 1 As shown, the display panel 1 includes a display area 101 and a non-display area 102. The non-display area 102 can be disposed on one side, two sides, three sides or four sides of the display area 101. The non-display area 102 can be bent to the back side of the display panel 1.

[0046] Specifically, such as Figures 1 to 6As shown, the display area 101 contains an array of pixel units 11 arranged along a first direction X and a second direction Y. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. Each pixel unit 11 includes multiple sub-pixel units, and the emission color of each column of sub-pixel units is the same. The non-display area 102 contains a driver chip 12, which integrates a multiplexing control circuit. The multiplexing control circuit includes a signal control line Mux, a first type of control transistor T01, and a second type of control transistor T02. The signal control line includes a first signal control line Mux1 and a second signal control line Mux2. The first type of control transistor T01 includes a first sub-type control transistor T1, a second sub-type control transistor T3, and a third sub-type control transistor. The second type of control transistor T02 includes a third sub-type control transistor T2, a second sub-type control transistor, and a fourth sub-type control transistor T4. By integrating the multiplexing control circuit into the driver chip 12, the bezel can be reduced.

[0047] Specifically, such as Figure 1 As shown, the display area 101 is equipped with a first-type data line Data1, a second-type data line Data2, and a fan-out connection line FIAA. Figure 1 As can be seen, the first type of data line, Data1, can be connected to the driver chip 12 without being directly connected to the driver chip 12. Instead, it can be connected to the driver chip 12 through the adapter cable ZL and the fan-out connection cable FIAA to realize the signal input, thereby reducing the bottom and left and right bezels. The second type of data line, Data2, can be directly connected to the driver chip 12.

[0048] It is understood that, for ease of explanation, in this application embodiment, some traces directly connected to the driver chip and some traces connected to the driver chip through fan-out connection lines FIAA are respectively named second type data lines and first type data lines. However, in actual design, the width and other designs of the first type data line Data1 and the second type data line Data2 may be the same.

[0049] Specifically, for ease of explanation, the vertical and horizontal portions of a trace connecting the first type of data line Data1 are named the fan-out connector FIAA and the adapter ZL, respectively. However, the fan-out connector FIAA and the adapter ZL transmit the same signal, and their width and other designs can be identical.

[0050] It is understood that the embodiments of this application show the design of the first type of data line Data1, the second type of data line Data2, the fan-out connecting line and the adapter line on the left side. It is also understood that the first type of data line Data1, the second type of data line Data2, the fan-out connecting line and the adapter line on the right side can be symmetrical to the first type of data line Data1, the second type of data line Data2, the fan-out connecting line and the adapter line on the left side, respectively.

[0051] It is understood that, in this embodiment of the application, due to space limitations, two signal lines can be set in the area corresponding to each column of sub-pixel units. In the setting area corresponding to the second type of data line Data2, the two signal lines on each column of sub-pixel units can be composed of: one second type of data line Data2 and one fan-out connection line FIAA; or one second type of data line Data2 and one high-potential power line VDD. In the setting area corresponding to the first type of data line Data1, the two signal lines on each column of sub-pixel units can be composed of: one first type of data line Data1 and one low-potential power line; or one first type of data line Data1 and one high-potential power line VDD. The arrangement of the signal lines in the setting area of ​​the first type of data line Data1 is the same as the arrangement of the same number of signal lines in the setting area of ​​the second type of data line Data2. The only difference is that some signal lines in the setting area of ​​the first type of data line Data1 are used as low-potential power lines, while some signal lines in the setting area of ​​the second type of data line Data2 are used as fan-out connection lines FIAA.

[0052] In some embodiments, the fan-out connection line FIAA electrically connected to the first sub-pixel unit 111 is electrically connected to the second sub-class control transistor T3, and the fan-out connection line FIAA electrically connected to the second sub-pixel unit 112 is electrically connected to the fourth sub-class control transistor T4.

[0053] Specifically, as can be seen from the above embodiments, when the data lines connected to red sub-pixels of the same emission color are controlled by different signal control lines, uneven display will occur. Similarly, when the fan-out connection lines connected to red sub-pixels of the same emission color are controlled by different signal control lines, the charging time of each red sub-pixel may be different, leading to uneven display. Figure 3 As shown, in this embodiment of the application, the first fan-out connection line FIAA1 and the fifth fan-out connection line FIAA5 connecting the red sub-pixel are both electrically connected to the second sub-class control transistor T3, and the second fan-out connection line FIAA2 and the fourth fan-out connection line FIAA4 connecting the green sub-pixel are both connected to the fourth sub-class control transistor T4. This ensures that the signal input of the red sub-pixel is synchronized, and the signal input of the green sub-pixel is synchronized, thereby avoiding uneven display caused by asynchronous signal input.

[0054] Specifically, such as Figure 3 As shown, taking a ratio of 2:1 between data lines Data and fan-out connection lines FIAA as an example, a repeating unit 21 can include 12 second-class data lines Data2 and 6 fan-out connection lines FIAA.

[0055] like Figure 2As shown, the first type of data line Data1 includes the first first type of data line Data11, the second first type of data line Data12, the third first type of data line Data13, the fourth first type of data line Data14, the fifth first type of data line Data15, the sixth first type of data line Data16, the seventh first type of data line Data17, the eighth first type of data line Data18, the ninth first type of data line Data19, the tenth first type of data line Data20, the eleventh first type of data line Data21, and the twelfth first type of data line Data22, which are set sequentially. Each first type of data line can be set and connected to a corresponding column of sub-pixel units.

[0056] Specifically, such as Figure 2 As shown, the second type of data line Data2 includes the following data lines arranged sequentially: Data31 (first), Data32 (second), Data33 (third), Data34 (fourth), Data35 (fifth), Data36 (sixth), Data37 (seventh), Data38 (eighth), Data39 (ninth), Data40 (tenth), Data41 (eleventh), Data42 (twelfth), and Data42 (thirteenth). Data lines ta43, 14th, 15th, 16th, 17th, 18th, 19th, 20th, 21st, 22nd, 23rd, and 24th, respectively, can be set and connected to a corresponding column of sub-pixel units.

[0057] Specifically, such as Figure 2As shown, the fan-out connection line FIAA includes the first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, the sixth fan-out connection line FIAA6, the seventh fan-out connection line FIAA7, the eighth fan-out connection line FIAA8, the ninth fan-out connection line FIAA9, the tenth fan-out connection line FIAA10, the eleventh fan-out connection line FIAA11, and the twelfth fan-out connection line FIAA12. Each fan-out connection line can be set and connected to a first-type data line Data1 corresponding to a column of sub-pixel units.

[0058] Specifically, such as Figure 2 As shown, the first fan-out connector FIAA1, the second fan-out connector FIAA2, the third fan-out connector FIAA3, the fourth fan-out connector FIAA4, the fifth fan-out connector FIAA5, the sixth fan-out connector FIAA6, the seventh fan-out connector FIAA7, the eighth fan-out connector FIAA8, the ninth fan-out connector FIAA9, the tenth fan-out connector FIAA10, the eleventh fan-out connector FIAA11, and the twelfth fan-out connector FIAA12 are respectively connected to the tenth Class 1 data line. Connect Data20, 11th Class I Data Line, Data21, 9th Class I Data Line, Data19, 8th Class I Data Line, Data18, 7th Class I Data Line, Data17, 12th Class I Data Line, Data22, 4th Class I Data Line, Data14, 5th Class I Data Line, Data15, 3rd Class I Data Line, Data13, 2nd Class I Data Line, Data12, 1st Class I Data Line, Data11, and 6th Class I Data Line.

[0059] Specifically, such as Figure 5As shown, the first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, the sixth fan-out connection line FIAA6, the seventh fan-out connection line FIAA7, the eighth fan-out connection line FIAA8, the ninth fan-out connection line FIAA9, the tenth fan-out connection line FIAA10, the eleventh fan-out connection line FIAA11, and the twelfth fan-out connection line FIAA12 are respectively connected to the eleventh type of data. Connect lines Data21, Data20 (10th Class I Data Line), Data19 (9th Class I Data Line), Data18 (8th Class I Data Line), Data17 (7th Class I Data Line), Data22 (12th Class I Data Line), Data15 (5th Class I Data Line), Data14 (4th Class I Data Line), Data13 (3rd Class I Data Line), Data12 (2nd Class I Data Line), Data11 (1st Class I Data Line), and Data16 (6th Class I Data Line).

[0060] In some embodiments, such as Figure 2 , Figure 3 As shown, in the first direction X, every three second-type data lines Data2 are respectively connected to the red sub-pixel, green sub-pixel and blue sub-pixel in the pixel unit 11;

[0061] In the first direction X, within the six adjacent second-type data lines Data2 and three fan-out connection lines FIAA, the three second-type data lines Data2 connected to one pixel unit 11, the two fan-out connection lines electrically connected to the red sub-pixel and the green sub-pixel respectively, the three second-type data lines Data2 connected to another pixel unit 11, and the fan-out connection line electrically connected to the blue sub-pixel are arranged in sequence.

[0062] The first type of control transistor T01 includes a first sub-type control transistor T1 and a second sub-type control transistor T3. The second type of control transistor T02 includes a third sub-type control transistor T2 and a fourth sub-type control transistor T4. The second type of data line Data2 connected to the red sub-pixel is electrically connected to the first sub-type control transistor T1, and the second type of data line Data2 connected to the green sub-pixel is electrically connected to the third sub-type control transistor T2. The fan-out connection line electrically connected to the red sub-pixel is electrically connected to the second sub-type control transistor T3, and the fan-out connection line electrically connected to the green sub-pixel is electrically connected to the fourth sub-type control transistor T4. By connecting the fan-out connection line electrically connected to the red sub-pixel to the second sub-type control transistor T3 and the fan-out connection line electrically connected to the green sub-pixel to the fourth sub-type control transistor T4, the data line or fan-out connection line electrically connected to the red sub-pixel is controlled by the first signal control line, and the data line or fan-out connection line electrically connected to the green sub-pixel is electrically connected to the second signal control line, resulting in better display uniformity of the first sub-pixel unit 111 and the second sub-pixel unit 112.

[0063] In some embodiments, such as Figure 2 , Figure 3 As shown, the fan-out connection line FIAA, which is partially electrically connected to the green sub-pixel, and the second type of data line Data2, which is partially electrically connected to the red sub-pixel, are arranged adjacent to each other.

[0064] Specifically, such as Figure 2 , Figure 3 As shown, the second fan-out connection line FIAA2 is connected to the green sub-pixel via the eleventh first-class data line Data21. The second fan-out connection line FIAA2 and the fourth second-class data line Data34, which is electrically connected to the red sub-pixel, are arranged adjacent to each other. The fifth fan-out connection line FIAA5 is connected to the red sub-pixel via the seventh first-class data line Data17. The fifth fan-out connection line FIAA5 and the tenth second-class data line Data40, which is electrically connected to the red sub-pixel, are arranged adjacent to each other.

[0065] In some embodiments, such as Figure 2 , Figure 3As shown, among the twelve adjacent Type II data lines Data12 and six fan-out connection lines FIAA, the first fan-out connection line FIAA1 is electrically connected to a red sub-pixel, the second fan-out connection line FIAA2 is electrically connected to a green sub-pixel, the third fan-out connection line FIAA3 is electrically connected to a blue sub-pixel, the fourth fan-out connection line FIAA4 is electrically connected to another green sub-pixel, the fifth fan-out connection line FIAA5 is electrically connected to another red sub-pixel, and the sixth fan-out connection line FIAA6 is electrically connected to another blue sub-pixel.

[0066] The first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, and the sixth fan-out connection line FIAA6 are arranged sequentially along the first direction X. This ensures that the signal output sequence of the fan-out connection lines FIAA is consistent with the signal output mode of the driver chip, eliminating the need to change the signal output mode of the driver chip.

[0067] Specifically, the above embodiments illustrate the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit. It can be understood that the connection relationship between the seventh fan-out connection line FIAA7 to the twelfth fan-out connection line FIAA12 and the sub-pixel unit can be found in the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit.

[0068] In some embodiments, the third fan-out connection line FIAA3 is connected to the second subclass control transistor T3, and the sixth fan-out connection line FIAA6 is connected to the fourth subclass control transistor T4;

[0069] Among the twelve adjacent second-class data lines Data2 and six fan-out connection lines FIAA, among the four second-class data lines Data2 that connect to the third sub-pixel unit 113, two adjacent second-class data lines Data2 are electrically connected to the first sub-class control transistor T1 and the third sub-class control transistor T2, respectively.

[0070] Specifically, in order to reduce the number of control lines, considering that the blue sub-pixel has a small impact on brightness and can be compensated by the driver chip, a portion of the data line or fan-out connection line connected to the blue sub-pixel can be electrically connected to the first signal control line, and the other portion can be electrically connected to the second signal control line.

[0071] Specifically, such as Figure 2 , Figure 3As shown, taking a total of 600 signal input lines, i.e., a total of 1200 data lines, as an example, the connection relationships between the first Class II data line Data31 to the tenth Class II data line Data42, and the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6, and the control transistors, signal control lines, and signal input lines are explained. The connection relationships between other Class II data lines and fan-out connection lines and the control transistors, signal control lines, and signal input lines can be found in the following explanation.

[0072] Specifically, such as Figure 3 As shown, the first subclass control transistor T1 includes a first-class first control transistor T11, a first-class second control transistor T12, a first-class third control transistor T13, a first-class fourth control transistor T14, a first-class fifth control transistor T15, and a first-class sixth control transistor T16; the third subclass control transistor T2 includes a second-class first control transistor T21, a second-class second control transistor T22, a second-class third control transistor T23, a second-class fourth control transistor T24, a second-class fifth control transistor T25, and a second-class sixth control transistor T26; and the second subclass control transistor T3 includes... The third type of first control transistor T31, the third type of second control transistor T32, and the third type of third control transistor T33; the fourth subtype of control transistor T4 includes the fourth type of first control transistor T41, the fourth type of second control transistor T42, and the fourth type of third control transistor T43; the signal input line SL includes the first signal input line S1, the second signal input line S2, the third signal input line S3, the fourth signal input line S4, the fifth signal input line S5, the sixth signal input line S6, the fifth 198th signal input line S598, the fifth 199th signal input line S599, and the sixth 100th signal input line S600.

[0073] like Figure 3 As shown, the high-potential power line VDD, the second-class data line Data2, and the fan-out connection line FIAA are arranged alternately. The first fan-out connection line FIAA1 and the second fan-out connection line FIAA2 are arranged between the third second-class data line Data33 and the fourth second-class data line Data34. The third fan-out connection line FIAA3 is arranged between the sixth second-class data line Data36 and the high-potential power line VDD. The fourth fan-out connection line FIAA4 and the fifth fan-out connection line FIAA5 are arranged between the ninth second-class data line Data39 and the tenth second-class data line Data40. The sixth fan-out connection line FIAA6 is arranged after the twelfth second-class data line Data42.

[0074] like Figure 3As shown, the first signal input line S1 is connected to one electrode of the first type first control transistor T11 and the second type first control transistor T21, and the other electrode of the first type first control transistor T11 and the second type first control transistor T21 is connected to the first type second data line Data31 and the second type second data line Data32, respectively; the second signal input line S2 is connected to one electrode of the first type second control transistor T12 and the second type second control transistor T22, and the other electrode of the first type second control transistor T12 and the second type second control transistor T22 is connected to the fourth type second data line Data34 and the third type second data line Data33, respectively.

[0075] like Figure 3 As shown, the third signal input line S3 is connected to one electrode of the first type third control transistor T13 and the second type third control transistor T23, and the other electrode of the first type third control transistor T13 and the second type third control transistor T23 is connected to the sixth type second data line Data36 and the fifth type second data line Data35, respectively; the fourth signal input line S4 is connected to one electrode of the first type fourth control transistor T14 and the second type fourth control transistor T24, and the other electrode of the first type fourth control transistor T14 and the second type fourth control transistor T24 is connected to the seventh type second data line Data37 and the eighth type second data line Data38, respectively.

[0076] like Figure 3 As shown, the fifth signal input line S5 is connected to one electrode of the first type fifth control transistor T15 and the second type fifth control transistor T25. The other electrodes of the first type fifth control transistor T15 and the second type fifth control transistor T25 are connected to the tenth type second data line Data40 and the ninth type second data line Data39, respectively. The sixth signal input line S6 is connected to one electrode of the first type sixth control transistor T16 and the second type sixth control transistor T26. The other electrodes of the first type sixth control transistor T16 and the second type sixth control transistor T26 are connected to the twelfth type second data line Data42 and the eleventh type second data line Data41, respectively.

[0077] like Figure 3As shown, signal input line S600 is connected to one electrode of the first control transistor T31 of the third type and the first control transistor T41 of the fourth type. The other electrodes of the first control transistor T31 of the third type and the first control transistor T41 of the fourth type are connected to the first fan-out connection line FIAA1 and the second fan-out connection line FIAA2, respectively. Signal input line S599 is connected to one electrode of the second control transistor T32 of the third type and the second control transistor T42 of the fourth type. The other electrodes of the second control transistor T32 of the third type and the second control transistor T42 of the fourth type are connected to the third fan-out connection line FIAA3 and the fourth fan-out connection line FIAA4, respectively. Signal input line S598 is connected to one electrode of the third control transistor T33 of the third type and the third control transistor T43 of the fourth type. The other electrodes of the third control transistor T33 of the third type and the third control transistor T43 of the fourth type are connected to the fifth fan-out connection line FIAA5 and the sixth fan-out connection line FIAA6, respectively.

[0078] In some embodiments, the fan-out connection line FIAA electrically connected to the red sub-pixel and the second type of data line Data2 electrically connected to the red sub-pixel are arranged adjacent to each other. By arranging the fan-out connection line FIAA electrically connected to the red sub-pixel and the second type of data line Data2 electrically connected to the red sub-pixel adjacent to each other, the second type of data line connected to each red sub-pixel is subject to interference from the fan-out connection line controlled by the first signal control line. This makes the interference of the fan-out connection lines of the second type of data lines connected to each red sub-pixel similar or even consistent, improving display uniformity and avoiding vertical lines.

[0079] Specifically, compared to the embodiment that only improves the interference of the second type of data lines connected to the first sub-pixel unit with adjacent second type of data lines, this embodiment further improves the interference of the second type of data lines connected to the first sub-pixel unit with fan-out connection lines, further improving display uniformity and display effect.

[0080] In some embodiments, such as Figure 4 , Figure 5 As shown, among the twelve adjacent Type II data lines Data2 and six fan-out connection lines FIAA, the first fan-out connection line FIAA1 is electrically connected to a green sub-pixel, the second fan-out connection line FIAA2 is electrically connected to a red sub-pixel, the third fan-out connection line FIAA3 is electrically connected to a blue sub-pixel, the fourth fan-out connection line FIAA4 is electrically connected to another green sub-pixel, the fifth fan-out connection line FIAA5 is electrically connected to another red sub-pixel, and the sixth fan-out connection line FIAA6 is electrically connected to another blue sub-pixel.

[0081] The first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, and the sixth fan-out connection line FIAA6 are sequentially arranged along the first direction X. This ensures that the interference from the fan-out connection lines on the second type of data lines connected to the first sub-pixel unit is similar or even consistent, improving display uniformity and avoiding vertical lines.

[0082] Specifically, it can be seen that the second fan-out connection line FIAA2 and the fifth fan-out connection line FIAA5 to the left of the fourth Type II data line Data34 and the tenth Type II data line Data40 connected to the red sub-pixels are all controlled by the second signal control line Mux2. This makes the Type II data lines connected to each red sub-pixel subject to similar or even identical interference from the signal lines on the left, thereby improving display uniformity and avoiding display abnormalities.

[0083] Specifically, the above embodiments illustrate the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit. It can be understood that the connection relationship between the seventh fan-out connection line FIAA7 to the twelfth fan-out connection line FIAA12 and the sub-pixel unit can be found in the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit.

[0084] In some embodiments, the third fan-out connection line FIAA3 is connected to the second subclass control transistor T3, and the sixth fan-out connection line FIAA6 is connected to the fourth subclass control transistor T4;

[0085] Among them, in the twelve adjacent second-type data lines Data2 and the six fan-out connection lines FIAA, the four second-type data lines Data2 connecting the third sub-pixel unit 113 are respectively connected to a first sub-type control transistor T1, a third sub-type control transistor T2, another third sub-type control transistor T2 and another first sub-type control transistor T1.

[0086] Specifically, in order to reduce the number of control lines, considering that the blue sub-pixel has a small impact on brightness and can be compensated by the driver chip, a portion of the data line or fan-out connection line connected to the blue sub-pixel can be electrically connected to the first signal control line, and the other portion can be electrically connected to the second signal control line.

[0087] Specifically, such as Figure 4 , Figure 5As shown, taking a total of 600 signal input lines (i.e., 1200 data lines) as an example, the connection relationships between the second-class data lines and fan-out connection lines and the control transistors, signal control lines, and signal input lines are explained using the first second-class data line Data31 to the tenth second-class data line Data42 and the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 as examples. The connection relationships between other second-class data lines and fan-out connection lines and the control transistors, signal control lines, and signal input lines can be found in the following description.

[0088] Specifically, for Figure 5 The connection relationships of each signal line and transistor in the diagram are as follows: Figure 3 The identical connections between the signal lines and transistors in the diagram will not be repeated here. Figure 5 The connection relationships of each signal line and transistor in the diagram are as follows: Figure 3 The differences in the connection relationships between the various signal lines and transistors are as follows:

[0089] like Figure 5 As shown, the second signal input line S2 is connected to one electrode of the first type second control transistor T12 and the second type third control transistor T23, and the other electrode of the first type second control transistor T12 and the second type third control transistor T23 is connected to the third type second data line Data33 and the sixth type second data line Data36, respectively; the third signal input line S3 is connected to one electrode of the first type third control transistor T13 and the second type second control transistor T22, and the other electrode of the first type third control transistor T13 and the second type second control transistor T22 is connected to the fourth type second data line Data34 and the fifth type second data line Data35, respectively.

[0090] like Figure 5 As shown, signal input line S600 is connected to one electrode of the first control transistor T31 of the third type and the first control transistor T41 of the fourth type. The other electrodes of the first control transistor T31 of the third type and the first control transistor T41 of the fourth type are connected to the second fan-out connection line FIAA2 and the first fan-out connection line FIAA1, respectively. Signal input line S599 is connected to one electrode of the second control transistor T32 of the third type and the third control transistor T43 of the fourth type. The other electrodes of the second control transistor T32 of the third type and the third control transistor T43 of the fourth type are connected to the third fan-out connection line FIAA3 and the sixth fan-out connection line FIAA6, respectively. Signal input line S598 is connected to one electrode of the third control transistor T33 of the third type and the second control transistor T42 of the fourth type. The other electrodes of the third control transistor T33 of the third type and the second control transistor T42 of the fourth type are connected to the fifth fan-out connection line FIAA5 and the fourth fan-out connection line FIAA4, respectively.

[0091] In some embodiments, such as Figure 3 , Figure 5 As shown, the display panel 1 includes a repeating unit 21, which includes twelve Type II data lines (Data2) and six fan-out connection lines (FIAA).

[0092] Each of the fan-out connecting lines is connected to a first type of data line, and twelve second type data lines (Data2) and six fan-out connecting lines (FIAA) are correspondingly set to the four columns of pixel units 11.

[0093] Specifically, such as Figure 2 , Figure 4 As shown, twelve first-type data lines Data1 are configured corresponding to four columns of pixel units 11.

[0094] Specifically, it is understood that one or more repeating units can be set in the display panel, and the repeating units on both sides of the display panel can be symmetrically arranged. It is also understood that the arrangement of other type II data cables and fan-out connection cables can be found in [reference needed]. Figures 2 to 5 The arrangement of repeating units in the display panel is such that the first type of data lines can all be located at the edge of the display panel. The connection relationship between other repeating units and the first type of data lines can be found in [reference needed]. Figures 2 to 5 Specifically, you can Figure 2 , Figure 4 Other Type II data lines and fan-out connection lines are set on the right side of the repeating unit. Figure 2 , Figure 4 Other Type 1 data lines are set to the left of the Type 1 data lines. These other Type 1 data lines can be connected to other fan-out cables. Figure 2 , Figure 4 Connect above the repeating unit in the middle.

[0095] Specifically, for the thirteenth type 2 data line, Data43, since there is a high-potential power line VDD between it and the fan-out connection line, it is less affected by the interference from the fan-out connection line or even not affected at all, so the display panel can display normally.

[0096] Specifically, such as Figure 3 , Figure 5 As shown, the embodiments of this application use a P-type transistor as an example for illustration, but the embodiments of this application are not limited to this. The control transistor can be an N-type transistor, or partly a P-type transistor and partly an N-type transistor.

[0097] Specifically, the display panel can be an organic light-emitting diode (OLED) display panel.

[0098] Specifically, the above embodiments have described the display panel in detail from aspects such as pixel arrangement and signal line connection. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the display panel can be an organic light-emitting diode display panel, and the light emission colors of the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit can be red, green and blue, respectively.

[0099] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0100] Specifically, the display device may also include a control board and a power supply.

[0101] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0102] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0103] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0104] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel units, each pixel unit comprising a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit of different emitting colors. Within each pixel unit, the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are sequentially arranged along a first direction. Multiple scan lines; Multiple data lines, each of which is connected to a sub-pixel unit of the same luminous color, and the multiple data lines include multiple first-type data lines and multiple second-type data lines; Multiple fan-out connecting lines are electrically connected to the first type of data lines, and the multiple data lines and the multiple fan-out connecting lines are arranged at intervals along a first direction; Multiple signal input lines are provided. Some of the signal input lines are electrically connected to two second-type data lines, and some of the signal input lines are electrically connected to two fan-out connection lines. A first-type control transistor and a second-type control transistor are respectively provided between each signal input line and the corresponding two second-type data lines. A first-type control transistor and a second-type control transistor are respectively provided between each signal input line and the corresponding two fan-out connection lines. The gate of the first-type control transistor is connected to a first signal control line, and the gate of the second-type control transistor is connected to a second signal control line. The input time period of the effective level of the first signal control line does not overlap with the input time period of the effective level of the scan line, while the input time period of the effective level of the second signal control line overlaps with the input time period of the effective level of the scan line. Wherein, the second type of data line connected to the first sub-pixel unit is electrically connected to the first type of control transistor, and the second type of data line connected to the second sub-pixel unit is electrically connected to the second type of control transistor; In the first direction, every three second-type data lines are respectively connected to the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit in a pixel unit; wherein, in the first direction, within the six adjacent second-type data lines and three fan-out connection lines, the three second-type data lines connected to a pixel unit, the two fan-out connection lines electrically connected to the first sub-pixel unit and the second sub-pixel unit respectively, the three second-type data lines connected to another pixel unit, and the fan-out connection line electrically connected to the third sub-pixel unit are arranged sequentially; the first-type control transistor includes a first sub-type control transistor and a second sub-type control transistor, the second-type control transistor includes a third sub-type control transistor and a fourth sub-type control transistor, the second-type data lines connected to the first sub-pixel unit are electrically connected to the first sub-type control transistor, the second-type data lines connected to the second sub-pixel unit are electrically connected to the third sub-type control transistor; the fan-out connection lines electrically connected to the first sub-pixel unit are electrically connected to the second sub-type control transistor, and the fan-out connection lines electrically connected to the second sub-pixel unit are electrically connected to the fourth sub-type control transistor.

2. The display panel according to claim 1, characterized in that, The fan-out connection line partially electrically connected to the second sub-pixel unit and the second type of data line electrically connected to the first sub-pixel unit are arranged adjacent to each other.

3. The display panel according to claim 2, characterized in that, In the twelve adjacent second-type data lines and six fan-out connection lines, the first fan-out connection line is electrically connected to a first sub-pixel unit, the second fan-out connection line is electrically connected to a second sub-pixel unit, the third fan-out connection line is electrically connected to a third sub-pixel unit, the fourth fan-out connection line is electrically connected to another second sub-pixel unit, the fifth fan-out connection line is electrically connected to another first sub-pixel unit, and the sixth fan-out connection line is electrically connected to another third sub-pixel unit. The first fan-out connecting line, the second fan-out connecting line, the third fan-out connecting line, the fourth fan-out connecting line, the fifth fan-out connecting line, and the sixth fan-out connecting line are arranged sequentially along the first direction.

4. The display panel according to claim 3, characterized in that, The third fan-out connection line is connected to the second subclass control transistor, and the sixth fan-out connection line is connected to the fourth subclass control transistor; Among the twelve adjacent second-class data lines and six fan-out connection lines, in the four second-class data lines connecting the third sub-pixel unit, two adjacent second-class data lines are electrically connected to the first sub-class control transistor and the third sub-class control transistor, respectively.

5. The display panel according to claim 1, characterized in that, The fan-out connection line electrically connected to the first sub-pixel unit and the second type of data line electrically connected to the first sub-pixel unit are arranged adjacent to each other.

6. The display panel according to claim 5, characterized in that, In the twelve adjacent second-type data lines and six fan-out connection lines, the first fan-out connection line is electrically connected to a second sub-pixel unit, the second fan-out connection line is electrically connected to a first sub-pixel unit, the third fan-out connection line is electrically connected to a third sub-pixel unit, the fourth fan-out connection line is electrically connected to another second sub-pixel unit, the fifth fan-out connection line is electrically connected to another first sub-pixel unit, and the sixth fan-out connection line is electrically connected to another third sub-pixel unit. The first fan-out connecting line, the second fan-out connecting line, the third fan-out connecting line, the fourth fan-out connecting line, the fifth fan-out connecting line, and the sixth fan-out connecting line are arranged sequentially along the first direction.

7. The display panel according to claim 6, characterized in that, The third fan-out connection line is connected to the second subclass control transistor, and the sixth fan-out connection line is connected to the fourth subclass control transistor; Among the twelve adjacent second-type data lines and six fan-out connection lines, the four second-type data lines connecting the third sub-pixel unit are respectively connected to a first-type control transistor, a third-type control transistor, another third-type control transistor, and another first-type control transistor.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display panel includes a repeating unit, which includes twelve Type II data lines and six fan-out connection lines; Each of the fan-out connecting lines is connected to a first type of data line, and the twelve second type of data lines and six fan-out connecting lines are correspondingly arranged with the four columns of pixel units.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

Images