Gamma circuit, data driving circuit and display panel

Abstract

The embodiment of the application discloses a gamma circuit, a data driving circuit and a display panel. The gamma circuit comprises a voltage generating module and a voltage adjusting module. The voltage generating module is used for generating an initial gamma voltage sequence according to a power voltage and transmitting the initial gamma voltage sequence to the voltage adjusting module. The voltage adjusting module is used for adjusting the voltage of the initial gamma voltage sequence according to a control signal, generating at least two groups of gamma voltage sequences, and transmitting different gamma voltage sequences to different data driving circuits respectively. The control signal is received from a time sequence control circuit. The gamma voltage sequence is used for controlling the data driving circuit to output a data voltage to a pixel unit in a display area in cooperation with a data signal. By providing different gamma voltage sequences to different data driving circuits, the problem of insufficient brightness of the pixel unit caused by the advance pull-down of the scanning signal can be compensated.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to gamma circuits, data driving circuits, and display panels. Background Technology

[0002] With the development of display technology, the size and refresh rate of display panels have gradually increased, and the scan lines have become longer. After passing through a certain length of scan line, the scan signal experiences a delay due to the low-pass filtering effect. Because of this falling edge delay, the data signal for the second row of pixels may be output before the first row's scan signal reaches the TFT turn-off voltage, causing the data signal for the second row of pixels to be incorrectly charged to the first row, resulting in poor display quality. Current solutions involve pre-controlling the pull-down of the first row's scan signal to avoid this mischarging. However, because the delay of the scan signal in the center of the display panel is higher than at the sides, pre-pulling down the scan signal results in shorter data signal reception time in the side areas, leading to insufficient charging and consequently, insufficient brightness in the side display areas.

[0003] Therefore, how to avoid insufficient pixel brightness on both sides of the display panel due to incorrect charging is an urgent problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art, this application provides a gamma circuit, a data driving circuit, and a display panel that can effectively compensate for insufficient pixel brightness caused by premature pull-down of the scan signal.

[0005] This application provides a gamma circuit, including a voltage generation module and a voltage adjustment module. The voltage generation module generates an initial gamma voltage sequence based on the power supply voltage and transmits it to the voltage adjustment module. The voltage adjustment module adjusts the voltage of the initial gamma voltage sequence based on a control signal and generates at least two sets of gamma voltage sequences. The different gamma voltage sequences are then transmitted to different data driving circuits. The control signal is received from a timing control circuit, and the gamma voltage sequences are used to control the data driving circuit to output data voltages to pixel units within the display area in conjunction with the data signal.

[0006] Optionally, the voltage adjustment module includes an amplifier, a first resistor, a second resistor, a first adjustment unit, a second adjustment unit, and a third adjustment unit. The first resistor is electrically connected between the inverting input and the output input of the amplifier. The second resistor is electrically connected between the non-inverting input of the amplifier and the voltage generation module. The first adjustment unit, the second adjustment unit, and the third adjustment unit are connected in parallel between the ground terminal and the inverting input of the amplifier. The first adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a first gamma voltage sequence. The second adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a second gamma voltage sequence. The third adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a third gamma voltage sequence.

[0007] Optionally, the first gamma voltage sequence, the second gamma voltage sequence, and the third gamma voltage sequence each include a first gamma voltage, a second gamma voltage, a third gamma voltage, and a fourth gamma voltage. The first gamma voltage and the fourth gamma voltage are symmetrical about a central reference voltage, and the second gamma voltage and the third gamma voltage are also symmetrical about a central reference voltage. The first gamma voltage and the second gamma voltage are used to generate a positive data signal, and the third gamma voltage and the fourth gamma voltage are used to generate a negative data signal. The difference between the first gamma voltage and the central reference voltage is greater than the difference between the second gamma voltage and the central reference voltage. In the first gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is the first gamma voltage difference; in the second gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is the second gamma voltage difference; and in the third gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is the third gamma voltage difference. The first gamma voltage difference is greater than the second gamma voltage difference, and the second gamma voltage difference is greater than the third gamma voltage difference.

[0008] Optionally, the first adjustment unit includes a first switching transistor and a third resistor, the second adjustment unit includes a second switching transistor and a fourth resistor, and the third adjustment unit includes a third switching transistor. The control terminal of the first switching transistor is electrically connected to a timing control circuit, the first conductive terminal of the first switching transistor is electrically connected to a ground terminal, the second conductive terminal of the first switching transistor is electrically connected to a first terminal of the third resistor, and the second terminal of the third resistor is electrically connected to the inverting input of the amplifier. The control terminal of the second switching transistor is electrically connected to the timing control circuit, the first conductive terminal of the second switching transistor is electrically connected to the ground terminal, the second conductive terminal of the second switching transistor is electrically connected to a first terminal of the fourth resistor, and the second terminal of the fourth resistor is connected to the inverting input of the amplifier. The control terminal of the third switching transistor is electrically connected to the timing control circuit, and the first conductive terminal of the third switching transistor is electrically connected to... In the timing control circuit, the first conductive terminal of the third switch is electrically connected to the ground terminal, and the second conductive terminal of the third switch is electrically connected to the inverting input of the amplifier. The resistance value of the third resistor is greater than the resistance value of the fourth resistor. The first switch is turned on according to a first control signal to control the third resistor to be electrically connected to the inverting input of the amplifier. The first resistor and the third resistor, together with the amplifier, adjust the initial gamma voltage sequence to obtain a first gamma voltage sequence. The second switch is turned on according to a second control signal to control the fourth resistor to be electrically connected to the inverting input of the amplifier. The first resistor and the fourth resistor, together with the amplifier, adjust the initial gamma voltage sequence to obtain a second gamma voltage sequence. The third switch is turned on according to a third control signal to use the initial gamma voltage sequence as the third gamma voltage sequence.

[0009] This application embodiment also provides a data driving circuit, which is used to receive an initial data signal and a control signal from a timing control circuit and a gamma voltage sequence from a gamma circuit, and output a corresponding data voltage to the pixel unit in the display area. The data driving circuit includes an input control module and a logic processing module. The input control module is used to receive the initial data signal and the control signal, and receive the gamma voltage sequence under the control of the control signal, and transmit the initial data signal and the gamma voltage sequence to the logic processing module. The logic processing module generates a grayscale data signal based on the initial data signal and the gamma voltage sequence, and the grayscale data signal is used to form the data voltage.

[0010] Optionally, the input control module includes a fourth switch and a first capacitor. The control terminal of the fourth switch is electrically connected to the timing control circuit, the first conductive terminal of the fourth switch is electrically connected to the gamma circuit, and the second conductive terminal of the fourth switch is electrically connected to the logic processing module. The first capacitor is electrically connected between the ground terminal and the second conductive terminal of the fourth switch. The fourth switch is used to turn on according to the control signal output by the timing control circuit to transmit the gamma voltage sequence output by the gamma circuit to the logic control module.

[0011] This application embodiment also provides a display panel, the non-display area of ​​which includes a timing control circuit, a gamma circuit as described in claims 1-4, and a plurality of data driving circuits as described in claims 5-6. The timing control circuit controls the data driving circuit to output data signals including continuous first time period, second time period, and third time period. The plurality of data driving circuits includes a first data driving circuit, a second data driving circuit, and a third data driving circuit. During the first time period, the timing control circuit outputs a first control signal to the gamma circuit and the data driving circuit. The gamma circuit outputs a first gamma voltage sequence according to the first control signal. The data driving circuit receives the first gamma voltage sequence according to the first control signal; during the second time period, the timing control circuit outputs a second control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a second gamma voltage sequence according to the second control signal, and the second data driving circuit receives the second gamma voltage sequence according to the second control signal; during the third time period, the timing control circuit outputs a third control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a third gamma voltage sequence according to the third control signal, and the third data driving circuit receives the third gamma voltage sequence according to the third control signal.

[0012] Optionally, the display area of ​​the display panel includes a first sub-display area, a second sub-display area, and a third sub-display area, which are arranged sequentially from the edge of the display area toward the center. The first data driving circuit is used to control the first sub-display area to display an image according to the first gamma voltage sequence, the second data driving circuit is used to control the second sub-display area to display an image according to the second gamma voltage sequence, and the third data driving circuit is used to control the third sub-display area to display an image according to the third gamma voltage sequence.

[0013] Optionally, the timing control circuit adjusts the first gamma voltage to obtain a first gamma voltage subdivision sequence and a second gamma voltage subdivision sequence. The first sub-display area includes a first partition and a second partition. The data driving circuit controls the first partition to display an image according to the first gamma voltage subdivision sequence and controls the second partition to display an image according to the second gamma voltage subdivision sequence. The first partition is located at the edge of the display area, and the second partition is adjacent to the second sub-display area.

[0014] Optionally, both the first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence include a fifth gamma voltage, which is located between the first gamma voltage and the second gamma voltage. In the first gamma voltage subdivision sequence, the difference between the fifth gamma voltage and the first gamma voltage is a first voltage difference. In the second gamma voltage subdivision sequence, the difference between the fifth gamma voltage and the first gamma voltage is a second voltage difference. The first voltage difference is less than the second voltage difference.

[0015] Compared to the problems of existing technologies, the embodiments of this application adjust the initial gamma voltage sequence to generate at least two sets of gamma voltage sequences and provide them to different data driving circuits. This allows the data driving circuits to control the pixel units in different display areas to display different brightness levels at the same grayscale, thereby effectively solving the problem of brightness reduction caused by insufficient charging of pixel units. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display device provided in the first embodiment of this application; Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel; Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the array substrate; Figure 4 for Figure 3 Logic diagram for generating medium gamma voltage; Figure 5 for Figure 3 Schematic diagram of voltage adjustment for medium gamma circuit and data drive circuit; Figure 6 An embodiment of this application is provided as follows: Figure 4 A schematic diagram of the circuit architecture of a medium gamma circuit; Figure 7 A voltage diagram for each gamma voltage sequence; Figure 8 for Figure 6 Equivalent circuit diagram of the medium voltage regulation module; Figure 9 This is the timing diagram for the control signal output of the timing control circuit; Figure 10 for Figure 4 Circuit block diagram of the data driving circuit; Figure 11 for Figure 10 Equivalent circuit diagram of the input control module; Figure 12 A schematic diagram of the gamma voltage subdivision sequence; Figure 13 A schematic diagram of the working process of the gamma voltage subdivision sequence.

[0018] Explanation of reference numerals in the attached drawings: Display device-100, Display panel-10, Power module-20, Support frame-30, Display area-10a, Timing control circuit-11, Data driving circuit-12, Scan driving circuit-13, Gamma circuit-14, Pixel unit-P, Backlight module-17, Array substrate-10c, Liquid crystal layer-10e, Color filter substrate-10d, First direction-F1, Second direction-F2, Data line-S, Scan line-G, Data driving circuit-12, First data driving circuit Circuit-12a, Second Data Driver Circuit-12b, Third Data Driver Circuit-12c, Fourth Data Driver Circuit-12d, Fifth Data Driver Circuit-12e, Sixth Data Driver Circuit-12f, Input Control Module-121, Logic Processing Module-122, Shift Register Module-123, Data Latch Module-124, Analog-to-Digital Conversion Module-125, Output Buffer Module-126, First Sub-Display Area-a, Second Sub-Display Area-b, Third Sub-Display Area-c, Fourth Sub-Display Area-d Fifth sub-display area - e, Sixth sub-display area - f, Neutral line - L, Power supply voltage - AVDD, First gamma voltage - GM1, Second gamma voltage - GM7, Third gamma voltage - GM8, Fourth gamma voltage - GM14, Fifth gamma voltage - GM5, Voltage generation module - 141, Voltage adjustment module - 142, Output control module - 143, First adjustment unit - 142a, Second adjustment unit - 142b, Third adjustment unit - 142c, Amplifier - OP, First resistor - R 1. Second resistor - R2, Third resistor - R3, Fourth resistor - R4, First switch - Q1, Second switch - Q2, Third switch - Q3, Ground terminal - GND, Fourth switch - Q4, First capacitor - C1, First gamma voltage difference - VM1, Second gamma voltage difference - VM2, Third gamma voltage difference - VM3, First control signal - K1, Second control signal - K2, Third control signal - K3, Data signal - Data, First voltage difference - v1, Second voltage difference - v2. Detailed Implementation

[0019] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0020] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and have no sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "back," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying illustrations. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0022] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0024] Please see Figure 1 , Figure 1This is a schematic diagram of a display device according to the first embodiment of this application. The display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images, and the support frame 30 provides fixation and protection for the display panel 10 and the power module 20.

[0025] In other embodiments of this application, the display device 100 may not require the support frame 30, for example, it may be a portable electronic device, such as a mobile phone or tablet computer.

[0026] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel.

[0027] The display panel 10 includes an array substrate 10c and a color filter substrate 10d, and a liquid crystal layer 10e sandwiched between the array substrate 10c and the color filter substrate 10d. Driving elements are disposed on the array substrate 10c and the color filter substrate 10d to generate corresponding electric fields according to data signals, thereby driving the liquid crystal molecules in the liquid crystal layer 10e to rotate by an angle to emit light of corresponding brightness, so as to perform image display.

[0028] In this embodiment, the display panel 10 can be a liquid crystal display panel or other types of display panels, and this application does not impose any restrictions.

[0029] Taking a liquid crystal display panel as an example, the display panel 10 also includes a backlight module 17 (BM), which provides light for display to the display area 10a of the display panel 10. The display panel 10 emits corresponding light according to the image signal to be displayed to perform image display. The display panel 10 also includes other elements or components, such as a signal processor module and a signal sensing module.

[0030] Please see Figure 3 , Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the array substrate.

[0031] like Figure 3As shown, corresponding to the display area 10a of the display panel 10, the array substrate 10c is provided with multiple data lines S and multiple scan lines G arranged in a grid pattern. The multiple scan lines G extend along a first direction F1 and are arranged sequentially along a second direction F2, while the multiple data lines extend along the second direction F2 and are arranged sequentially along the first direction. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are correspondingly disposed at the intersections of the multiple scan lines G and the multiple data lines S.

[0032] In the non-display area of ​​the display panel 10, a timing control circuit 11, a data driving circuit 12, a scan driving circuit 13, and a gamma circuit 14 are also provided. The timing control circuit 11 receives image signals representing image information from an external signal source, obtains a clock signal CLK for synchronization, a horizontal synchronization signal, and a vertical synchronization signal, and outputs a gate output control signal for the scan driving circuit 13, a source output control signal for the data driving circuit 12, and a data signal representing image information. The scan driving circuit 13 outputs a scan signal to the pixel unit P to control the pixel unit P to receive data signals from the data driving circuit 12 for image display. The gamma circuit 14 provides a reference voltage to the data driving circuit 12, and the data driving circuit 12 outputs data signals of different gray levels according to the reference voltage.

[0033] In this embodiment, the display area 10a includes multiple display areas and multiple data driving circuits 12, wherein each data driving circuit 12 corresponds to a display area, and the data driving circuit 12 is used to output data signals to the pixel unit P in the corresponding display area to control the display area to display images.

[0034] For example, the display area 10a includes six display areas, which can be a first sub-display area a, a second sub-display area b, a third sub-display area c, a fourth sub-display area d, a fifth sub-display area e, and a sixth sub-display area f. The first sub-display area a and the fourth sub-display area d are symmetrical about the center line L. The first sub-display area a and the fourth sub-display area d are respectively located adjacent to the scanning drive circuits 13 on both sides. The second sub-display area b and the fifth sub-display area e are corresponding about the center line L. The second sub-display area b is located adjacent to the first sub-display area a along the first direction F1. The fifth sub-display area e is located adjacent to the fourth sub-display area d along the first direction F1. The third sub-display area c and the sixth sub-display area f are symmetrical about the center line L. The third sub-display area c and the sixth sub-display area f are adjacent to each other. That is, the fifth sub-display area and the sixth sub-display area f are the middle area of ​​the display area 10a.

[0035] Meanwhile, the display panel 10 includes six data driving circuits, namely a first data driving circuit 12a, a second data driving circuit 12b, a third data driving circuit 12c, a fourth data driving circuit 12d, a fifth data driving circuit 12e, and a sixth data driving circuit 12f. The first data driving circuit 12a to the sixth data driving circuit 12f correspond one-to-one with the first sub-display area a to the sixth sub-display area f, and are used to control the first sub-display area a to the sixth sub-display area f to display images respectively.

[0036] Due to the low-pass filtering effect causing scanning signal delay, the scanning signal delay is greater in the middle of display area 10a, namely the third sub-display area c and the sixth sub-display area f. The delay is smaller closer to the scanning drive circuit 13, namely the first sub-display area a and the fourth sub-display area d. Therefore, to avoid the data signal corresponding to the next row of pixel units being mistakenly charged to the previous row of pixel units due to scanning signal delay, the scanning signal is usually pulled down in advance. This can effectively avoid the data signal mischarge of the third sub-display area c and the sixth sub-display area f. However, the delay when the scanning signal is transmitted to the first sub-display area a and the fourth sub-display area f is smaller. Pulling down the scanning signal in advance will result in insufficient charging time in the edge areas, namely the first sub-display area a and the fourth sub-display area d, thus causing poor display effect. Based on this, this application embodiment provides a gamma circuit that can effectively avoid the problem of poor display effect caused by insufficient charging. Please refer to the following: Figure 4 and Figure 5 , Figure 4 for Figure 3 Logic diagram for generating medium gamma voltage. Figure 5 for Figure 3 A schematic diagram of voltage adjustment for the medium gamma circuit and data drive circuit.

[0037] like Figure 4 and Figure 5 As shown, the gamma circuit 14 outputs a first gamma voltage GM1, a second gamma voltage GM7, a third gamma voltage GM8, and a fourth gamma voltage GM14 based on the power supply voltage AVDD. The first gamma voltage GM1 and the fourth gamma voltage GM14 are the positive and negative voltages when the display panel 10 displays pure white, corresponding to grayscale level 255. The second gamma voltage GM7 and the third gamma voltage GM8 are the positive and negative voltages when the display panel displays pure black, corresponding to grayscale level 0. Other grayscale levels, i.e., grayscale levels 1 to 254, are generated by the data driving circuit 12 based on the first gamma voltage GM1 to the fourth gamma voltage GM14. The first gamma voltage GM1 and the fourth gamma voltage GM14 are symmetrical about the center reference voltage GM0, and the second gamma voltage GM7 and the third gamma voltage GM8 are also symmetrical about the center reference voltage GM0, which is a common voltage.

[0038] Specifically, the gamma circuit 14 includes multiple resistors R connected in series to divide the received power supply voltage AVDD into the required gamma voltages, namely the first gamma voltage GM1 to the fourth gamma voltage GM14, through the multiple resistors R. The data driving circuit 12 includes multiple resistors R connected in series to divide the received gamma voltage to generate multiple different grayscale voltages. Among them, the first gamma voltage GM1 and the second gamma voltage GM7 generate positive grayscale voltages from 0 to 255, and the third gamma voltage GM8 and the fourth gamma voltage GM14 generate negative grayscale voltages from 0 to 255, that is, generate n data signals Data1 to Datan.

[0039] Please see Figure 6 , Figure 6 An embodiment of this application is provided as follows: Figure 4 A schematic diagram of the circuit architecture of a medium gamma circuit.

[0040] like Figure 6 As shown, the gamma circuit 14 includes a voltage generation module 141 and a voltage adjustment module 142. The voltage generation module 141 is used to generate an initial gamma voltage sequence, namely the first gamma voltage GM1 to the fourth gamma voltage GM14, based on the power supply voltage, and transmits the initial gamma voltage to the voltage adjustment module 142. The voltage adjustment module 142 is used to adjust the initial gamma voltage sequence according to the control signal output by the timing control circuit 11, and generate at least two sets of gamma voltage sequences. The different gamma voltage sequences are provided to different data driving circuits 12. The gamma voltage sequences are used to control the data driving circuit 12 to output data voltage to the pixel unit P in the display area in conjunction with the data signal. Furthermore, based on the division of the display area 10a, the voltage adjustment module 142 generates different gamma voltage sequences. That is, the number of gamma voltage sequences can be adjusted according to the number of display areas in the display area 10a. For example, three gamma voltage sequences can be generated corresponding to the first sub-display area a, the second sub-display area b, and the third sub-display area c, respectively, which can be the first gamma voltage sequence GS1 (…). Figure 7 ), second gamma voltage sequence GS2 ( Figure 7 ) and the third gamma voltage sequence GS3 ( Figure 7In this circuit, the first gamma voltage sequence GS1 is output to the first data driving circuit 12a to control the first sub-display area a to display an image; the second gamma voltage sequence GS2 is output to the second data driving circuit 12b to control the second sub-display area b to display an image; and the third gamma voltage sequence GS3 is output to the third data driving circuit 12c to control the third sub-display area c to display an image. Similarly, since the fourth sub-display area d, the fifth sub-display area e, and the sixth sub-display area f are symmetrically arranged with the first sub-display area a, the second sub-display area b, and the third sub-display area c, respectively, the first gamma voltage sequence GS1, the second gamma voltage sequence GS2, and the third gamma voltage sequence GS3 can also be provided to the fourth data driving circuit 12d, the fifth data driving circuit 12e, and the sixth data driving circuit 12f, respectively, to control the fourth sub-display area d, the fifth sub-display area e, and the sixth sub-display area f to display images.

[0041] like Figure 7 As shown, Figure 7 This is a voltage diagram for each gamma voltage sequence.

[0042] The differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3, and the fourth gamma voltage GM4 in the first gamma voltage sequence GS1 and the central reference voltage GM0 are all greater than the differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3, and the fourth gamma voltage GM4 and the central reference voltage GM0 in the second gamma voltage sequence GS2. Similarly, the differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3, and the fourth gamma voltage GM4 and the central reference voltage GM0 in the second gamma voltage sequence GS2 are all greater than the differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3, and the fourth gamma voltage GM4 and the central reference voltage GM0 in the third gamma voltage sequence GS3.

[0043] For example, in the first gamma voltage sequence GS1, the voltage difference between the first gamma voltage GM1 and the central reference voltage GM0 is the first gamma voltage difference VM1; in the second gamma voltage sequence GS2, the voltage difference between the first gamma voltage GM1 and the central reference voltage GM0 is the second gamma voltage difference VM2; and in the third gamma voltage sequence GS3, the voltage difference between the first gamma voltage GM1 and the central reference voltage GM0 is the third gamma voltage difference VM3. In this case, the first gamma voltage difference VM1 is greater than the second gamma voltage difference VM2, and the second gamma voltage difference VM2 is greater than the third gamma voltage difference VM3.

[0044] By adjusting the initial gamma voltage, a first gamma voltage sequence GS1 to a third gamma voltage sequence GS3 are obtained. Based on the first gamma voltage sequence GS1 to the third gamma voltage sequence GS3, the first sub-display area a to the third sub-display area c are controlled to display images respectively. Since the first gamma voltage difference VM1, the second gamma voltage difference VM2, and the third gamma voltage difference decrease sequentially, at the same gray level, the brightness of the first sub-display area a is greater than the brightness of the second sub-display area b, and the brightness of the second sub-display area b is greater than the brightness of the third sub-display area c. That is, the brightness of the first sub-display area a to the third sub-display area c decreases sequentially, which effectively compensates for the sequential increase in brightness of the first sub-display area a to the third sub-display area c caused by the early pull-down of the scanning signal, thereby making the brightness of the first sub-display area a to the third sub-display area c consistent.

[0045] In this embodiment, the first sub-display area a to the third sub-display area c are symmetrical to the fourth sub-display area d to the sixth sub-display area f, respectively. Therefore, the first gamma voltage sequence GS1 to the third gamma voltage sequence GS3 can also control the fourth sub-display area d to the sixth sub-display area f to perform the same image display. Of course, the gamma voltage sequence can also be adjusted according to the specific situation of the display panel. For example, when the first sub-display area a to the sixth sub-display area d are controlled by the same scanning drive circuit, the first sub-display area a has the lowest brightness and the sixth sub-display area f has the highest brightness because the scanning signal is pulled down in advance. At this time, the gamma voltage sequence output to the first data drive circuit 12a to the sixth data drive circuit 12f can be adjusted in the same way to make the brightness of the first sub-display area a to the sixth sub-display area d consistent.

[0046] Please refer to the following: Figure 8 and Figure 9 , Figure 8 for Figure 6 Equivalent circuit diagram of the medium voltage regulation module. Figure 9 This is the timing diagram for the control signal output of the timing control circuit.

[0047] like Figure 8 As shown, the voltage adjustment module 142 includes an amplifier OP, a first resistor R1, a second resistor R2, a first adjustment unit 142a, a second adjustment unit 142b, and a third adjustment unit 142c. The first resistor R1 is electrically connected between the inverting input and the output input of the amplifier OP, and the second resistor is electrically connected to the non-inverting input of the amplifier OP. The initial gamma voltage output by the voltage generation module 141 is transmitted to the amplifier OP via the second resistor R2. The first adjustment unit 142a, the second adjustment unit 142b, and the third adjustment unit 142c are connected in parallel between the ground terminal and the inverting input of the amplifier OP, used to adjust the adjustment range of the amplifier OP for the initial gamma voltage.

[0048] The first adjustment unit 142a is used to adjust the initial gamma voltage sequence to the first gamma voltage sequence in conjunction with the amplifier OP; the second adjustment unit 142b is used to adjust the initial gamma voltage sequence to the second gamma voltage sequence in conjunction with the amplifier OP; and the third adjustment unit 142c is used to adjust the initial gamma voltage sequence to the third gamma voltage sequence in conjunction with the amplifier OP.

[0049] Specifically, the first adjustment unit 142a includes a first switch Q1 and a third resistor R3, the second adjustment unit 142b includes a second switch Q2 and a fourth resistor R4, and the third adjustment unit 142c includes a fourth switch Q4. The control terminal of the first switch Q1 is electrically connected to the timing control circuit 11, the first conductive terminal of the first switch Q1 is electrically connected to the ground terminal GND, the second control terminal of the first switch Q1 is electrically connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is electrically connected to the inverting terminal of the amplifier OP.

[0050] The control terminal of the second switch Q2 is electrically connected to the timing control circuit 11, the first conductive terminal of the second switch Q2 is electrically connected to the ground terminal GND, the second control terminal of the second switch Q2 is electrically connected to the first terminal of the fourth resistor R4, and the second terminal of the fourth resistor R4 is electrically connected to the inverting terminal of the amplifier OP.

[0051] The control terminal of the fourth switch Q4 is electrically connected to the timing control circuit 11, the first conductive terminal of the fourth switch Q4 is electrically connected to the ground terminal GND, and the second control terminal of the fourth switch Q4 is electrically connected to the inverting terminal of the amplifier OP. The third resistor R3 is greater than the fourth resistor R4.

[0052] like Figure 9As shown, the gamma voltage output period includes three consecutive time periods: a first time period t1, a second time period t2, and a third time period t3. In the first time period t1, the timing control circuit 11 outputs a first control signal K1 to the first adjustment unit 142a to control the first switch Q1 to turn on. The amplifier OP amplifies the voltage of the initial gamma voltage sequence by a factor of (1 + R1 / R3) to obtain the first gamma voltage sequence, which is then transmitted to the first data drive circuit 12a and the second data drive circuit 12b. In the second time period t2, the timing control circuit 11 outputs a second control signal K2 to the second adjustment unit 142b to control the second switch Q2 to turn on. The amplifier OP amplifies the voltage of the initial gamma voltage sequence by a factor of (1 + R1 / R4) to obtain the second gamma voltage sequence, which is then transmitted to the third data drive circuit 12c and the fourth data drive circuit 12d. The base level of the first gamma voltage sequence is greater than the base level of the second gamma voltage sequence. During the third time period t3, the timing control circuit 11 outputs the third control signal K3 to the third adjustment unit 142c to control the fourth switch Q4 to turn on. The amplifier OP transmits the initial gamma voltage sequence as the third gamma voltage sequence to the fifth data drive circuit 12e and the sixth data drive circuit 12f.

[0053] By using amplifier OP to raise the base level of the initial gamma voltage sequence, the base level of the gamma voltage corresponding to the first sub-display area a to the third sub-display area c decreases sequentially. This allows the first sub-display area a to the third sub-display area c to be compensated for brightness using different gamma voltages, thereby reducing the brightness difference between the first sub-display area a to the third sub-display area c and improving the compensation effect.

[0054] Please refer to the following: Figure 10 and Figure 11 , Figure 10 for Figure 4 The circuit block diagram of the data driving circuit. Figure 11 for Figure 10 The equivalent circuit diagram of the input control module.

[0055] like Figure 10As shown, the data driving circuit 12 includes an input control module 121, a logic processing module 122, a shift register module 123, a data latch module 124, a digital-to-analog converter module 125, and an output buffer module 126. The input control module 121 is electrically connected to the timing control circuit 11, the gamma circuit 14, and the logic processing module 122. The input control module 121 receives initial data signals and control signals from the timing control circuit 11, and receives a gamma voltage sequence from the gamma circuit 14 under the control of the control signals. Then, it transmits the initial data signals and the gamma voltage sequence... The data is input to the logic processing module 122. The logic processing module 122 generates grayscale data signals based on the initial data signal and the gamma voltage sequence and transmits them to the shift register module 123 and the data latch module 124 for storage. The digital-to-analog conversion module 125 performs analog-to-digital conversion on the data signal in the data latch module 124 to obtain a digital data signal and transmits the converted data signal to the output buffer module 126 for storage. At a preset time, the output buffer module 126 outputs the data voltage to the pixel unit P in the corresponding display area to control the pixel unit P to display the image.

[0056] like Figure 11 As shown, the input control module 121 includes a fourth switch Q4 and a first capacitor C1. The control terminal of the fourth switch Q4 is electrically connected to the timing control circuit 11, the first conductive terminal of the fourth switch Q4 is electrically connected to the voltage adjustment module 142 in the gamma circuit 14, and the second conductive terminal of the fourth switch Q4 is electrically connected to the data driving circuit 12. The first capacitor C1 is electrically connected between the ground terminal GND and the second terminal of the fourth switch Q4. The fourth switch Q4 is turned on under the control of the timing control circuit 11 to transmit the corresponding gamma voltage sequence to the first capacitor C1 for storage and continuously transmit it to the data driving circuit 12, so that the gamma voltage sequence received by the data driving circuit 12 controls the pixel unit to perform image display.

[0057] In this system, multiple data driving circuits 12, under the control of the timing control circuit 11, receive different gamma voltage sequences and control the corresponding display areas to display images based on the received gamma voltage sequences. Taking the first data driving circuit 12a, the second data driving circuit 12b, and the third data driving circuit 12c as examples, in the first time period t1, the timing control circuit 11 outputs a first control signal K1 to the first adjustment unit 142a to control the voltage adjustment module 142 to output the first gamma voltage sequence. At the same time, the timing control circuit 11 outputs the first control signal K1 to the input control module 121 in the first data driving circuit 12a to control the first data driving circuit 12 to receive and store the first gamma voltage sequence.

[0058] During the second time period t2, the timing control circuit 11 outputs the second control signal K2 to the second adjustment unit 142b to control the voltage adjustment module 142 to output the second gamma voltage sequence. At the same time, the timing control circuit 11 outputs the second control signal to the input control module 121 in the second data driving circuit 12b to control the second data driving circuit 12b to receive and store the second gamma voltage sequence.

[0059] During the third time period t3, the timing control circuit 11 outputs a third control signal K3 to the third adjustment unit 142c to control the voltage adjustment module 142 to output a third gamma voltage sequence. Simultaneously, the timing control circuit 11 outputs a third control signal to the input control module 121 in the third data drive circuit 12c to control the third data drive circuit 12c to receive and store the third gamma voltage sequence. After the gamma scan cycle ends, the first data drive circuit 12a to the third data drive circuit 12c control the corresponding display area to display an image based on the received gamma voltage sequence. Similarly, the fourth data drive circuit 12d, the fifth data drive circuit 12e, and the sixth data drive circuit 12f receive their corresponding gamma voltage sequences under the control of the timing control circuit 11. The specific adjustment method is the same as described above, and will not be repeated here.

[0060] Please refer to the following: Figure 12 and Figure 13 , Figure 12 This is a schematic diagram of the gamma voltage subdivision sequence. Figure 13 A schematic diagram of the working process of the gamma voltage subdivision sequence.

[0061] like Figure 12 and Figure 13 As shown, when the gamma circuit 14 generates the basic gamma voltage sequence, the timing control circuit 11 can further adjust the basic gamma voltage sequence (GM1, GM7, GM8 and GM14) to generate the gamma voltage subdivision sequence (GM1, GM2, GM3, ..., GM14), wherein the first gamma voltage sequence, the second gamma voltage sequence and the third gamma voltage sequence are all basic gamma voltage sequences.

[0062] The specific steps are as follows: S101, the gamma circuit generates the initial gamma voltage.

[0063] S102, control the first data driving circuit and the fourth data driving circuit to receive the first gamma voltage sequence; S103, control the second data driving circuit and the fifth data driving circuit to receive the second gamma voltage sequence; S104 controls the third data drive circuit and the sixth data drive circuit to receive the third gamma voltage sequence.

[0064] Specifically, the timing control circuit 11 can generate a first gamma voltage subdivision sequence and a second gamma voltage subdivision sequence based on the first gamma voltage sequence, and simultaneously provide the first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence to the first sub-display area a. The first sub-display area a may include a first partition and a second partition. The first gamma voltage subdivision sequence can be provided to the first partition, and the second gamma voltage subdivision sequence can be provided to the second partition. For example, the first and second gamma voltage subdivision sequences include a fifth gamma voltage GM5, which is located between the first gamma voltage GM1 and the second gamma voltage GM7. In the first gamma voltage subdivision sequence, the difference between the first gamma voltage GM1 and the fifth gamma voltage GM5 is a first voltage difference v1, and in the second gamma voltage subdivision sequence, the difference between the first gamma voltage GM1 and the fifth gamma voltage is a second voltage difference v2. The first voltage difference v1 is less than the second voltage difference v2, which makes the voltage of the fifth gamma voltage GM5 closer to the first gamma voltage GM1 in the first gamma voltage subdivision sequence. That is, the voltage of the fifth gamma voltage GM5 is further away from the central reference voltage GM0. This allows the brightness of the first zone to be higher than that of the second zone at the same gray level, resulting in better uniform brightness compensation in the first sub-display area a.

[0065] Similarly, the second sub-display area b can be divided into a third and a fourth partition. The timing control circuit 11 can generate a third and a fourth gamma voltage subdivision sequence based on the second gamma voltage sequence. The third and fourth gamma voltage subdivision sequences can be provided to the third and fourth partitions, respectively. The third sub-display area c can include a fifth and a sixth partition. The timing control circuit 11 generates a fifth and a sixth gamma voltage subdivision sequence based on the third gamma voltage sequence. The fifth and sixth gamma voltage subdivision sequences can be provided to the fifth and sixth partitions, respectively. Similarly, the fourth, fifth, and sixth sub-display areas d, e, and f are symmetrical to the first, second, and third sub-display areas a, b, and c, respectively. Therefore, the fourth, fifth, and sixth sub-display areas d, e, and f can be configured with the same partitioning and controlled by the same gamma voltage for display.

[0066] For example, display area 10a includes 2160 columns of pixels, first sub-display area a includes columns 1 to 360 of pixels, first partition includes columns 1 to 180 of pixels, second partition includes columns 181 to 360 of pixels, a first gamma voltage subdivision sequence is provided to the first partition (columns 1 to 180), and a second gamma voltage subdivision sequence is provided to the second partition (columns 181 to 360). Fourth sub-display area d includes columns 1801 to 2160, a first gamma voltage subdivision sequence is provided up to columns 1981 to 2160, and a second gamma voltage subdivision sequence is provided up to columns 1801 to 1980. The second sub-display area b includes columns 361 to 720 of pixels. The third sub-display area may include columns 361 to 540, and the fourth sub-display area may include columns 541 to 720 of pixels. A third gamma voltage subdivision sequence may be provided to columns 361 to 540, and a fourth gamma voltage subdivision sequence may be provided to columns 541 to 720. Similarly, the fifth sub-display area e is symmetrical to the second sub-display area b; therefore, the third and fourth gamma voltage subdivision sequences may also be provided to the third sub-display area d. The third sub-display area c may include columns 721 to 1080 of pixels. The fifth sub-display area may include columns 721 to 900, and the sixth sub-display area may include columns 901 to 1080. A fifth gamma voltage subdivision sequence may be provided to columns 721 to 900, and a sixth gamma voltage subdivision sequence may be provided to columns 901 to 1080. Similarly, the sixth sub-display area f is symmetrical to the third sub-display area c, so the fifth gamma voltage subdivision sequence and the sixth gamma voltage subdivision sequence can also be provided to the sixth sub-display area f.

[0067] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A gamma circuit, characterized in that, The system includes a voltage generation module and a voltage adjustment module. The voltage generation module generates an initial gamma voltage sequence based on the power supply voltage and transmits it to the voltage adjustment module. The voltage adjustment module adjusts the voltage of the initial gamma voltage sequence based on a control signal and generates at least two sets of gamma voltage sequences. The different gamma voltage sequences are then transmitted to different data driving circuits. The control signal is received from a timing control circuit, and the gamma voltage sequences are used to control the data driving circuit to output data voltages to the pixel units within the display area in conjunction with the data signal. The voltage adjustment module includes an amplifier, a first resistor (R1), a second resistor (R2), a first adjustment unit, a second adjustment unit, and a third adjustment unit. The first resistor is electrically connected between the inverting input and the output input of the amplifier. The second resistor is electrically connected between the non-inverting input of the amplifier and the voltage generation module. The first adjustment unit, the second adjustment unit, and the third adjustment unit are connected in parallel between the ground terminal and the inverting input of the amplifier. The first adjustment unit is used to work with the amplifier to adjust the initial gamma voltage to a first gamma voltage sequence. The second adjustment unit is used to work with the amplifier to adjust the initial gamma voltage to a second gamma voltage sequence. The third adjustment unit is used to work with the amplifier to adjust the initial gamma voltage to a third gamma voltage sequence. The first adjustment unit includes a first switching transistor and a third resistor (R3). The second adjustment unit includes a second switching transistor and a fourth resistor (R4). The third adjustment unit includes a third switching transistor. The output period of the gamma voltage includes three consecutive periods: a first period, a second period, and a third period. In the first period, a first control signal output from the timing control circuit to the first adjustment unit controls the first switch to turn on. The amplifier amplifies the initial gamma voltage sequence by a factor of (1 + R1 / R3) to obtain a first gamma voltage sequence, which is then transmitted to the first and fourth data drive circuits. In the second period, a second control signal output from the timing control circuit to the second adjustment unit controls the second switch to turn on. The amplifier amplifies the initial gamma voltage sequence by a factor of (1 + R1 / R4) to obtain a second gamma voltage sequence, which is then transmitted to the second and fifth data drive circuits. The base level of the first gamma voltage sequence is greater than the base level of the second gamma voltage sequence. In the third period, a third control signal output from the timing control circuit to the third adjustment unit controls the third switch to turn on. The amplifier transmits the initial gamma voltage sequence as the third gamma voltage sequence to the third data drive circuit and... A sixth data driving circuit is provided, wherein the base level of the second gamma voltage sequence is greater than the base level of the third gamma voltage sequence. The first to sixth data driving circuits correspond one-to-one with the first, second, third, fourth, fifth, and sixth sub-display areas arranged along a first direction within the display area, respectively, and are used to control the first to sixth sub-display areas to display images. Within the display area, the first and fourth sub-display areas are symmetrical about a center line. The first and fourth sub-display areas are respectively located adjacent to the scanning driving circuits on both sides of the display panel. The second and fifth sub-display areas correspond about the center line. The second sub-display area is located adjacent to the first sub-display area along the first direction, and the fifth sub-display area is located adjacent to the fourth sub-display area along the first direction. The third and sixth sub-display areas are symmetrical about a center line and are adjacent to each other.

2. The gamma circuit as described in claim 1, characterized in that, The first gamma voltage sequence, the second gamma voltage sequence, and the third gamma voltage sequence each include a first gamma voltage, a second gamma voltage, a third gamma voltage, and a fourth gamma voltage. The first gamma voltage and the fourth gamma voltage are symmetrical about the central reference voltage, and the second gamma voltage and the third gamma voltage are also symmetrical about the central reference voltage. The first gamma voltage and the second gamma voltage are used to generate a positive data signal, and the third gamma voltage and the fourth gamma voltage are used to generate a negative data signal. The difference between the first gamma voltage and the central reference voltage is greater than the difference between the second gamma voltage and the central reference voltage. In the first gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is the first gamma voltage difference; in the second gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is the second gamma voltage difference; and in the third gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is the third gamma voltage difference. The first gamma voltage difference is greater than the second gamma voltage difference, and the second gamma voltage difference is greater than the third gamma voltage difference.

3. The gamma circuit as described in claim 1, characterized in that, The control terminal of the first switching transistor is electrically connected to the timing control circuit, the first conductive terminal of the first switching transistor is electrically connected to the ground terminal, the second conductive terminal of the first switching transistor is electrically connected to the first terminal of the third resistor, and the second terminal of the third resistor is electrically connected to the inverting terminal of the amplifier. The control terminal of the second switching transistor is electrically connected to the timing control circuit, the first conductive terminal of the second switching transistor is electrically connected to the ground terminal, the second conductive terminal of the second switching transistor is electrically connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is connected to the inverting terminal of the amplifier. The control terminal of the third switch is electrically connected to the timing control circuit, the first conductive terminal of the third switch is electrically connected to the ground terminal, and the second conductive terminal of the third switch is electrically connected to the inverting terminal of the amplifier. The resistance value of the third resistor is greater than the resistance value of the fourth resistor.

4. A data driving circuit, characterized in that, The data driving circuit is used to receive an initial data signal and a control signal from the timing control circuit and a gamma voltage sequence from the gamma circuit according to any one of claims 1-3, and output a corresponding data voltage to the pixel unit in the display area. The data driving circuit includes an input control module and a logic processing module. The input control module is used to receive the initial data signal and the control signal, and receive the gamma voltage sequence under the control of the control signal, and transmit the initial data signal and the gamma voltage sequence to the logic processing module. The logic processing module generates a grayscale data signal based on the initial data signal and the gamma voltage sequence, and the grayscale data signal is used to form the data voltage.

5. The data driving circuit as described in claim 4, characterized in that, The input control module includes a fourth switch and a first capacitor. The control terminal of the fourth switch is electrically connected to the timing control circuit, the first conductive terminal of the fourth switch is electrically connected to the gamma circuit, the second conductive terminal of the fourth switch is electrically connected to the logic processing module, and the first capacitor is electrically connected between the ground terminal and the second conductive terminal of the fourth switch. The fourth switch is turned on according to the control signal output by the timing control circuit, so as to transmit the gamma voltage sequence output by the gamma circuit to the logic processing module.

6. A display panel, characterized in that, The non-display area of ​​the display panel includes a timing control circuit, a gamma circuit as described in any one of claims 1-3, and a plurality of data driving circuits as described in any one of claims 4-5. The timing control circuit controls the data driving circuit to output data signals including a continuous first time period, a second time period, and a third time period. The plurality of data driving circuits include a first data driving circuit, a second data driving circuit, a third data driving circuit, a fourth data driving circuit, a fifth data driving circuit, and a sixth data driving circuit. During the first time period, the timing control circuit outputs a first control signal to the gamma circuit and the data driving circuit. The gamma circuit outputs a first gamma voltage sequence according to the first control signal, and the first data driving circuit and the fourth data driving circuit receive the first gamma voltage sequence according to the first control signal. During the second time period, the timing control circuit outputs a second control signal to the gamma circuit and the data driving circuit. The gamma circuit outputs a second gamma voltage sequence according to the second control signal, and the second data driving circuit and the fifth data driving circuit receive the second gamma voltage sequence according to the second control signal. During the third time period, the timing control circuit outputs a third control signal to the gamma circuit and the data driving circuit. The gamma circuit outputs a third gamma voltage sequence according to the third control signal, and the third data driving circuit and the sixth data driving circuit receive the third gamma voltage sequence according to the third control signal.

7. The display panel as described in claim 6, characterized in that, The display panel includes a first sub-display area, a second sub-display area, and a third sub-display area, which are arranged sequentially from the edge of the display area toward the center. The first data driving circuit is used to control the first sub-display area to display an image according to the first gamma voltage sequence, the second data driving circuit is used to control the second sub-display area to display an image according to the second gamma voltage sequence, and the third data driving circuit is used to control the third sub-display area to display an image according to the third gamma voltage sequence.

8. The display panel as described in claim 7, characterized in that, The timing control circuit adjusts the first gamma voltage to obtain a first gamma voltage subdivision sequence and a second gamma voltage subdivision sequence. The first sub-display area includes a first partition and a second partition. The data driving circuit controls the first partition to display an image according to the first gamma voltage subdivision sequence and controls the second partition to display an image according to the second gamma voltage subdivision sequence. The first partition is located at the edge of the display area, and the second partition is adjacent to the second sub-display area.

9. The display panel as described in claim 8, characterized in that, Both the first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence include a fifth gamma voltage, which is located between the first gamma voltage and the second gamma voltage. In the first gamma voltage subdivision sequence, the difference between the fifth gamma voltage and the first gamma voltage is a first voltage difference. In the second gamma voltage subdivision sequence, the difference between the fifth gamma voltage and the first gamma voltage is a second voltage difference. The first voltage difference is less than the second voltage difference.

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