A low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture

Abstract

This invention belongs to the field of semiconductor device packaging technology and discloses a low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture, including: an upper substrate, a lower substrate, a decoupling capacitor, a ceramic hermetically sealed frame, bonding wires / metal foil, a power semiconductor chip, a pad, and a high-temperature potting material. This invention utilizes the structural feature of a double-sided cooling module with two substrates, employing a specially designed ceramic hermetically sealed frame to construct a small hermetically sealed system between the upper and lower substrates. This packaging architecture can provide hermetically sealed protection for the core components of the module without increasing the length of the internal and external heat dissipation paths and the commutation loop path of the double-sided cooling power module, and without affecting the module's low thermal resistance and low parasitic inductance performance advantages.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device packaging technology, and particularly relates to a packaging architecture and method for low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor devices. Background Technology

[0002] Wide bandgap power devices, due to their advantages such as high critical electric field, high thermal conductivity, low on-resistance, high switching speed, and low switching losses, have broad application prospects in harsh environments such as aerospace, electric vehicles, and energy exploration. To fully utilize the high-temperature and high-pressure operating capabilities of wide bandgap devices, wide bandgap power module packaging technology is developing towards high-temperature resistance, high-pressure resistance, and high reliability. Hermetic seals, providing sufficient mechanical protection and high-temperature water, oxygen, and contamination resistance at high temperatures, play a crucial role in high-temperature power module packaging.

[0003] Compared to traditional single-sided cooled bonded wire power modules, double-sided cooled SiC power semiconductor modules add an extra heat dissipation path and employ a three-dimensional commutation structure, significantly reducing thermal resistance and parasitic inductance, thereby significantly improving the power density of power semiconductor devices. However, traditional hermetically sealed architectures use thick hermetically sealed cavities to encapsulate the sealed devices, using terminals passing through the cavity walls to achieve electrical connections between the inside and outside of the cavity. This significantly increases the length of the heat dissipation path and the commutation loop path. Furthermore, the terminals passing through the hermetically sealed cavity need to fit well with the sealed device to achieve electrical connections. Therefore, using a traditional hermetically sealed architecture to seal double-sided cooled power semiconductor modules will significantly increase the module's thermal resistance and parasitic inductance, while also increasing the difficulty of the fabrication process.

[0004] To address the aforementioned issues, it is particularly important to design an easily implementable hermetically sealed packaging architecture that does not affect the low inductance and low thermal resistance performance of double-sided cooled high-temperature SiC power semiconductor modules.

[0005] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0006] Traditional hermetic packaging architectures use a hermetic cavity to enclose the sealed device, with terminals used to achieve electrical connections between the inside and outside of the hermetic cavity. This significantly increases the length of the heat dissipation path and the commutation loop path. In addition, the terminals passing through the hermetic cavity need to fit well with the sealed device to achieve electrical connection. Therefore, using a traditional hermetic architecture to seal a double-sided cooled power semiconductor module will significantly increase the module's thermal resistance and parasitic inductance, while also increasing the difficulty of the fabrication process. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention provides a packaging architecture for low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor devices.

[0008] This invention is implemented as follows: a low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture includes:

[0009] Upper substrate, lower substrate, decoupling capacitor, ceramic hermetic frame, bonding wire / metal foil, power semiconductor chip, padding, high-temperature potting material;

[0010] Connect the DC+ power terminal and the drain of the upper bridge arm chipset to the DC+ metallization region of the lower substrate, and connect the DC- power terminal to the DC- metallization region of the lower substrate; connect the Kelvin source, gate, and Kelvin drain signal terminals of the upper bridge arm to the Kelvin source metallization region, gate metallization region, and DC+ metallization region of the lower substrate, respectively; connect the pad to the power source and AC metallization region of the upper bridge arm power chipset, and use bonding wires or metal foil to connect the Kelvin source and gate of the chip to the metallized conductive pads on the ceramic hermetically sealed frame boss of the upper bridge arm.

[0011] The bottom sealing ring and two conductive pads of the upper bridge arm's ceramic hermetic frame are connected to the DC+ metallization region, the upper bridge arm's Kelvin source metallization region, and the gate metallization region, respectively. The top sealing ring of the upper bridge arm's ceramic hermetic frame is connected to the AC metallization region. The DC+ metallization region, the AC metallization region, and the upper bridge arm's ceramic hermetic frame together form the upper bridge arm's hermetic cavity, achieving hermetic sealing of the core components of the upper bridge arm.

[0012] Symmetrically, the AC power terminal and the drain of the lower bridge arm chip group are connected to the AC metallization area of ​​the upper substrate. The Kelvin source, gate, and Kelvin drain signal terminals of the lower bridge arm are connected to the lower bridge arm Kelvin source metallization area, the gate metallization area, and the AC metallization area of ​​the upper substrate, respectively. The pad is connected to the power source and DC metallization area of ​​the lower bridge arm power chip group. The Kelvin source and gate of the chip are connected to the metallization conductive pads on the ceramic hermetically sealed frame boss of the lower bridge arm using bonding wires or metal foil.

[0013] The bottom sealing ring of the ceramic frame of the lower bridge arm and the two conductive pads are connected to the AC metallization region, the Kelvin source metallization region, and the gate metallization region of the lower bridge arm, respectively. The top sealing ring of the ceramic hermetic frame of the lower bridge arm is connected to the DC-metallization region. The AC metallization region, the DC-metallization region, and the ceramic hermetic frame of the lower bridge arm constitute the hermetic cavity of the lower bridge arm, realizing the hermetic sealing of the core component of the lower bridge arm.

[0014] Furthermore, the substrate: the process includes, but is not limited to, copper / silver plating DBC, AMB, DPC;

[0015] Metallization coating on substrate: including but not limited to silver plating, nickel-silver plating, nickel plating, nickel-gold plating, and gold plating.

[0016] Furthermore, the decoupling capacitor includes, but is not limited to, ceramic capacitors and thin-film capacitors.

[0017] Furthermore, the ceramic airtight frame is manufactured using processes including but not limited to high-temperature co-firing and low-temperature co-firing; the metallized area plating includes but is not limited to silver plating, nickel-silver plating, nickel plating, nickel-gold plating, and gold plating; and the ceramic substrate material includes but is not limited to alumina, aluminum nitride, and silicon nitride.

[0018] Furthermore, the power semiconductor chip includes, but is not limited to, Si-based, SiC-based, and GaN-based power devices;

[0019] Interconnection processes between chips and substrates, terminals and substrates, and ceramic frames and substrates include, but are not limited to: silver / copper sintering, welding, transient liquid phase bonding, and ultrasonic bonding.

[0020] Furthermore, the pad material includes, but is not limited to, copper pad, copper diamond pad, silver diamond pad, molybdenum pad, and copper-molybdenum-copper pad; its surface metallization includes, but is not limited to, silver plating, nickel-silver plating, nickel plating, nickel-gold plating, and gold plating.

[0021] Furthermore, the high-temperature potting materials include, but are not limited to: polyimide, pyrene, alumina film, modified glass, and special ceramics.

[0022] This invention also provides a packaging method for a low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture, comprising the following steps:

[0023] (1) Provide an upper substrate and a lower substrate, wherein the substrate is prepared by AMB process, DBC process or DPC process, the substrate material is silicon nitride, aluminum nitride or aluminum oxide, and a metallization region is formed on the substrate surface.

[0024] (2) The power source of the power semiconductor chip is connected to the metallized area of ​​the substrate through a pad. The pad is made of copper, copper diamond, silver diamond, molybdenum or copper molybdenum copper and is metal plated on the surface.

[0025] (3) Connect the Kelvin source and gate of the power semiconductor chip to the metallized pads on the ceramic hermetic frame boss through bonding wires or metal foil.

[0026] (4) Prepare a ceramic airtight frame by high temperature co-firing, low temperature co-firing or DPC process, and connect the metal sealing ring of the ceramic airtight frame to the metallization area corresponding to the upper substrate or the lower substrate.

[0027] (5) Decoupling capacitors are set between the positive and negative busbars, and high-temperature potting material is covered on the surface of the chip, interconnect area and internal structure to complete the encapsulation.

[0028] Furthermore, the connection between the chip and the substrate, and between the terminal and the ceramic hermetic frame, is achieved using silver sintering, copper sintering, welding, transient liquid phase bonding, or ultrasonic bonding processes; the high-temperature potting material is polyimide, pyrene, alumina film, modified glass, or special ceramics.

[0029] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0030] This invention utilizes the structural feature of a double-sided cooling module with two substrates, upper and lower. By employing a specially designed ceramic hermetic frame, a small hermetic system is constructed between the upper and lower substrates. This packaging architecture provides hermetic sealing protection for the core components of the module without increasing the length of the internal and external heat dissipation paths or the commutation loop path of the double-sided cooling power module, and without affecting the module's advantages of low thermal resistance and low parasitic inductance.

[0031] The technical solution of this invention fills the technical gap in the packaging architecture of high-performance ceramic hermetically sealed double-sided cooling high-temperature power semiconductor devices both domestically and internationally.

[0032] The technical solution of this invention solves the technical problem that traditional hermetic architecture is difficult to apply to the packaging of double-sided cooled high-temperature power semiconductor devices. It achieves hermetic packaging while ensuring low thermal resistance and low parasitic inductance of the module, thereby enabling the hermetic protection capability of the double-sided cooled module.

[0033] This invention relates to a ceramic hermetically sealed, double-sided cooled high-temperature SiC power semiconductor device packaging architecture. The main components include upper and lower ceramic substrates, a ceramic hermetically sealed frame, a SiC power chip, metal interconnect structures (pads, bonding wires, or metal foils), decoupling capacitors, and high-temperature corrosion-resistant potting material. The substrates are manufactured using AMB, DBC, or DPC processes. The hermetically sealed frame is fabricated using high-temperature co-firing (HTCC), low-temperature co-firing (LTCC), or direct copper plating (DPC) technology. The chip is interconnected with the substrate and frame using silver sintering, copper sintering, welding, or transient liquid phase bonding processes to achieve low thermal resistance and high reliability. The overall structure forms a high-temperature hermetically sealed packaging module designed for extreme environments above 250°C.

[0034] This invention addresses the problems of solder joint failure, insufficient hermeticity, and accelerated interface thermal fatigue in traditional double-sided cooled SiC power devices under high-temperature environments (>200℃). It proposes a novel packaging method that utilizes a synergistic design of a ceramic hermetic frame, a metal seal, and a high-temperature potting material. In existing technologies, metal wire bonding and conventional silicone potting materials are prone to migration, cracking, and seal failure at high temperatures, making it difficult to meet the high-temperature hermeticity and long-term reliability requirements of aerospace, electric vehicle high-voltage platforms, and other applications. Therefore, this invention focuses on solving the problems of stress release at the metal / ceramic heterojunction interface at high temperatures, long-term hermeticity maintenance, and insulation stability during high-frequency, high-voltage operation.

[0035] By introducing aluminum nitride (AlN) or silicon nitride (Si3N4) ceramic materials with excellent thermomechanical matching properties, and using sol-gel modified polyimide, pyrene, or special ceramic films as high-temperature insulating potting media, this invention significantly improves the overall thermal cycling resistance and breakdown voltage rating of the device. The ceramic hermetic frame has independent boss metallized pads on top, which, by independently leading out the Kelvin source and gate, reduces the dynamic on-resistance degradation problem and also reduces package parasitic inductance, thus improving the reliability and efficiency of high-frequency switching devices.

[0036] The ceramic hermetic double-sided cooling packaging architecture of the present invention achieves a systematic improvement in key indicators such as device temperature resistance, power density, hermetic life and high voltage insulation level compared with traditional single-sided cooling or non-hermetic packaging technology. Attached Figure Description

[0037] Figure 1 This is a structural diagram of the packaging architecture of a low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device provided in an embodiment of the present invention.

[0038] Figure 2 This is a structural diagram of a specially designed ceramic airtight frame provided in an embodiment of the present invention.

[0039] Figure 3(a) is a structural diagram of the ceramic airtight frame of the upper bridge arm in an embodiment of the present invention.

[0040] Figure 3(b) is a structural diagram of the ceramic airtight frame of the bridge arm in an embodiment of the present invention.

[0041] Figure 4 This is a top view of the packaging architecture provided in an embodiment of the present invention.

[0042] Figure 5 This is a front view of the packaging architecture provided in an embodiment of the present invention.

[0043] Figure 6 This is a sample image of a specially designed ceramic airtight frame provided in an embodiment of the present invention.

[0044] Figure 7 This is a diagram of the internal structure of a sample prepared using the packaging architecture provided in this embodiment of the invention.

[0045] Figure 8 This is an appearance diagram of a sample prepared using the packaging architecture provided in an embodiment of the present invention.

[0046] Figure 9 This is a model diagram of a double-sided cooling module that is sealed with a traditional airtight structure, according to an embodiment of the present invention.

[0047] Figure 10This is a comparison diagram of the parasitic inductance simulation extraction of the embodiment of the present invention and the traditional airtight double-sided cooling module.

[0048] Figure 11 This is a thermal simulation comparison diagram of the embodiment of the present invention and the traditional airtight double-sided cooling module.

[0049] In the diagram: 1. Upper substrate; 2. Lower substrate; 3. Decoupling capacitor; 4. Ceramic hermetic frame; 5. Bonding wire / metal foil; 6. Power semiconductor chip; 7. Pad; 8. High-temperature potting material; 101. AC metallization region; 102. Kelvin source metallization region of the lower bridge arm; 103. Gate metallization region of the lower bridge arm; 111. AC terminal; 112. Kelvin drain terminal of the lower bridge arm; 113. Gate terminal of the lower bridge arm; 114. Kelvin source terminal of the lower bridge arm; 201. DC+ metallization region; 202. DC- metallization region; 203. Gate metallization region of the upper bridge arm; 204. Kelvin source terminal of the upper bridge arm. Metallized region; 211, DC+ terminal; 212, DC- terminal; 213, upper bridge arm Kelvin drain terminal; 214, upper bridge arm gate terminal; 215, upper bridge arm Kelvin source terminal; 401, ceramic sidewall substrate; 402, ceramic boss; 403, cavity; 411, metallized conductive pad; 412, metallized conductive pad; 413, metallized conductive pad; 421, metallized conductive pad; 422, metallized conductive pad; 423, metallized conductive pad; 431, upper metal sealing ring; 432, lower metal sealing ring; 441, metal conductive pad; 442, metal conductive pad. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0051] The purpose of this invention is to overcome the shortcomings of traditional hermetic architectures that are not suitable for double-sided cooling modules, and to provide a ceramic hermetic double-sided cooling high-temperature SiC power module packaging architecture. This architecture has the characteristics of hermetic core components, low thermal resistance, low inductance, high temperature resistance, and no significant increase in process difficulty.

[0052] like Figure 1 As shown, the low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture provided by this embodiment of the invention includes: an upper substrate 1, a lower substrate 2, a decoupling capacitor 3, a ceramic hermetically sealed frame 4, bonding wires / metal foil 5, a power semiconductor chip 6, a pad 7, and a high-temperature potting material 8.

[0053] The specially designed ceramic airtight frame 4 of this invention comprises a ceramic sidewall substrate 401, a ceramic boss 402, a cavity 403, metallized conductive pads 411, 412, 413, 421, 422, 423, an upper metal sealing ring 431, a lower metal sealing ring 432, and metal conductive pads 441 and 442. The metallized conductive pads 411, 413, 421, and 423 are electrically interconnected with the conductive pad 442 through vertically downward-facing (fully filled) metal vias inside the ceramic boss 402. Similarly, the metallized conductive pads 412 and 422 are electrically interconnected with the conductive pad 441 through vertically downward-facing (fully filled) metal vias inside the ceramic boss 402.

[0054] The packaging architecture of the low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device consists of two sets of packaging structures arranged in a mirror image. Each of the upper and lower bridge arms has a ceramic hermetic frame, and its structure and numbering are shown in Figure 3(a) and Figure 3(b).

[0055] The top of the lower substrate 2 is provided with a DC+ metallization region 201, a DC- metallization region 202, an upper bridge arm Kelvin source metallization region 204, and an upper bridge arm gate metallization region 203. Correspondingly, the DC+ power terminal 211 and the upper bridge arm Kelvin drain signal terminal 213 are connected to the DC+ metallization region 201, the upper bridge arm Kelvin source signal terminal 215 is connected to the upper bridge arm Kelvin source metallization region 204, the upper bridge arm gate signal terminal 214 is connected to the upper bridge arm gate metallization region 203, the DC- power terminal 212 is connected to the DC- metallization region, and the pads on both sides of the decoupling capacitor 3 are connected to the DC+ and DC- metallization regions, respectively.

[0056] The drain of the upper bridge arm power semiconductor chip is connected to the DC+ metallization region 201 of the lower substrate, the power source is connected to the AC metallization region 101 through a pad, the gate is connected to the metallization pads 412.a and 422.a on the ceramic hermetic frame boss of the upper bridge arm, and the Kelvin source is connected to the metallization pads 411.a, 413.a, 421.a and 423.a on the ceramic hermetic frame boss of the upper bridge arm, respectively.

[0057] The upper metal sealing ring 431.a of the upper bridge arm ceramic hermetic frame is connected to the AC metallization region 101, and the lower metal sealing ring 432.a is connected to the DC+ metallization region 201. The AC metallization region, the DC+ metallization region, and the ceramic hermetic frame together form the upper bridge arm hermetic cavity, achieving hermetic sealing of the core component of the upper bridge arm. The conductive pad 441.a below the ceramic boss is connected to the upper bridge arm gate metallization region 203, and the conductive pad 442.a below the ceramic boss is connected to the upper bridge arm Kelvin source metallization region 204, providing drive signals for the chip.

[0058] Symmetrically, the bottom of the upper substrate 1 is provided with an AC metallization region 101, a Kelvin source metallization region 102 of the lower bridge arm, and a gate metallization region 103 of the lower bridge arm. The AC power terminal 111 and the lower bridge arm Kelvin drain signal terminal 112 are connected to the AC metallization region 101, the lower bridge arm Kelvin source signal terminal 114 is connected to the lower bridge arm Kelvin source metallization region 102, and the lower bridge arm gate signal terminal 113 is connected to the lower bridge arm gate metallization region 103.

[0059] The drain of the lower bridge arm power semiconductor chip is connected to the AC metallization region 101 of the upper substrate, the power source is connected to the DC metallization region 202 of the lower substrate through a pad, the gate is connected to the metallization pads 412.b and 422.b on the ceramic hermetically sealed frame boss of the lower bridge arm, and the Kelvin source is connected to the metallization pads 411.b, 413.b, 421.b and 423.b on the boss.

[0060] The upper metal sealing ring 431.b of the lower bridge arm ceramic hermetic frame is connected to the DC-metallization region 202, and the lower metal sealing ring 432.b is connected to the AC-metallization region 101. The DC-metallization region, the AC-metallization region, and the ceramic hermetic frame together form the lower bridge arm hermetic cavity, achieving hermetic sealing of the core component of the lower bridge arm. The conductive pad 441.b below the ceramic boss is connected to the lower bridge arm gate metallization region 103, and the conductive pad 442.b below the ceramic boss is connected to the lower bridge arm Kelvin source metallization region 102.

[0061] The device is internally reinforced with a high-temperature potting material 8, which covers all surfaces of the module and has good heat resistance and electrical insulation.

[0062] It should be noted that, in order to demonstrate the general applicability of the hermetically sealed double-sided cooling high-temperature SiC power semiconductor module packaging architecture described in this invention, apart from the specially designed ceramic hermetically sealed frame 4, the rest of the packaging structure is similar to that of conventional double-sided cooling SiC power semiconductor module packaging.

[0063] It should be noted that the above materials have a wide range of options, some of which are listed below:

[0064] Substrate: Processes include, but are not limited to, copper / silver plating DBC, AMB, DPC, etc.

[0065] Metallization coating on substrate: including but not limited to silver plating, nickel-silver plating, nickel plating, nickel-gold plating, and gold plating.

[0066] Decoupling capacitors: including but not limited to ceramic capacitors, film capacitors, etc.

[0067] Ceramic airtight frame: The process includes, but is not limited to, high-temperature co-firing process and low-temperature co-firing process; the metallized area coating includes, but is not limited to, silver plating, nickel silver plating, nickel plating, nickel gold plating, gold plating, etc.; the ceramic substrate material includes, but is not limited to, alumina, aluminum nitride, silicon nitride, etc.

[0068] Power semiconductor chips include, but are not limited to, Si-based, SiC-based, and GaN-based power devices.

[0069] Interconnection processes between chips and substrates, terminals and substrates, and ceramic frames and substrates include, but are not limited to: silver / copper sintering, welding, transient liquid phase bonding, and ultrasonic bonding.

[0070] The pad materials include, but are not limited to, copper pads, copper diamond pads, silver diamond pads, molybdenum pads, copper-molybdenum-copper pads, etc.; their surface metallization includes, but is not limited to, silver plating, nickel-silver plating, nickel plating, nickel-gold plating, gold plating, etc.

[0071] Encapsulation materials include, but are not limited to: polyimide, pyrene, alumina film, modified glass, and special ceramics.

[0072] It should be noted that the specific connection process and component metallization plating can be determined according to the application scenario of the module. The bonding wire / metal foil material and wire diameter are determined by the metallization material and size of the chip pads. The ceramic hermetic frame material, shape, thickness, number of conductive pads, electrical connection logic, and specific manufacturing process used are jointly determined by factors such as the number of chipsets, the expected application scenario, manufacturing capabilities, and costs. Of course, the ceramic frame architecture placed inside the module is not limited to the specific ceramic frame described in this invention, and the electrical logic can be modified according to actual needs.

[0073] The core of this invention lies in utilizing a specially designed ceramic airtight frame as the sidewall of the airtight sealing cavity, and the upper and lower substrates of the double-sided cooling module as the upper and lower cover plates of the airtight sealing cavity. This constructs a small airtight system within the double-sided cooling module, providing airtight protection for core power module components such as chips, bonding wires, and spacers. Unlike traditional externally enclosed airtight sealing architectures, the airtight sealing cavity of this invention utilizes the structural characteristics of the double-sided cooling module itself to construct an airtight system within the module. This does not increase the length of the internal and external heat dissipation paths or the commutation loop path of the double-sided cooled SiC power module (i.e., ensuring the advantages of low inductance and low thermal resistance), nor does it significantly increase the difficulty of power module fabrication.

[0074] In addition, external driving signals (small currents) are introduced into the airtight cavity through the internal through-holes of the ceramic airtight frame, while the thick metallized areas of the upper and lower substrates serve as the upper and lower cover plates of the airtight cavity and simultaneously bear the large current of the power stage. This design effectively avoids the problem that the metallized layer of co-fired ceramics is too thin to bear large currents.

[0075] Specific examples:

[0076] In this embodiment, both the upper and lower bridge arms have chipsets consisting of two SiC power chips connected in parallel. It should be noted that the chips in the chipset can be two, three, or even more chips connected in parallel; this can be achieved by adjusting the size of the ceramic frame or by using multiple ceramic frames grouped together for airtightness.

[0077] In this embodiment, each of the upper and lower bridge arms has a ceramic airtight frame, the structure and numbering of which are shown in Figure 3(a) and Figure 3(b).

[0078] The specially designed ceramic airtight frame 4 of this invention comprises a ceramic sidewall substrate 401, a ceramic boss 402, a cavity 403, metallized conductive pads 411, 412, 413, 421, 422, 423, an upper metal sealing ring 431, a lower metal sealing ring 432, and metal conductive pads 441 and 442. The metallized conductive pads 411, 413, 421, and 423 are electrically interconnected with the conductive pad 442 through vertically downward-facing (fully filled) metal vias inside the ceramic boss 402. Similarly, the metallized conductive pads 412 and 422 are electrically interconnected with the conductive pad 441 through vertically downward-facing (fully filled) metal vias inside the ceramic boss 402.

[0079] It should be noted that the size and position of the ceramic frame and boss, as well as the number of conductive pads and electrical interconnection logic, can all be adjusted according to actual needs.

[0080] In this embodiment, an alumina-based ceramic hermetic frame was fabricated using a high-temperature co-firing process. The ceramic frame has an external length and width of 16*16mm, a boss thickness of 0.8mm, a cavity length and width of 8mm*13mm, and a sidewall thickness of 1.5mm. The plating is encapsulated nickel-gold (ENIG). Furthermore, a 0.2mm thick Kovar alloy was soldered to the ceramic hermetic frame using a high-temperature brazing process as a stress buffer layer. The total thickness of the ceramic frame is 2mm, which matches the internal thickness of a conventional double-sided cooled power semiconductor module. Figure 5 As shown.

[0081] In this embodiment, a silicon nitride AMB substrate is selected, with a silicon nitride ceramic thickness of 0.32 mm and a copper thickness of 0.3 mm. The surface treatment is electroless nickel-gold plating (ENIG). The chip is metallized with nickel-palladium-gold, and the copper terminals are surface treated with electroless nickel-gold plating (ENIG). The pad is a copper-molybdenum alloy containing 70% molybdenum, and the surface treatment is nickel-silver.

[0082] In this embodiment, the insulation is a composite conformal coating consisting of a 15µm thick Parylene-HT film deposited inside and outside the module and a 90nm aluminum oxide inorganic layer film.

[0083] like Figure 7 , Figure 8 The specific connections and potting instructions for each part in the embodiment are as follows:

[0084] 1. Connection instructions for core components such as chips:

[0085] The drain of the upper bridge arm power semiconductor chip group is connected to the DC+ metallization region 201 of the lower substrate, and the power source is connected to the AC metallization region 101 through a pad.

[0086] The drain of the lower bridge arm power semiconductor chip is connected to the AC metallization region 101 of the upper substrate, and the power source is connected to the DC metallization region 202 of the upper substrate through a pad.

[0087] The gate of the upper bridge arm power semiconductor chip group is connected to the metallized pads 412.a and 422.a on the ceramic hermetic frame boss of the upper bridge arm via bonding wires; the Kelvin source of the upper bridge arm power semiconductor chip group is connected to the metallized pads 411.a, 413.a, 421.a and 423.a on the ceramic hermetic frame boss of the upper bridge arm via bonding wires.

[0088] The gate of the lower bridge arm power semiconductor chip is connected to the metallized pads 412.b and 422.b on the ceramic hermetic frame boss of the lower bridge arm via bonding wires; the Kelvin source of the lower bridge arm power semiconductor chip is connected to the metallized pads 411.b, 413.b, 421.b and 423.b on the ceramic hermetic frame boss of the lower bridge arm via bonding wires.

[0089] 2. Terminal connection instructions:

[0090] The top of the lower substrate 2 is provided with a DC+ metallization region 201, a DC- metallization region 202, an upper bridge arm Kelvin source metallization region 204, and an upper bridge arm gate metallization region 203. Correspondingly, the DC+ power terminal 211 and the upper bridge arm Kelvin drain signal terminal 213 are connected to the DC+ metallization region 201, the upper bridge arm Kelvin source signal terminal 215 is connected to the lower bridge arm Kelvin source metallization region 204, the upper bridge arm gate signal terminal 214 is connected to the upper bridge arm gate metallization region 203, the DC- power terminal 212 is connected to the DC- metallization region, and the decoupling capacitor 3 is connected to the DC+ and DC- metallization regions respectively.

[0091] The bottom of the upper substrate 1 is provided with an AC metallization region 101, a Kelvin source metallization region 102 of the lower bridge arm, and a gate metallization region 103 of the lower bridge arm. Correspondingly, the AC power terminal 111 and the Kelvin drain signal terminal 112 of the lower bridge arm are connected to the metallization region 101, the Kelvin source signal terminal 114 of the lower bridge arm is connected to the Kelvin source metallization region 102 of the lower bridge arm, and the gate signal terminal 113 of the lower bridge arm is connected to the gate metallization region 103 of the lower bridge arm.

[0092] 3. Ceramic airtight frame connection instructions:

[0093] The upper metal sealing ring 431.a of the upper bridge arm ceramic hermetic frame is connected to the AC metallization region 101, and the lower metal sealing ring 432.a is connected to the DC+ metallization region 201. The AC metallization region, the DC+ metallization region, and the ceramic hermetic frame together form the hermetic cavity of the upper bridge arm. The conductive pad 441.a below the ceramic boss is connected to the gate metallization region 203 of the upper bridge arm, and the conductive pad 442.a below the ceramic boss is connected to the Kelvin source metallization region 204 of the upper bridge arm.

[0094] The upper metal sealing ring 431.b of the lower bridge arm ceramic hermetic frame is connected to the DC-metallization region 202, and the lower metal sealing ring 432.b is connected to the AC-metallization region 101. The DC-metallization region, the AC-metallization region, and the ceramic hermetic frame together form the hermetic cavity of the lower bridge arm. The conductive pad 441.b below the ceramic boss is connected to the gate metallization region 103 of the lower bridge arm, and the conductive pad 442.b below the ceramic boss is connected to the Kelvin source metallization region 102 of the lower bridge arm.

[0095] 4. Filling Instructions:

[0096] In this embodiment, Kapton tape is used to mask areas that do not require coating with insulating material. A 15µm Pyrelin HT layer is prepared by CVD process, and then a 90nm alumina inorganic layer is prepared by ALD method to form a high-temperature resistant and highly insulating composite conformal coating 8.

[0097] The relevant evidence for the technical effects obtained by the embodiments of the present invention is as follows:

[0098] The model of the ceramic hermetically sealed double-sided cooled high-temperature power semiconductor device packaging architecture described in this invention is as follows: Figure 9 As shown in (a), a model of a packaging architecture for double-sided cooled power semiconductor devices using a traditional hermetically sealed casing is established. Figure 9 As shown in (b). The parasitic inductance of both was extracted by simulation at 100kHz, and the results are as follows. Figure 2 As shown; the embodiments of the present invention maintain the advantage of low parasitic inductance of the double-sided module, with a parasitic inductance of only 3.43nH, as... Figure 10 As shown in (a); conversely, the module sealed using a conventional hermetically sealed architecture extends the path length of the converter loop, resulting in a significant increase in parasitic inductance. The extracted parasitic inductance is 8.55 nH, which is 249% larger than that of the embodiment of the present invention. Figure 10 As shown in (b). Under identical conditions of loss and heat dissipation, thermal simulations were performed on both, and the thermal simulation results of this embodiment are as follows. Figure 11 As shown in (a), the thermal simulation results of the package using a traditional hermetically sealed architecture are as follows: Figure 11 As shown in (b), the traditional hermetic architecture adds a thick, low-thermal-conductivity Kovar layer to the heat dissipation path, significantly increasing thermal resistance. However, the embodiments of the present invention do not affect the original heat dissipation path of the module. The embodiments of the present invention maintain the advantage of low thermal resistance in the double-sided cooling module, with a junction temperature 34% lower than modules packaged using a traditional hermetic architecture.

[0099] Example 1:

[0100] In a typical high-power-density application, a silicon nitride (Si3N4) ceramic substrate is selected. The upper and lower substrates are fabricated using an active metal brazing (AMB) process. The metal layer uses copper (Cu) and undergoes a nickel-gold plating (Ni / Au) treatment to improve interface stability and oxidation resistance. The power semiconductor chip is a 1200V-class SiC MOSFET chip. The power source is connected to the metallized region of the lower substrate via an ag-sintering process to achieve excellent interface thermal stability at high temperatures. The Kelvin source and gate of the chip are connected to the metallized pads on the top of the ceramic hermetic frame via aluminum-bondwires, respectively, to achieve independent gate control loops and improve switching transient response speed.

[0101] The ceramic hermetic frame is made of aluminum nitride (AlN) ceramic and is sealed to the upper and lower substrates via a metal sealing ring at the bottom, ensuring excellent hermeticity of the device even during long-term operation at 250°C. The interior of the frame uses a sol-gel type high-temperature corrosion-resistant organic-inorganic hybrid material as the potting medium, completely encapsulating the chip, bonding area, and decoupling capacitors, effectively improving the insulation withstand voltage rating. The decoupling capacitors are high-temperature tantalum capacitors, connected in series between the internal buses of the ceramic frame, optimizing DC bus stability and electromagnetic interference suppression during device switching transients.

[0102] Example 2:

[0103] In the device architecture designed for extreme aerospace environments, aluminum nitride (AlN) substrates are used to fabricate both upper and lower substrates via direct copper bonding (DBC). The copper layer surface is silver-plated (Ag) to reduce contact resistance and ensure compatibility with subsequent bonding processes. The selected power semiconductor chip is a 650V SiC JBS (junction barrier Schottky) device. The chip's power source is sintered to the lower substrate's metallization layer using nano-silver paste to reduce thermomechanical stress at the contact interface. The Kelvin source and gate are replaced with copper cuclips instead of traditional bonding wires, achieving an ultra-low parasitic inductance structure and further improving high-frequency switching characteristics.

[0104] The hermetic ceramic frame employs a multilayer silicon nitride (MLSiN) composite ceramic structure, which is silver-sintered and sealed to the upper and lower substrates through metallized sealing areas at the top and bottom, forming an integral hermetic cavity. The internal potting material is siloxane-modified polyimide (Si-PI) high-temperature insulating material, fully covering the chip surface and internal metal connection areas to enhance high-temperature insulation strength. The decoupling capacitor uses a high-temperature stable ceramic capacitor (C0G / NP0 dielectric) to rapidly suppress transient voltage spikes on the DC bus, ensuring the device's electrical stability and long-term reliable operation in harsh environments.

[0105] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A packaging architecture for a low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device, characterized in that, include: Upper substrate, lower substrate, decoupling capacitor, ceramic sealing frame, bonding wire or metal foil, power semiconductor chip, pad, and high-temperature potting material; The upper and lower substrates are respectively provided with metallized regions and connected to the power semiconductor chip and terminals. The power source of the power semiconductor chip is connected to the metallized region of the substrate through a pad. The Kelvin source and gate of the chip are connected to the metallized conductive pads on the ceramic sealing frame protrusion through bonding wires or metal foil. The decoupling capacitor is arranged between the positive and negative busbars. The potting material covers all surfaces of the device that need to be insulated. The packaging architecture consists of two sets of packaging structures arranged in a mirror arrangement, with a ceramic sealing frame on each of the upper and lower bridge arms. One of the ceramic sealing frames is connected to the metallized area of ​​the upper substrate via an upper metal sealing ring, and to the metallized area of ​​the lower substrate via a lower metal sealing ring and a metal conductive pad; the other ceramic sealing frame is connected to the metallized area of ​​the lower substrate via an upper metal sealing ring, and to the metallized area of ​​the upper substrate via a lower metal sealing ring and a metal conductive pad; thus achieving airtight sealing and electrical connection. The ceramic sealing frame consists of a ceramic sidewall substrate, a ceramic boss, a cavity, six metallized conductive pads, an upper metal sealing ring, a lower metal sealing ring, and metal conductive pads. The six metallized conductive pads are located inside the upper metal sealing ring and outside the lower metal sealing ring. The metallized conductive pads are electrically connected to the conductive pads through vertically downward metal through-holes inside the ceramic boss.

2. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The upper and lower substrates are manufactured using high-temperature co-firing, low-temperature co-firing, AMB, DBC, or DPC processes. The substrate materials include silicon nitride, aluminum nitride, diamond, diamond-ceramic hybrid, zirconium oxide-toughened alumina, or alumina. The metallized conductive pads and metal conductive pads are made of silver, aluminum, or copper. The surface plating of the metallized conductive pads and metal conductive pads is silver plating, nickel-silver plating, nickel plating, nickel-gold plating, gold plating, or bare copper.

3. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The decoupling capacitor is a ceramic capacitor or a film capacitor.

4. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The ceramic sealing frame is manufactured using a high-temperature co-firing process, a low-temperature co-firing process, an AMB process, a DBC process, or a DPC process. The base material is silicon nitride, aluminum nitride, diamond, diamond-ceramic hybrid, zirconium oxide-toughened alumina, or alumina. The metallized area is plated with silver, nickel-silver, nickel, nickel-gold, gold, or bare copper. The boss conductive pads of the ceramic sealing frame are electrically connected to their external conductive pads.

5. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The power semiconductor chip includes Si-based, SiC-based, GaN-based, diamond-based, or gallium oxide-based power devices. The interconnection between the chip, terminals, ceramic frame, and substrate is achieved using silver sintering, copper sintering, welding, hot-press bonding, transient liquid phase bonding, or ultrasonic bonding processes.

6. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The pad material is copper, copper diamond, silver diamond, carbon-based reinforced metal, molybdenum, or copper-molybdenum-copper, and the surface of the pad is plated with silver, nickel-silver, nickel, nickel-gold, or gold, or is bare copper.

7. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The bonding wire is gold wire, aluminum wire, copper wire or alloy wire, and the metal foil is copper foil, aluminum foil or silver foil.

8. The low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 1, characterized in that, The high-temperature potting material is polyimide or phenelzine.

9. A packaging method for preparing a low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in any one of claims 1 to 8, characterized in that, Includes the following steps: (1) Provide an upper substrate and a lower substrate, wherein the substrate is made by high temperature co-firing, low temperature co-firing, AMB, DBC or DPC process, and the substrate material includes silicon nitride, aluminum nitride, diamond, diamond mixed ceramic, zirconium oxide toughened alumina or alumina, and the metallization area material on both sides of the substrate includes silver, aluminum or copper, and the surface coating of the metallization area is silver plating, nickel silver plating, nickel plating, nickel gold plating, gold plating or bare copper. (2) Connect the power source of the power semiconductor chip to the corresponding metallization area of ​​the substrate through a pad. The pad is made of copper, copper diamond, silver diamond, carbon-based reinforced metal, molybdenum or copper-molybdenum-copper and is metal-plated on the surface. (3) Connect the Kelvin source and gate of the power semiconductor chip to the metallized conductive pads on the ceramic sealing frame boss through bonding wires or metal foil. (4) A ceramic sealing frame is prepared by high temperature co-firing process, low temperature co-firing process, AMB process, DBC process or DPC process, and the upper metal sealing ring of the ceramic sealing frame is connected to the metallized area of ​​the corresponding substrate, and the lower metal sealing ring and metal conductive pad of the ceramic sealing frame are connected to the metallized area of ​​the corresponding substrate to achieve airtight sealing and electrical connection. (5) Decoupling capacitors are set between the positive and negative busbars, and high-temperature potting material is covered on the surface of the chip, interconnect area and internal structure to complete the encapsulation.

10. The packaging method of the low-inductance, low-thermal-resistance, high-temperature resistant SiC power semiconductor device packaging architecture as described in claim 9, characterized in that, The connection between the chip and the substrate, and between the terminal and the ceramic sealing frame, is achieved using silver sintering, copper sintering, welding, hot pressing, transient liquid phase bonding, or ultrasonic bonding processes; the high-temperature potting material is polyimide or phenelzine.

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