A key integrity verification method, system, medium and program product

Abstract

The application discloses a kind of key integrity check method, system, medium and program product, belong to key check technical field.The method is used for SoC security system, including the following steps: initialization stage, the load board of test equipment is powered on, then release chip external global reset;Check stage, run key SM3 check value programming test sequence, use SM3 algorithm to carry out key integrity check;Test stage, carry out key SM3 check value test, judge whether key SM3 check value test passes, if key SM3 check value test passes, then judge that the chip is good product, continue to carry out other chip test, if key SM3 check value test does not pass, then judge that the chip is defective product.The key stored in OTP / eFuse component is checked by SM3 security algorithm of state secret, and the check value is stored in OTP / eFuse component, the algorithm check of key integrity is realized, and safety and reliability are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of key verification technology, and in particular to a key integrity verification method, system, medium, and program product. Background Technology

[0002] With the rapid development of IoT (Internet of Things) and artificial intelligence technologies, the security and reliability of chip-stored data are becoming increasingly important. This has led to the widespread application of eFuse or OTP (One-Time Programmable) devices in embedded SoC (System-on-Chip) chips. As a non-volatile memory device, OTP is a one-time programmable device with high reliability, strong stability, and radiation resistance. Once programmed, the data is permanently stored for the entire lifespan of the OTP, unaffected by external interference and tamper-proof.

[0003] However, eFuse or OTP still carries reliability risks. Values ​​read from eFuse or OTP may change after prolonged aging or exposure to cosmic rays. Therefore, redundancy is typically implemented, such as mapping 2-bit physical addresses to 1-bit logical addresses and adding redundant bits to enhance storage reliability. Existing technologies only mitigate the risk of reliability issues with simple techniques; they cannot directly determine whether bit flips have occurred, nor can they correct errors when bit flips do occur. They also lack security algorithms to guarantee storage reliability, resulting in insufficient security in the field of security chips. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a key integrity verification method, system, medium and program product.

[0005] The objective of this invention is achieved through the following technical solution: The first aspect of this invention provides: a key integrity verification method for a SoC security system, comprising the following steps: During the initialization phase, the load board of the test equipment is powered on, and then the external global reset of the chip is released. During the verification phase, the SM3 checksum programming test sequence is run, and the SM3 algorithm is used to verify the key integrity. During the testing phase, the SM3 key verification value test is performed to determine whether the SM3 key verification value test passes. If the SM3 key verification value test passes, the chip is determined to be a good product, and the testing of other chips continues. If the SM3 key verification value test fails, the chip is determined to be a defective product.

[0006] Preferably, the SoC security system includes: The CPU component is connected to the AHB2CFG component, which in turn is connected to the CFG_ARB component. The CFG_ARB component is connected to the ATE_RW_REG component and the CFG_DEC component. The ATE_RW_REG component is connected to the TAP_CTRL component, which is connected to the JTAG component. The CFG_DEC component is connected to the OTP_CTRL component, the TRNG component, and the SM3 component. The OTP_CTRL component is connected to the OTP / eFuse component, the TRNG component, and the SM3 component. The CPU component is used to control the operation process, implement security policies, and manage keys for the SoC security system. The AHB2CFG component is used to convert the AHB bus into a configuration register bus. The CFG_ARB component is used to perform polling arbitration operations on different register operations of the master device. In the ATE test scenario, only the ATE_RW_REG component is allowed to perform read and write operations on the SoC registers. The ATE_RW_REG component is used to convert the JTAG bus protocol into a SoC-private register read / write control bus. During ATE testing, the registers of the components required for testing are configured through the JTAG component. The CFG_DEC component is used to decode register read / write addresses and route register read / write requests to various target components. The TAP_CTRL component is used to implement the JTAG protocol based on JTAG signals and communicate with the ATE_RW_REG component; The JTAG component is used to physically connect the JTAG pins to the ATE equipment. The OTP_CTRL component is used to implement read and write operations, permission management, and CPU command processing of the OTP / eFuse component; The TRNG component is used to generate truly random numbers; The SM3 component is used to perform hash operations on the data; The OTP / eFuse component is used to store chip PUF values, chip ID information, simulated IP checksums, firmware information, and various keys.

[0007] Preferably, the testing equipment is an ATE machine or a CPU.

[0008] Preferably, when the testing equipment is an ATE (Automatic Test Equipment) machine, the verification stage includes the following steps: The command used to configure the SM3 command register of the ATE machine is a key hash command; The SM3 component reads the key area of ​​the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component performs a hash operation on the key and temporarily stores the hash value into the SM3 component. The SM3 component triggers the OTP_CTRL component to program the hash value; The OTP_CTRL component programs the hash value of the key into a specified area of ​​the OTP / eFuse component; After the OTP_CTRL component completes the programming operation, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the successful completion of the command to the SM3 status register. The ATE machine reads the successful completion status value from the SM3 status register, confirming that the hash value of the confirmation key has been written into the OTP / eFuse component.

[0009] Preferably, when the testing device is a CPU, the verification stage includes the following steps: The command that configures the SM3 command register on the CPU is the key verification command; The SM3 component reads the key area of ​​the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component reads the key verification area of ​​the OTP / eFuse component and temporarily stores the verification value of the read key in the SM3 component; The SM3 component performs a hash operation on the key to generate a hash value for the key; The SM3 component compares the hash value calculated by the SM3 component with the check value. If the comparison passes, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of successful command completion to the SM3 status register. The CPU reads the returned check status value and confirms that the SM3 check is successful. If the comparison fails, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the failed comparison to the SM3 status register. The CPU reads the returned check status value and confirms that the SM3 check has failed.

[0010] Preferably, when the test equipment is an ATE machine, the verification phase is performed by configuring the SM3 register through the JTAG component; when the test equipment is a CPU, the verification phase is performed directly by configuring the SM3 register through the CPU.

[0011] A second aspect of the present invention provides: a key integrity verification system for implementing any of the above-described key integrity verification methods, comprising: The initialization module is used to power on the load board of the test equipment and then release the external global reset of the chip. The verification module is used to run the SM3 checksum programming test sequence and perform key integrity verification using the SM3 algorithm. The testing module is used to perform SM3 key verification value testing and determine whether the SM3 key verification value test passes. If the SM3 key verification value test passes, the chip is determined to be good and other chips are tested. If the SM3 key verification value test fails, the chip is determined to be defective.

[0012] A third aspect of the present invention provides: a computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are loaded and executed by a processor, any of the above-described key integrity verification methods are implemented.

[0013] A fourth aspect of the present invention provides: a computer program product containing instructions, which, when run on a terminal, causes the terminal to execute any of the above-described key integrity verification methods.

[0014] The beneficial effects of this invention are: 1) This invention uses the national cryptographic SM3 security algorithm to verify the key stored in the OTP / eFuse component and stores the verification value in the OTP / eFuse component, thereby realizing the algorithm verification of key integrity and greatly improving security and reliability. Attached Figure Description

[0015] Figure 1 This is a block diagram of the SoC security system principle. Detailed Implementation

[0016] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] See Figure 1 The first aspect of this invention provides: a key integrity verification method for a SoC security system, comprising the following steps: During the initialization phase, the load board of the test equipment is powered on, and then the external global reset of the chip is released. During the verification phase, the SM3 checksum programming test sequence is run, and the SM3 algorithm is used to verify the key integrity. During the testing phase, the SM3 key verification value test is performed to determine whether the SM3 key verification value test passes. If the SM3 key verification value test passes, the chip is determined to be a good product, and the testing of other chips continues. If the SM3 key verification value test fails, the chip is determined to be a defective product.

[0018] In this embodiment, there are two ways to program the verification value during the verification phase: ATE (Automatic Test Equipment) machine programming and CPU programming. The keys being verified include the root key and other types of keys, etc.

[0019] In some embodiments, the SoC security system includes: The CPU component is connected to the AHB2CFG component, which in turn is connected to the CFG_ARB component. The CFG_ARB component is connected to the ATE_RW_REG component and the CFG_DEC component. The ATE_RW_REG component is connected to the TAP_CTRL component, which is connected to the JTAG component. The CFG_DEC component is connected to the OTP_CTRL component, the TRNG component, and the SM3 component. The OTP_CTRL component is connected to the OTP / eFuse component, the TRNG component, and the SM3 component. The CPU component is used to control the operation process, implement security policies, and manage keys for the SoC security system. The AHB2CFG component is used to convert the AHB bus into a configuration register bus. The CFG_ARB component is used to perform polling arbitration operations on different register operations of the master device. In the ATE test scenario, only the ATE_RW_REG component is allowed to perform read and write operations on the SoC registers. The ATE_RW_REG component is used to convert the JTAG bus protocol into a SoC-private register read / write control bus. During ATE testing, the registers of the components required for testing are configured through the JTAG component. The CFG_DEC component is used to decode register read / write addresses and route register read / write requests to various target components. The TAP_CTRL component is used to implement the JTAG protocol based on JTAG signals and communicate with the ATE_RW_REG component; The JTAG component is used to physically connect the JTAG pins to the ATE equipment. The OTP_CTRL component is used to implement read and write operations, permission management, and CPU command processing of the OTP / eFuse component; The TRNG component is used to generate truly random numbers; The SM3 component is used to perform hash operations on the data; The OTP / eFuse component is used to store chip PUF values, chip ID information, simulated IP checksums, firmware information, and various keys.

[0020] In some embodiments, the test equipment is an ATE machine or a CPU.

[0021] In some embodiments, when the test equipment is an ATE (Automatic Test Equipment) machine, the verification phase includes the following steps: The command used to configure the SM3 command register of the ATE machine is a key hash command; The SM3 component reads the key area of ​​the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component performs a hash operation on the key and temporarily stores the hash value into the SM3 component. The SM3 component triggers the OTP_CTRL component to program the hash value; The OTP_CTRL component programs the hash value of the key into a specified area of ​​the OTP / eFuse component; After the OTP_CTRL component completes the programming operation, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the successful completion of the command to the SM3 status register. The ATE machine reads the successful completion status value from the SM3 status register, confirming that the hash value of the confirmation key has been written into the OTP / eFuse component.

[0022] In this embodiment, the process information includes the root key or other keys that have been temporarily stored in the hardware, hash values, etc. The process of generating hash values ​​and comparing hash values ​​for other keys is similar to that for keys and will not be described again.

[0023] In some embodiments, when the test device is a CPU, the verification phase includes the following steps: The command that configures the SM3 command register on the CPU is the key verification command; The SM3 component reads the key area of ​​the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component reads the key verification area of ​​the OTP / eFuse component and temporarily stores the verification value of the read key in the SM3 component; The SM3 component performs a hash operation on the key to generate a hash value for the key; The SM3 component compares the hash value calculated by the SM3 component with the check value. If the comparison passes, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of successful command completion to the SM3 status register. The CPU reads the returned check status value and confirms that the SM3 check is successful. If the comparison fails, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the failed comparison to the SM3 status register. The CPU reads the returned check status value and confirms that the SM3 check has failed.

[0024] In some embodiments, when the test device is an ATE machine, the verification phase is performed by configuring the SM3 register through the JTAG component; when the test device is a CPU, the verification phase is performed directly by configuring the SM3 register through the CPU.

[0025] A second aspect of the present invention provides: a key integrity verification system for implementing any of the above-described key integrity verification methods, comprising: The initialization module is used to power on the load board of the test equipment and then release the external global reset of the chip. The verification module is used to run the SM3 checksum programming test sequence and perform key integrity verification using the SM3 algorithm. The testing module is used to perform SM3 key verification value testing and determine whether the SM3 key verification value test passes. If the SM3 key verification value test passes, the chip is determined to be good and other chips are tested. If the SM3 key verification value test fails, the chip is determined to be defective.

[0026] A third aspect of the present invention provides: a computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are loaded and executed by a processor, any of the above-described key integrity verification methods are implemented.

[0027] A fourth aspect of the present invention provides: a computer program product containing instructions, which, when run on a terminal, causes the terminal to execute any of the above-described key integrity verification methods.

[0028] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A key integrity verification method, characterized in that: For SoC security systems, the following steps are included: During the initialization phase, the load board of the test equipment is powered on, and then the external global reset of the chip is released. During the verification phase, the SM3 checksum programming test sequence is run, and the SM3 algorithm is used to verify the key integrity. During the testing phase, the SM3 key verification value test is performed to determine whether the SM3 key verification value test passes. If the SM3 key verification value test passes, the chip is determined to be a good product, and the testing of other chips continues. If the SM3 key verification value test fails, the chip is determined to be a defective product. The testing equipment mentioned is an ATE machine and a CPU; When the test equipment is an ATE (Automatic Test Equipment) machine, the verification stage includes the following steps: The command used to configure the SM3 command register of the ATE machine is a key hash command; The SM3 component reads the key area of ​​the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component performs a hash operation on the key and temporarily stores the hash value into the SM3 component. The SM3 component triggers the OTP_CTRL component to program the hash value; The OTP_CTRL component programs the hash value of the key into a specified area of ​​the OTP / eFuse component; After the OTP_CTRL component completes the programming operation, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the successful completion of the command to the SM3 status register. The ATE machine reads the successful completion status value from the SM3 status register, confirming that the hash value of the key has been written into the OTP / eFuse component; When the test device is a CPU, the verification phase includes the following steps: The command that configures the SM3 command register on the CPU is the key verification command; The SM3 component reads the key area of ​​the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component reads the key verification area of ​​the OTP / eFuse component and temporarily stores the verification value of the read key in the SM3 component; The SM3 component performs a hash operation on the key to generate a hash value for the key; The SM3 component compares the hash value calculated by the SM3 component with the check value. If the comparison passes, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of successful command completion to the SM3 status register. The CPU reads the returned check status value and confirms that the SM3 check is successful. If the comparison fails, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the failed comparison to the SM3 status register. The CPU reads the returned check status value and confirms that the SM3 check has failed.

2. The key integrity verification method according to claim 1, characterized in that: The SoC security system includes: The CPU component is connected to the AHB2CFG component, which in turn is connected to the CFG_ARB component. The CFG_ARB component is connected to the ATE_RW_REG component and the CFG_DEC component. The ATE_RW_REG component is connected to the TAP_CTRL component, which is connected to the JTAG component. The CFG_DEC component is connected to the OTP_CTRL component, the TRNG component, and the SM3 component. The OTP_CTRL component is connected to the OTP / eFuse component, the TRNG component, and the SM3 component. The CPU component is used to control the operation process, implement security policies, and manage keys for the SoC security system. The AHB2CFG component is used to convert the AHB bus into a configuration register bus. The CFG_ARB component is used to perform polling arbitration operations on different registers of the master device. In the ATE test scenario, only the ATE_RW_REG component is allowed to perform read and write operations on the SoC registers. The ATE_RW_REG component is used to convert the JTAG bus protocol into a SoC-private register read / write control bus. During ATE testing, the registers of the components required for testing are configured through the JTAG component. The CFG_DEC component is used to decode register read / write addresses and route register read / write requests to various target components. The TAP_CTRL component is used to implement the JTAG protocol based on JTAG signals and communicate with the ATE_RW_REG component; The JTAG component is used to physically connect the JTAG pins to the ATE equipment. The OTP_CTRL component is used to implement read and write operations, permission management, and CPU command processing of the OTP / eFuse component; The TRNG component is used to generate truly random numbers; The SM3 component is used to perform hash operations on the data; The OTP / eFuse component is used to store chip PUF values, chip ID information, simulated IP checksums, firmware information, and various keys.

3. The key integrity verification method according to claim 1, characterized in that: When the test equipment is an ATE machine, the verification phase is performed by configuring the SM3 register through the JTAG component; when the test equipment is a CPU, the verification phase is performed directly by configuring the SM3 register through the CPU.

4. A key integrity verification system, characterized in that: A method for implementing the key integrity verification method as described in any one of claims 1-3 includes: The initialization module is used to power on the load board of the test equipment and then release the external global reset of the chip. The verification module is used to run the SM3 checksum programming test sequence and perform key integrity verification using the SM3 algorithm. The testing module is used to perform SM3 key verification value testing and determine whether the SM3 key verification value test passes. If the SM3 key verification value test passes, the chip is determined to be good and other chips are tested. If the SM3 key verification value test fails, the chip is determined to be defective.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the key integrity verification method as described in any one of claims 1-3.

6. A computer program product containing instructions, characterized in that: When the computer program product is run on a terminal, the terminal performs the key integrity verification method as described in any one of claims 1-3.

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