A device structure based on a trench isolation process

Abstract

The application discloses a device structure based on a trench isolation process, and the device comprises a first trench isolation structure and a second trench isolation structure; the second trench isolation structure is provided with a "serpentine" structure and comprises at least two trench unit structures, and is used for characterizing the stability and reliability of etching and filling processes; the first trench isolation structure is a closed ring structure, and the second trench isolation structure overlaps the first isolation structure on both sides, thereby forming two closed structure areas; by biasing voltage signals of first contact metals and second contact metals in the two structure areas, the leakage current and the breakdown voltage of the device structure are tested, so that the isolation performance and reliability of the process and the circuit can be accurately evaluated.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more specifically to a device structure based on trench isolation technology. Background Technology

[0002] For high-voltage power integrated circuits, the isolation between high-voltage devices differs from that between low-voltage devices. Due to the higher voltage and potential, the influence and crosstalk between devices are more severe, and parasitic transistors may be triggered. Therefore, more reliable isolation technology is required to achieve complete isolation of high-voltage devices. SOI technology with full dielectric isolation forms complete isolation between devices through dielectric trench structures, suppressing substrate current and eliminating latch-up effects. The reduction in substrate parasitic capacitance significantly reduces crosstalk, resulting in superior electromagnetic compatibility characteristics. It also improves switching speed and enables low-voltage designs, greatly simplifying the design process. Full dielectric isolation avoids complex high- and low-voltage isolation termination designs, significantly reducing silicon wafer area loss and increasing packaging density.

[0003] Trench isolation technology is a core process in SOI (Single-Insulation) technology, directly affecting the performance and reliability of devices and circuits. The increasing voltage of high-voltage power circuits leads to increased interference between devices integrated on the same chip, resulting in reduced device withstand voltage. Complete isolation through trench isolation can fundamentally improve this characteristic. However, trench isolation technology places very strict requirements on etching processes, sidewall oxidation, and polysilicon filling. The sidewalls of the trenches must be smooth after etching; otherwise, excessive stress can easily be generated, ultimately forming defects in the oxide layer, thus affecting the isolation characteristics and reliability of the integrated circuit. Summary of the Invention

[0004] The purpose of this invention is to provide a device structure based on trench isolation technology, solve the reliability problems of trench isolation technology and circuits, and test and evaluate the effect of trench isolation technology.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a device structure based on trench isolation technology, including a first active region, a second active region, a third active region, a fourth active region, a first trench isolation structure, a second trench isolation structure, a first doped region, a second doped region, a third doped region, a first contact hole, a second contact hole, a first contact metal, and a second contact metal. The first trench isolation structure is disposed inside the first active region and does not intersect with the first active region. The second trench isolation structure is disposed inside the second active region and does not intersect with the second active region. The first active region and the first trench isolation structure are each a closed ring structure. The two sides of the second active region overlap with the first active region. The two sides of the second active region overlap with the first trench isolation structure. The second active region and the second trench isolation structure constitute the third structural region. The third structural region divides the trench isolation process development structure into the first structural region and the second structural region. The first structural region contains the second doped region, the third active region, the first contact hole, and the first contact metal. The second structural region contains the third doped region, the fourth active region, the second contact hole, and the second contact metal. The third active region contains the second doped region and the first contact hole. The third active region does not intersect with the first and second active regions. The fourth active region contains the third doped region and the second contact hole. The fourth active region does not intersect with the first and second active regions.

[0006] Compared with existing technologies, the beneficial effects of this invention are as follows: The device structure based on trench isolation technology provided by this invention features a "serpentine" second trench isolation structure in the second structural region. Multiple trench unit structures increase the process complexity of trench etching, trench filling, and filling corrosion, accurately characterizing the development results of the trench isolation technology. This invention uses a first test electrode and a second test electrode to apply bias test voltage signals to the first and second structural regions, respectively, forming a test path between the first doped region, the second doped region of the first structural region, and the first doped region and the third doped region of the second structural region. This allows for testing of the device structure based on trench isolation technology, obtaining leakage current parameters and breakdown parameters of the device structure, and characterizing the isolation characteristics and reliability of the trench process and circuit products. Attached Figure Description

[0007] Figure 1 This is a top view of the device structure based on trench isolation technology according to the first embodiment of the present invention;

[0008] Figure 2 yes Figure 1 A sectional view along the AB direction;

[0009] Figure 3 yes Figure 1 A sectional view along the CD direction;

[0010] Figure 4 yes Figure 1 Sectional view along the EF direction;

[0011] Figure 5 This is a top view of the device structure based on trench isolation technology according to the second embodiment of the present invention;

[0012] Figure 6 yes Figure 5 A sectional view along the AB direction;

[0013] Figure 7 yes Figure 5 Sectional view along the EF direction;

[0014] Figure 8 This is a top view of the device structure based on trench isolation technology according to the third embodiment of the present invention;

[0015] Figure 9 This is a top view of the device structure based on trench isolation technology according to the fourth embodiment of the present invention.

[0016] Explanation of reference numerals in the attached figures: 101-First active region, 102-Second active region, 103-Third active region, 104-Fourth active region, 211-First trench isolation structure, 212-Second trench isolation structure, 31-First doped region, 32-Second doped region, 33-Third doped region, 41-First contact hole, 42-Second contact hole, 51-First contact metal, 52-Second contact metal, 311-First structural region, 312-Third structural region, 313-Substrate, 20-Buried oxide layer, 21-Linear oxide layer, 22-Trench filling layer, 23-Field isolation dielectric layer, 24-Gate oxide layer, 25-Pre-metal dielectric layer, 26-Inter-metal dielectric layer, 511-First test electrode, 521-Second test electrode. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] To evaluate the effectiveness of trench isolation technology development and improve the reliability of the process and circuitry, in one embodiment of the present invention, combined with... Figure 1 The device structure based on trench isolation technology includes:

[0019] The system includes a first active region 101, a second active region 102, a third active region 103, a fourth active region 104, a first trench isolation structure 211, a second trench isolation structure 212, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, and a second contact metal 52. The first trench isolation structure 211 is located inside the first active region 101 and does not intersect with it. The second trench isolation structure 212 is located inside the second active region 102 and does not intersect with it. The first active region 101 and the first trench isolation structure 211 are both closed annular structures. The two sides of the second active region 102 overlap with the first active region 101, and the two sides of the second trench isolation structure 212 overlap with the first trench isolation structure 211. The second active region 102 and the second trench isolation structure 212 are connected in a closed annular structure. The trench isolation structure 212 constitutes the third structural region 313. The third structural region 313 divides the trench isolation process development structure into a first structural region 311 and a second structural region 312. The first structural region 311 contains a second doped region 32, a third active region 103, a first contact hole 41, and a first contact metal 51. The second structural region 312 contains a third doped region 33, a fourth active region 104, a second contact hole 42, and a second contact metal 52. The third active region 103 contains a second doped region 32, and the second doped region 32 contains a first contact hole 41. The third active region 103 does not intersect with the first active region 101 and the second active region 102. The fourth active region 104 contains a third doped region 33, and the third doped region 33 contains a second contact hole 42. The fourth active region 104 does not intersect with the first active region 101 and the second active region 102.

[0020] The second trench isolation structure 212 is disposed inside the first trench isolation structure 211, and its two ends overlap with the first trench isolation structure 211 to form two closed structures. These two closed structures achieve full-medium isolation based on the first trench isolation structure 211 and the second trench isolation structure 212.

[0021] The second trench isolation structure 212 is serpentine in shape and contains at least two trench unit structures 220. The serpentine trench structure is used to evaluate the isolation characteristics and reliability of processes and circuits.

[0022] A first isolation gap 2a exists between the third active region 103, the fourth active region 104 and the first active region 101, and a second isolation gap 2b exists between the third active region 103, the fourth active region 104 and the second active region 102, wherein the first isolation gap 2a and the second isolation gap 2b are equal. Specifically, the dimensions of the first isolation gap 2a and the second isolation gap 2b are 10μm to 100μm, and different gap dimensions are designed according to different voltage levels.

[0023] The first doped region 31, the second doped region 32, and the third doped region 33 are doped regions of the same type, which can be N-type or P-type doped. The second doped region 32 and the third doped region 33 are heavily doped regions with an implantation dose of 1E15cm. -2 ~1E16cm -2 .

[0024] Figure 2 yes Figure 1 The AB-direction cross-sectional view in the embodiment shows the device disposed on an SOI substrate, including a substrate 11, a buried oxide layer 20, a first trench isolation structure 211, a second trench isolation structure 212, a linear oxide layer 21, a trench filling layer 22, a field isolation dielectric layer 23, a gate oxide layer 24, a metal front dielectric layer 25, an inter-metal dielectric layer 26, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, a second contact metal 52, a first test electrode 511, a second test electrode 521, and the second trench isolation structure 212 is disposed between the first trench isolation structures 211. A gate oxide layer 24 is disposed on the surface of the isolation structure 212. The gate oxide layer 24 and the field isolation dielectric layer 23 are alternately arranged on the surface of the first doped region 31. A first contact hole 41 is disposed on the surface of the second doped region 32, and a second contact hole 42 is disposed on the surface of the third doped region 33. A first contact metal 51 leads out the second doped region 32 through the first contact hole 41 to form a first test electrode 511. A second contact metal 52 leads out the third doped region 33 through the second contact hole 42 to form a second test electrode 521. The first contact metal 51 and the second contact metal 52 are isolated from each other by an intermetallic dielectric layer 26, and the first contact hole 41 and the second contact hole 42 are isolated from each other by a metal front dielectric layer 25.

[0025] Figure 3 yes Figure 1The embodiment is a cross-sectional view along the CD direction. The device is disposed on an SOI substrate and includes a substrate 11, a buried oxide layer 20, a first trench isolation structure 211, a second trench isolation structure 212, a linear oxide layer 21, a trench filling layer 22, a field isolation dielectric layer 23, a gate oxide layer 24, a metal front dielectric layer 25, an inter-metal dielectric layer 26, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, a second contact metal 52, a first test electrode 511, a second test electrode 521, and the second trench isolation structure 212 is disposed between the first trench isolation structures 211. The first trench isolation structure 211 and the second trench... A gate oxide layer 24 is disposed on the surface of the isolation structure 212. The gate oxide layer 24 and the field isolation dielectric layer 23 are alternately arranged on the surface of the first doped region 31. A first contact hole 41 is disposed on the surface of the second doped region 32, and a second contact hole 42 is disposed on the surface of the third doped region 33. A first contact metal 51 leads out the second doped region 32 through the first contact hole 41 to form a first test electrode 511. A second contact metal 52 leads out the third doped region 33 through the second contact hole 42 to form a second test electrode 521. The first contact metal 51 and the second contact metal 52 are isolated from each other by an intermetallic dielectric layer 26, and the first contact hole 41 and the second contact hole 42 are isolated from each other by a metal front dielectric layer 25.

[0026] Figure 4 yes Figure 1 The cross-sectional view along the EF direction in the embodiment shows that the device is disposed on an SOI substrate and includes a substrate 11, a buried oxide layer 20, a first trench isolation structure 211, a second trench isolation structure 212, a linear oxide layer 21, a trench filling layer 22, a field isolation dielectric layer 23, a gate oxide layer 24, a metal front dielectric layer 25, an intermetallic dielectric layer 26, and a first doped region 31. The gate oxide layer 24 is disposed on the surface of the first trench isolation structure 211 and the second trench isolation structure 212. The gate oxide layer 24 and the field isolation dielectric layer 23 are disposed on the surface of the first doped region 31. The metal front dielectric layer 25 is disposed on the upper surface of the gate oxide layer 24 and the field isolation dielectric layer 23. The intermetallic dielectric layer 26 is disposed on the upper surface of the metal front dielectric layer 25. At least four second trench isolation structures 212 are disposed in the device structure.

[0027] Specifically, the first trench isolation structure 211 and the second trench isolation structure 212 include a linear oxide layer 21 and a trench filling layer 22, wherein the trench filling layer 22 includes polycrystalline silicon or silicon oxide material.

[0028] Specifically, the substrate 11 is N-type doped or P-type doped.

[0029] Specifically, the field isolation medium layer 23 is a field oxide layer formed by an oxidation process or a shallow trench medium layer formed by a shallow trench isolation process.

[0030] Specifically, the second trench isolation structure 212 is surrounded by the second active region 102, and each side of the second trench isolation structure 212 is perpendicular or parallel to the four sides of the first trench isolation structure 211. The first trench isolation structure 211 and the second trench isolation structure 212 are both at a 90° angle.

[0031] Figure 5 This is a top view of a device structure based on trench isolation technology according to the second embodiment of the present invention, including a first active region 101, a second active region 102, a third active region 103, a fourth active region 104, a first trench isolation structure 211, a second trench isolation structure 212, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, and a second contact metal 52. The second active region 102 is configured in a "serpentine" structure, and the second trench isolation structure 212 is disposed inside the second active region 102, which increases the complexity of the manufacturing process and is used to evaluate the development effect of trench etching, trench filling, filling corrosion and other processes as well as circuit performance.

[0032] Furthermore, the first structural region 311 is biased by the test voltage signal through the first contact hole 41 and the first contact metal 51, and the second structural region 312 is biased by the test voltage signal through the second contact hole 42 and the second contact metal 52.

[0033] Furthermore, either the first contact metal 51 or the second contact metal 52 is used to bias a positive voltage signal or a negative voltage signal, and the other is used to bias zero voltage.

[0034] Figure 6 yes Figure 5A cross-sectional view along the AB direction shows the device disposed on an SOI substrate, including a substrate 11, a buried oxide layer 20, a first trench isolation structure 211, a second trench isolation structure 212, a linear oxide layer 21, a trench fill layer 22, a field isolation dielectric layer 23, a gate oxide layer 24, a metal front dielectric layer 25, an inter-metal dielectric layer 26, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, a second contact metal 52, a first test electrode 511, a second test electrode 521, and the second trench isolation structure 212 is disposed between the first trench isolation structures 211. A gate oxide layer 24 is disposed on the surface of structure 212. The gate oxide layer 24 and the field isolation dielectric layer 23 are alternately arranged on the surface of the first doped region 31. A first contact hole 41 is disposed on the surface of the second doped region 32, and a second contact hole 42 is disposed on the surface of the third doped region 33. A first contact metal 51 leads out the second doped region 32 through the first contact hole 41 to form a first test electrode 511. A second contact metal 52 leads out the third doped region 33 through the second contact hole 42 to form a second test electrode 521. The first contact metal 51 and the second contact metal 52 are isolated from each other by an intermetallic dielectric layer 26, and the first contact hole 41 and the second contact hole 42 are isolated from each other by a metal front dielectric layer 25.

[0035] Figure 7 yes Figure 5 A cross-sectional view along the EF direction shows a device disposed on an SOI substrate, including a substrate 11, a buried oxide layer 20, a first trench isolation structure 211, a second trench isolation structure 212, a linear oxide layer 21, a trench filling layer 22, a field isolation dielectric layer 23, a gate oxide layer 24, a metal front dielectric layer 25, an intermetallic dielectric layer 26, and a first doped region 31. The gate oxide layer 24 is disposed on the surface of the first trench isolation structure 211 and the second trench isolation structure 212. The gate oxide layer 24 and the field isolation dielectric layer 23 are alternately disposed on the surface of the first doped region 31. The metal front dielectric layer 25 is disposed on the upper surface of the gate oxide layer 24 and the field isolation dielectric layer 23. The intermetallic dielectric layer 26 is disposed on the upper surface of the metal front dielectric layer 25. At least four second trench isolation structures 212 are disposed in the device structure.

[0036] Figure 8This is a top view of a device structure based on trench isolation technology according to the third embodiment of the present invention. The device includes a first active region 101, a second active region 102, a third active region 103, a fourth active region 104, a first trench isolation structure 211, a second trench isolation structure 212, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, and a second contact metal 52. The four corners of the first trench isolation structure 211 are designed to be 135°, and the corners of the second trench isolation structure 212 are all designed with 135° chamfers.

[0037] Figure 9 This is a top view of a device structure based on trench isolation technology according to the fourth embodiment of the present invention. The device includes a first active region 101, a second active region 102, a third active region 103, a fourth active region 104, a first trench isolation structure 211, a second trench isolation structure 212, a first doped region 31, a second doped region 32, a third doped region 33, a first contact hole 41, a second contact hole 42, a first contact metal 51, and a second contact metal 52. The four corners of the first trench isolation structure 211 are designed to be rounded, and the corners of the second trench isolation structure 212 are also designed to be rounded.

[0038] Specifically, the device structure can be disposed on an SOI substrate or on a bulk silicon substrate.

[0039] In summary, the device structure based on trench isolation technology of the present invention comprises a first trench isolation structure that is a closed ring structure, and a second trench isolation structure that overlaps with the first trench isolation structure at both ends to form two closed structural regions. These closed regions are biased by test voltage signals applied to the first and second contact metals, respectively. By testing the leakage current and breakdown voltage of the device structure, the effectiveness of trench technology development and the isolation characteristics of the circuit product can be evaluated, thereby guiding trench technology development and circuit fabrication. The second trench isolation structure of the present invention employs a "serpentine" structural design, accurately characterizing the etching, filling, and other processes in the trench process.

Claims

1. A device structure based on trench isolation technology, characterized in that, The active region includes a first active region (101), a second active region (102), a third active region (103), a fourth active region (104), a first trench isolation structure (211), a second trench isolation structure (212), a first doped region (31), a second doped region (32), a third doped region (33), a first contact hole (41), a second contact hole (42), a first contact metal (51), and a second contact metal (52). The first trench isolation structure (211) is disposed inside the first active region (101). The second trench isolation structure (212) is located inside the second active region (102) and does not intersect with the first active region (101). The first active region (101) and the first trench isolation structure (211) are both closed ring structures. The two sides of the second active region (102) overlap with the first active region (101), and the two sides of the second trench isolation structure (212) overlap with the first trench isolation structure (211). The second active region (102) and the second trench isolation structure (212) are both closed ring structures. The trench isolation structure (212) constitutes the third structural region (313). The third structural region (313) divides the trench isolation process development structure into a first structural region (311) and a second structural region (312). The first structural region (311) contains a second doped region (32), a third active region (103), a first contact hole (41), and a first contact metal (51). The second structural region (312) contains a third doped region (33), a fourth active region (104), a second contact hole (42), and a third active region (51). Two contact metals (52), a second doped region (32) is provided inside the third active region (103), a first contact hole (41) is provided inside the second doped region (32), the third active region (103) does not intersect with the first active region (101) and the second active region (102), a third doped region (33) is provided inside the fourth active region (104), a second contact hole (42) is provided inside the third doped region (33), the fourth active region (104) does not intersect with the first active region (101) and the second active region (102).

2. The device structure based on trench isolation technology according to claim 1, characterized in that, The second trench isolation structure (212) is disposed inside the first trench isolation structure (211), and its two ends overlap with the first trench isolation structure (211) to form two closed structures. These two closed structures achieve full-medium isolation based on the first trench isolation structure (211) and the second trench isolation structure (212). The second trench isolation structure (212) is in the shape of a "snake". The second trench isolation structure (212) contains two or more trench unit structures (220).

3. A device structure based on trench isolation technology according to claim 1 or 2, characterized in that, There is a first isolation gap (2a) between the third active region (103), the fourth active region (104) and the first active region (101), and there is a second isolation gap (2b) between the third active region (103), the fourth active region (104) and the second active region (102). The first isolation gap (2a) and the second isolation gap (2b) are equal. The size of the first isolation gap (2a) and the second isolation gap (2b) is 10μm~100μm, and different gap sizes are designed according to different voltage levels.

4. A device structure based on trench isolation technology according to claim 1 or 2, characterized in that, The first doped region (31), the second doped region (32), and the third doped region (33) are doped regions of the same type, using N-type doping or P-type doping. The second doped region (32) and the third doped region (33) are heavily doped regions with an implantation dose of 1E15cm. -2 ~1E16cm -2 .

5. The device structure based on trench isolation technology according to claim 1, characterized in that, The trench isolation process development structure is set on an SOI substrate, including a substrate (11), a buried oxide layer (20), a first trench isolation structure (211), a second trench isolation structure (212), a linear oxide layer (21), a trench filling layer (22), a field isolation dielectric layer (23), a gate oxide layer (24), a metal front dielectric layer (25), an inter-metal dielectric layer (26), a first doped region (31), a second doped region (32), a third doped region (33), a first contact hole (41), a second contact hole (42), a first contact metal (51), a second contact metal (52), a first test electrode (511), and a second test electrode (521). The second trench isolation structure (212) is disposed between the first trench isolation structures (211), and the first trench isolation structure (211) and the second trench isolation structure are connected. A gate oxide layer (24) is disposed on the surface of the structure (212). The gate oxide layer (24) and the field isolation dielectric layer (23) are alternately arranged on the surface of the first doped region (31). The first contact hole (41) is disposed on the surface of the second doped region (32). The second contact hole (42) is disposed on the surface of the third doped region (33). The first contact metal (51) leads out the second doped region (32) through the first contact hole (41) and forms the first test electrode (511). The second contact metal (52) leads out the third doped region (33) through the second contact hole (42) and forms the second test electrode (521). The first contact metal (51) and the second contact metal (52) are isolated from each other by an intermetallic dielectric layer (26). The first contact hole (41) and the second contact hole (42) are isolated from each other by a metal front dielectric layer (25).

6. The device structure based on trench isolation technology according to claim 5, characterized in that, The first trench isolation structure (211) and the second trench isolation structure (212) include a linear oxide layer (21) and a trench filling layer (22), wherein the trench filling layer (22) includes polysilicon or silicon oxide material; and the substrate (11) is N-type doped or P-type doped.

7. The device structure based on trench isolation technology according to claim 1, characterized in that, The second trench isolation structure (212) is surrounded by the second active region (102). Each side of the second trench isolation structure (212) is perpendicular or parallel to the four sides of the first trench isolation structure (211). The turning angles of the first trench isolation structure (211) and the second trench isolation structure (212) are both 90°.

8. A device structure based on trench isolation technology according to claim 1 or 7, characterized in that, The second active region (102) is configured as a "serpentine" structure, and a second trench isolation structure (212) is provided inside the "serpentine" structure.

9. The device structure based on trench isolation technology according to claim 1, characterized in that, The four corners of the first trench isolation structure (211) are designed to be round, and the corners of the second trench isolation structure (212) are all designed to be round.

10. A device structure based on trench isolation technology according to claim 1, characterized in that, The first structural region (311) biases the test voltage signal through the first contact hole (41) and the first contact metal (51), and the second structural region (312) biases the test voltage signal through the second contact hole (42) and the second contact metal (52); either the first contact metal (51) or the second contact metal (52) is used to bias a positive voltage signal or a negative voltage signal, and the other is used to bias zero voltage.

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