A mask pattern, a mask structure and a method for manufacturing a semiconductor structure

Abstract

This disclosure provides a method for fabricating a mask pattern, a mask structure, and a semiconductor structure. The mask pattern includes a main pattern array and a preset pattern array. The main pattern array includes multiple main patterns arranged along a first direction and a second direction. The main pattern array includes at least a first pattern array located at the edge of the main pattern array. The first pattern array includes a reference main pattern and a secondary reference main pattern located at the outermost and second outermost edges of the main pattern array, respectively. The preset pattern array is located on at least one side of the first pattern array and includes multiple preset patterns. In the preset direction, the size of the preset pattern is smaller than the size of the reference main pattern, and the first pitch is smaller than the second pitch. The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the distance between the preset pattern array and the first pattern array is smaller than the second pitch in the same direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for preparing a mask pattern, a mask structure, and a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, it is used to transfer the designed circuit pattern onto the wafer. As chip integration increases, chip design makes the layout environment increasingly complex. Due to the shrinking size of devices, the difference between the pattern on the chip surface and the original photomask pattern increases after the photolithography process, which can easily lead to optical proximity effect (OPE) and other issues such as pattern distortion.

[0003] Therefore, there are still many problems that need to be improved in the process of transferring the pattern on the photomask to the wafer. Summary of the Invention

[0004] This disclosure provides a photomask pattern, the photomask pattern comprising:

[0005] A main graphic array, comprising a plurality of main graphics arranged along a first direction and a second direction, the main graphic array comprising at least a first graphic array located at the edge of the main graphic array, the first graphic array comprising a reference main graphic and a secondary reference main graphic, the reference main graphic being located at the outermost edge of the main graphic array, the secondary reference main graphic being located at the second outermost edge of the main graphic array, wherein the first direction and the second direction are parallel to the surface of the main graphics and intersect each other, and the edge of the main graphic array is the edge of the main graphic array in the first direction and / or the second direction;

[0006] A preset graphic array, located on at least one side of the first graphic array and comprising multiple preset graphics, wherein, in a preset direction, the size of the preset graphics is smaller than the size of the reference main graphic, the sum of the distance between two adjacent preset graphics and the size of the preset graphics is a first pitch, the sum of the distance between the reference main graphic and the secondary reference main graphic and the size of the reference main graphic is a second pitch, and the first pitch is smaller than the second pitch;

[0007] The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing between the preset graphic array and the first graphic array is smaller than the second pitch in the same direction.

[0008] In some embodiments, the ratio of the size of the preset graphic to the size of the reference main graphic has a first range, the ratio of the first pitch to the second pitch has a second range, the first range and the second range are the same, and both the first range and the second range are between 1 / 5 and 1 / 3.

[0009] In some embodiments, the ratio of the spacing between the preset graphic array and the first graphic array to the second pitch is between 1 / 5 and 1 / 3.

[0010] In some embodiments, the boundary of the reference main graphic adjacent to the preset graphic array is defined as a first boundary; the range of the number of columns of the preset graphics arranged in the preset graphic array in a direction extending parallel to the first boundary satisfies one of the following conditions:

[0011] When the size of the reference master pattern is less than 0.5 times the exposure wavelength in the exposure process, the number of columns ranges from 5 to 6.

[0012] When the size of the reference master pattern is 0.5 to 1 times the exposure wavelength in the exposure process, the number of columns ranges from 3 to 4.

[0013] When the size of the reference master pattern is greater than 1 times the exposure wavelength in the exposure process, the number of columns ranges from 1 to 2.

[0014] In some embodiments, the main graphic is uniformly arranged in the main graphic array; or...

[0015] The arrangement density of the main graphics gradually increases or decreases in the direction from the center of the main graphic array to its edge.

[0016] In some embodiments, the dimensions of each of the preset graphics are equal; and / or

[0017] In a direction extending parallel to the first boundary, the number of columns of the preset graphics is multiple, and in a direction extending perpendicular to the first boundary, the spacing between two adjacent preset graphics is equal; and / or

[0018] In a direction extending parallel to the first boundary, the spacing between two adjacent preset patterns is equal.

[0019] In some embodiments, the main graphic and the preset graphic have the same shape.

[0020] In some embodiments, the size of the preset pattern is larger than the size of the sub-resolution pattern in the photolithography process.

[0021] This disclosure also provides a mask structure, which includes the mask pattern described in any of the above embodiments.

[0022] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0023] A substrate is provided, on which a material layer to be etched is formed, and a first mask layer and a second mask layer are sequentially formed on the material layer to be etched;

[0024] An exposure process is performed on the second mask layer using the mask structure described in any of the above embodiments to form an initial first pattern and an initial second pattern on the second mask layer that expose the top of the first mask layer. The initial first pattern is the pattern obtained by transferring the main pattern to the second mask layer, and the initial second pattern is the pattern obtained by transferring the preset pattern to the second mask layer.

[0025] Along the thickness direction of the material layer to be etched, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer.

[0026] The first etched mask layer is used as a mask to etch the material layer to be etched, so as to transfer the first pattern to the material layer to be etched to form a first structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, the second pattern is not transferred to the material layer to be etched, or the second pattern is transferred to the material layer to be etched to form a second structure, and the second structure does not penetrate the material layer to be etched.

[0027] In some embodiments, the preparation method further includes: forming a filling material layer in the first structure, wherein,

[0028] When the filler material layer is a conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; including:

[0029] The first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, while the second pattern penetrates a portion of the first mask layer and does not expose the top of the material layer to be etched.

[0030] Using the etched first mask layer as a mask, the material layer to be etched is etched to transfer the first pattern into the material layer to be etched, forming a first structure, including:

[0031] The first mask layer after etching is used as a mask to etch the material layer to be etched, so as to transfer the first pattern to the material layer to be etched to form a first structure. The first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred to the material layer to be etched.

[0032] In some embodiments, the preparation method further includes: forming a filling material layer in the first structure, wherein,

[0033] When the filler material layer is a non-conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; including:

[0034] The first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates the first mask layer and exposes the top of the material layer to be etched.

[0035] Using the etched first mask layer as a mask, the material layer to be etched is etched to transfer the first pattern into the material layer to be etched, forming a first structure, including:

[0036] The first etched mask layer is used as a mask to etch the material layer to be etched, so as to transfer the first pattern to the material layer to be etched to form a first structure, and transfer the second pattern to the material to be etched to form a second structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second structure does not penetrate the material layer to be etched.

[0037] In some embodiments, after forming the first structure, the preparation method further includes:

[0038] A conductive material layer is formed in the first structure to form a conductive structure.

[0039] In some embodiments, after forming the first structure, the preparation method further includes:

[0040] A non-conductive material layer is formed in the first structure to form a non-conductive structure.

[0041] In some embodiments, in the step of etching the material layer to be etched using the etched first mask layer as a mask, the etching selectivity ratio between the etched first mask layer and the material layer to be etched is in the range of 1:(5-10).

[0042] The mask pattern provided in this embodiment includes: a main pattern array, the main pattern array comprising a plurality of main patterns arranged along a first direction and a second direction, the main pattern array including at least a first pattern array located at the edge of the main pattern array, the first pattern array including a reference main pattern and a secondary reference main pattern, the reference main pattern being located at the outermost edge of the main pattern array, the secondary reference main pattern being located at the secondary outermost edge of the main pattern array, wherein the first direction and the second direction are parallel to the surface of the main pattern and intersect each other, and the edge of the main pattern array is the edge of the main pattern array in the first direction and / or the second direction; a preset pattern array. The preset graphic array is located on at least one side of the first graphic array and includes multiple preset graphics. In a preset direction, the size of each preset graphic is smaller than the size of the reference main graphic. The sum of the distance between two adjacent preset graphics and the size of the preset graphic is a first pitch. The sum of the distance between the reference main graphic and the secondary reference main graphic and the size of the reference main graphic is a second pitch. The first pitch is smaller than the second pitch. The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the distance between the preset graphic array and the first graphic array is smaller than the second pitch in the same direction. Thus, in this embodiment of the present disclosure, by adding a preset pattern array to the mask pattern, and by designing multiple aspects based on the size and pitch information of the preset pattern located in the preset pattern array, as well as the spacing between the preset pattern array and the first pattern array being less than the second pitch in the same direction, the light intensity distribution of the exposure light source at the edge position of the main pattern array can be effectively increased. This can improve the optical correction effect of the mask pattern after optical correction operations, reduce the occurrence of pattern distortion at the edge position, and improve the lithography imaging quality. This can help ensure that the semiconductor structure obtained after exposure, development, etching and other processes has a significantly higher degree of matching with the main pattern, whether in the middle region or the edge region.

[0043] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of a mask structure provided in an embodiment of the present disclosure;

[0046] Figure 2 This is a schematic diagram of another mask structure provided in an embodiment of the present disclosure;

[0047] Figure 3 This is a partial structural schematic diagram of the mask structure provided in an embodiment of the present disclosure;

[0048] Figure 4 A flowchart illustrating the method for fabricating the semiconductor structure provided in this disclosure;

[0049] Figures 5 to 10 This is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; wherein, Figure 5 This is a three-dimensional structural diagram of a semiconductor structure during its fabrication process. Figure 6 Figure (1) in the middle and Figure 9 Figure (1) is a partial structural diagram of the photomask. Figure 6 Figure (2) in the middle and Figure 9 Figure (2) in the figure is a schematic diagram of the semiconductor structure during the fabrication process;

[0050] Figures 11 to 15 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure; wherein, Figure 11 This is a three-dimensional structural diagram of a semiconductor structure during its fabrication process. Figure 12 Figure (1) in the middle and Figure 14 Figure (1) is a partial structural diagram of the photomask. Figure 12 Figure (2) in the middle and Figure 14 Figure (2) in the figure is a schematic diagram of the semiconductor structure during the fabrication process. Detailed Implementation

[0051] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0053] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] As process nodes continue to shrink, the requirements for lithographic resolution and pattern edge precision in semiconductor structures are becoming increasingly stringent. However, during semiconductor fabrication, the pattern density changes at the edges of the pattern array compared to the central region, easily leading to optical proximity effect (OPE) and pattern distortion. In many cases, even adding sub-resolution patterns does not completely resolve the edge distortion problem.

[0058] Based on this, the technical solution of the present disclosure embodiment is proposed as follows:

[0059] This disclosure provides a photomask pattern, which includes:

[0060] A main graphic array, comprising a plurality of main graphics arranged along a first direction and a second direction, the main graphic array comprising at least a first graphic array located at the edge of the main graphic array, the first graphic array comprising a reference main graphic and a secondary reference main graphic, the reference main graphic being located at the outermost edge of the main graphic array, and the secondary reference main graphic being located at the secondary outermost edge of the main graphic array, wherein the first direction and the second direction are parallel to the surface of the main graphic and intersect each other, and the edge of the main graphic array is the edge of the main graphic array in the first direction and / or the second direction;

[0061] A preset graphic array is located on at least one side of the first graphic array and includes multiple preset graphics. In a preset direction, the size of the preset graphics is smaller than the size of the reference main graphic. The sum of the distance between two adjacent preset graphics and the size of the preset graphics is the first pitch. The sum of the distance between the reference main graphic and the secondary reference main graphic and the size of the reference main graphic is the second pitch. The first pitch is smaller than the second pitch.

[0062] The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing between the preset graphic array and the first graphic array is less than the second pitch in the same direction.

[0063] Thus, in this embodiment of the present disclosure, by adding a preset pattern array to the mask pattern, and by designing multiple aspects based on the size and pitch information of the preset pattern located in the preset pattern array, as well as the spacing between the preset pattern array and the first pattern array being less than the second pitch in the same direction, the light intensity distribution of the exposure light source at the edge position of the main pattern array can be effectively increased. This can improve the optical correction effect of the mask pattern after optical correction operations, reduce the occurrence of pattern distortion at the edge position, and improve the lithography imaging quality. This can help ensure that the semiconductor structure obtained after exposure, development, etching and other processes has a significantly higher degree of matching with the main pattern, whether in the middle region or the edge region.

[0064] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0065] Figure 1 This is a schematic diagram of a mask structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another mask structure provided in an embodiment of the present disclosure; Figure 3 This is a partial structural schematic diagram of the mask structure provided in an embodiment of this disclosure.

[0066] The mask pattern provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0067] like Figure 1 and Figure 2 As shown, the mask pattern Y includes:

[0068] The main graphic array 10 includes a plurality of main graphics 11 arranged along a first direction and a second direction. The main graphic array 10 includes at least a first graphic array 12 located at the edge of the main graphic array 10. The first graphic array 12 includes a reference main graphic A1 and a secondary reference main graphic A2. The reference main graphic A1 is located at the outermost edge of the edge of the main graphic array 10, and the secondary reference main graphic A2 is located at the secondary outer edge of the edge of the main graphic array 10. The first direction and the second direction are parallel to the surface of the main graphic 11 and intersect each other. The edge of the main graphic array 10 is the edge of the main graphic array 10 in the first direction and / or the second direction.

[0069] A preset graphic array 20 is located on at least one side of the first graphic array 12 and includes a plurality of preset graphics 21. In a preset direction, the size of the preset graphics 21 is smaller than the size of the reference main graphic A1. The sum of the distance between two adjacent preset graphics 21 and the size of the preset graphics 21 is the first pitch D1. The sum of the distance between the reference main graphic A1 and the secondary reference main graphic A2 and the size of the reference main graphic A1 is the second pitch D2. The first pitch D1 is smaller than the second pitch D2.

[0070] The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing G between the preset graphic array 20 and the first graphic array 12 is less than the second pitch D2 in the same direction.

[0071] Here, the first direction and the second direction intersect each other, which can include cases where they are perpendicular to each other, or cases where they are not perpendicular but have other angles. Specifically, the choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0072] In some embodiments, the main graphic 11 is evenly arranged in the main graphic array 10; or...

[0073] In the direction from the center of the main pattern array 10 to the edge of the main pattern array 10, the arrangement density of the main pattern 11 gradually increases or decreases.

[0074] In this embodiment of the disclosure, the arrangement of the main graphic 11 located next to the preset graphic array 20 can be divided into the following cases:

[0075] One type is where the main pattern 11 can be a repeating arrangement of unit patterns, and within the range of the main pattern array 10, there is only one arrangement density. At the same time, in the area surrounding the main pattern array 10 (which can be understood as the area starting from the edge point of the main pattern array 10, and the size from the edge point is 5 to 10 times the size of the main pattern 11 in the same direction), there are no other patterns corresponding to the functional structures in the semiconductor structure set.

[0076] Another method is to gradually increase or decrease the arrangement density of the main graphics 11 in the direction from the center of the main graphics array 10 to the edge of the main graphics array 10, while there is still an area around which a preset graphics array can be set.

[0077] In some specific embodiments, regarding the center of the main pattern array 10 pointing to the edge of the main pattern array 10, the range of increasing or decreasing the arrangement density of the main pattern 11 can be greater than 0% and less than or equal to 90%, for example, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc.

[0078] In other words, in this embodiment of the disclosure, the mask pattern Y does not impose specific restrictions on the pattern density in the area where the main pattern array 10 is located, and the main patterns 11 with various density arrangements can be applied to the mask pattern Y provided in this embodiment of the disclosure.

[0079] In some embodiments, such as Figure 1 As shown, the preset graphic array 20 can be located on one side of the edge of the main graphic array 10. The preset graphic array 20 includes multiple columns R arranged along a first direction, and each column R includes multiple preset graphics 21 arranged along a second direction.

[0080] At this point, the understanding of dimensions, pitches, and spacing between the two graphic arrays related to the preset graphic 21, the reference main graphic A1, and the secondary reference main graphic A2 in the preset direction can be further explained as follows: In both the first and second directions, the size of the preset graphic 21 is smaller than the size of the reference main graphic A1 in the same direction; and in the first direction, the sum of the spacing between two adjacent preset graphics 21 and the size of the preset graphic 21 is the first pitch D1, and the sum of the spacing between the reference main graphic A1 and the secondary reference main graphic A2 and the size of the reference main graphic A1 is the second pitch D2. In the first direction, the first pitch D1 is smaller than the second pitch D2, and in the first direction, the spacing G between the preset graphic array 20 and the first graphic array 12 is smaller than the second pitch D2 in the same direction.

[0081] Continue to refer to Figure 1 In some cases, the sum of the distance between two adjacent preset graphics 21 and the size of the preset graphics 21 in the second direction can also be called the first pitch D1. At the same time, the sum of the distance between two adjacent reference main graphics A1 in the second direction and the size of the reference main graphics A1 can also be called the second pitch D2. In the second direction, the first pitch D1 is smaller than the second pitch D2.

[0082] However, this is not the only one; in other embodiments, such as Figure 2 As shown, the preset graphic array 20 can also be located on both sides of the main graphic array 10. In this embodiment, the first graphic array 12 may further include a first sub-graphic array 121 located at the edge of the main graphic array 10 along a first direction, and a second sub-graphic array 122 located at the edge of the main graphic array 10 along a second direction. The preset graphic array 20 includes a first preset graphic array 201 located at the edge of the first sub-graphic array 121 along the first direction, and a second preset graphic array 202 located at the edge of the second sub-graphic array 122 along the second direction.

[0083] exist Figure 2In the illustrated embodiment, the preset graphic array 20 may be located on both sides of the edge of the main graphic array 10. The preset graphic array 20 may include multiple columns R. Column R may further include multiple first columns R1 arranged along a first direction and multiple second columns R2 arranged along a second direction, and each column R includes multiple preset graphics 21 arranged along the first direction or the second direction.

[0084] At this point, the understanding of dimensions, pitches, and spacing between the two graphic arrays related to the preset graphic 21, the reference main graphic A1, and the secondary reference main graphic A2 in the preset direction can be further interpreted as follows: Information regarding the dimensions, spacing, and pitch between the first sub-graphic array 121 and the first preset graphic array 201 can be referenced from... Figure 1 The relevant details will not be elaborated upon here.

[0085] Furthermore, regarding the understanding of dimensions, pitches, and spacing between two graphic arrays related to the preset graphic 21, the reference main graphic A1, and the secondary reference main graphic A2 in the preset direction, it can be further explained as follows: In either the first or second direction, the size of the preset graphic 21 is smaller than the size of the reference main graphic A1; and in the second direction, the sum of the spacing between two adjacent preset graphics 21 and the size of the preset graphic 21 is the first pitch D1, and the sum of the spacing between the reference main graphic A1 and the secondary reference main graphic A2 and the size of the reference main graphic A1 is the second pitch D2. In the second direction, the first pitch D1 is smaller than the second pitch D2, and in the second direction, the spacing G between the second preset graphic array 202 and the second sub-graphic array 122 is smaller than the second pitch D2 in the same direction.

[0086] Continue to refer to Figure 2 In some cases, in the second preset pattern array 202, the sum of the distance between two adjacent preset patterns 21 and the size of the preset pattern 21 in the first direction can also be called the first pitch D1. At the same time, in the second sub-pattern array 122, the sum of the distance between two adjacent reference main patterns A1 in the first direction and the size of the reference main pattern A1 can also be called the second pitch D2. In the first direction, the first pitch D1 is smaller than the second pitch D2.

[0087] In some embodiments, the shape of the main graphic 11 may include, but is not limited to, at least one or a combination of circles, ellipses, polygons, or irregular shapes. When the shape of the main graphic 11 includes a polygon, the shape of the main graphic 11 may further include triangles, quadrilaterals, rectangles (e.g.,...). Figure 3The shape of the main graphic 11 can be one of the following: a strip shape, a pentagon, or even a polygon with more sides. Furthermore, the shape of the main graphic 11 can also be a combination of any two or more of the above-mentioned shapes. No specific limitation is made here, and the shape can be flexibly selected according to the actual situation.

[0088] It should be noted that, although in Figure 1 The diagram shows that the preset graphics array 20 can be located on one side of the main graphics array 10, and in Figure 2 The illustration shows a scenario where the preset graphic array 20 can be located on both sides of the main graphic array 10. This is merely an illustrative example and is not intended to limit the application scenarios of this disclosure.

[0089] In some other embodiments, where the preset pattern array 20 is located on one side, the preset pattern array 20 may also be set on... Figure 2 The side where the second sub-pattern array 122 is located, as shown in the diagram, or the opposite side, or, as... Figure 1 The opposite side of the preset graphic array 20 shown is not specifically limited here and can be flexibly set according to the actual situation.

[0090] Furthermore, in some embodiments where the preset graphic array 20 is located on both sides, the preset graphic array 20 can also be configured to be adjacent to each other or opposite each other. No specific limitation is made here; the configuration can be flexibly selected according to the actual situation.

[0091] Furthermore, the preset graphic array 20 can also be set on more sides of the main graphic array 10, such as three or four sides. Depending on the boundary shape of the main graphic array 10, the preset graphic array 20 can be set to correspond to the boundary of the main graphic array 10, or it can be flexibly set on the side of the boundary that is prone to graphic distortion or other arbitrary areas according to the actual process.

[0092] Continue to refer to Figure 1 and Figure 2 In some embodiments, the main graphic 11 and the preset graphic 21 may have the same shape.

[0093] In some specific embodiments, the specific graphic of the preset graphic 21 can be set according to the shape of the main graphic 11, and in particular, it can be set according to the setting of the main graphic 11 located at the edge of the main graphic array 10, that is, the reference main graphic A1. For example, the specific shape, size and other settings of the graphic can be referenced to the setting of the reference main graphic A1 located at the edge of the main graphic array 10, while the settings related to spacing and other distances can be specifically set by referring to the settings between the reference main graphic A1 and the secondary reference main graphic A2.

[0094] Continue to refer to Figure 1 and Figure 2 As shown, in any of the above embodiments, the ratio of the size of the preset graphic 21 to the size of the reference main graphic A1 has a first range, and the ratio of the first pitch D1 to the second pitch D2 has a second range. The first range and the second range are the same, and both the first range and the second range are between 1 / 5 and 1 / 3 (including the endpoint values), such as 0.2, 0.21, 0.22, 0.23, 0.25, 0.27, 0.29, 0.3, 0.31, 0.32, 0.33, etc.

[0095] In some embodiments, the ratio of the spacing G between the preset pattern array 20 and the first pattern array 12 to the second pitch D2 is between 1 / 5 and 1 / 3 (including the endpoint values), for example, 0.2, 0.21, 0.22, 0.23, 0.25, 0.27, 0.29, 0.3, 0.31, 0.32, 0.33, etc.

[0096] It can be seen that, in this embodiment, the settings of relevant information in the preset graphic array 20 are strongly correlated with the settings of relevant information in the main graphic array 10. Specifically, this can be manifested in the following aspects:

[0097] (1) The shape of the preset graphic 21 can be set to be the same as the shape of the main graphic 11.

[0098] (2) The size of the preset graphic 21 is smaller than the size of the main graphic 11 in the same direction, the first pitch D1 is smaller than the second pitch D2, and the spacing is smaller than the second pitch.

[0099] (3) The ratio of the size of the preset graphic 21 in the preset graphic array 20 to the size of the reference main graphic A1 in the first graphic array 12 is the same as the ratio between the first pitch D1 and the second pitch D2.

[0100] (4) The ratio range of the distance G between the preset graphic array 20 and the first graphic array 12 to the second pitch D2 can also be the same as the aforementioned ratio range.

[0101] Thus, it can be seen that in this embodiment, the settings of information in the preset graphic array 20 and the settings of information in the main graphic array 10 are highly dependent and related. They complement each other and work together to improve the graphic distortion at the edge of the main graphic array 10. Furthermore, since the information settings in the preset graphic array 20 are set based on the settings of the main graphic 11 in this embodiment, the information of the preset graphic 21 added in this embodiment has a high degree of compatibility with the information of the main graphic array 10, especially the first graphic array 12. This can effectively and specifically improve the edge graphic distortion of the main graphic array 10 to a large extent.

[0102] Continue to refer to Figure 1 and Figure 2 In some embodiments, the boundary of the reference main graphic A1 adjacent to the preset graphic array 20 is defined as the first boundary W1; the range of column R of the preset graphic 21 arranged in the preset graphic array 20 in a direction extending parallel to the first boundary W1 satisfies one of the following conditions:

[0103] When the size of the reference master pattern A1 is less than 0.5 times the exposure wavelength in the exposure process (such as the exposure wavelength of the exposure light source, the same below), the value range of column R is between 5 and 6 (including the endpoint value), for example 5 or 6.

[0104] When the size of the reference master pattern A1 is 0.5 to 1 times the exposure wavelength in the exposure process, the value of column R is between 3 and 4 (including the endpoint value), for example, 3 or 4;

[0105] When the size of the reference master pattern A1 is greater than 1 times the exposure wavelength in the exposure process, the value of column R is between 1 and 2 (including the endpoint value), for example, 1 or 2.

[0106] In some embodiments, such as Figure 2 As shown, the first boundary W1 may further include a first sub-boundary W11 and a second sub-boundary W12. When the size of the reference main pattern A1 is set based on the multiple of the exposure wavelength in the exposure process to determine the number of columns R, the specific number of columns R can be set according to the side position of the preset pattern array 20 on the main pattern array 10, by selecting the extension direction of the corresponding sub-boundary and setting the specific value of the corresponding column R.

[0107] In some embodiments, the dimensions of each preset graphic 21 are equal in the same direction; and / or

[0108] In the direction extending parallel to the first boundary W1, there are multiple columns R of preset patterns 21 extending in the same direction, and in the direction extending perpendicular to the first boundary W1, the spacing between two adjacent preset patterns 21 is equal; and / or

[0109] In the direction extending parallel to the first boundary W1, the spacing between two adjacent preset patterns 21 is equal.

[0110] In some embodiments, the size of the preset pattern 21 is larger than the size of the sub-resolution pattern in the photolithography process.

[0111] It is understandable that when the size of a graphic is within the size range of a sub-resolution graphic, the graphic will not be transferred to the semiconductor structure in the actual photolithography process. However, in this embodiment of the present disclosure, the size of the preset graphic 21 is set to be larger than the size of the sub-resolution graphic in the photolithography process. This helps to obtain a graphic structure that is transferred or not transferred in actual operation by using the parameter settings in the process in combination with the structural requirements, which has high flexibility.

[0112] As can be seen, in this embodiment of the present disclosure, by limiting the size, shape, density, and arrangement of the preset pattern 21, and by setting information related to the main pattern 11 in terms of size, pitch, and array spacing, the mask pattern Y can be transferred to the mask layer (e.g., in subsequent photolithography processes) through a photolithography process. Figure 5 The second mask layer 32 is applied to the hard mask layer (e.g., in subsequent etching processes) and transferred to the hard mask layer (e.g., in subsequent etching processes). Figure 5 On the first mask layer 31 or the material layer L to be etched, the fidelity of the main pattern 11 after pattern transfer is improved.

[0113] like Figure 1 and Figure 2 As shown, this disclosure also provides a mask structure M, which includes the mask pattern Y of any of the above embodiments.

[0114] In some embodiments, when obtaining the mask structure M, an optical correction operation (OPC), i.e., optical proximity effect simulation optimization, can be performed based on the mask pattern Y provided in any of the above embodiments. During the execution of this operation, the main pattern 11 can be used as the target reference for optimization.

[0115] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the preparation method includes the following steps:

[0116] Step S101: Provide a substrate, form a material layer to be etched on the substrate, and sequentially form a first mask layer and a second mask layer on the material layer to be etched;

[0117] Step S102: Perform an exposure process on the second mask layer using the mask structure of any of the above embodiments to form an initial first pattern and an initial second pattern that expose the top of the first mask layer on the second mask layer. The initial first pattern is a pattern obtained by transferring the main pattern to the second mask layer, and the initial second pattern is a pattern obtained by transferring a preset pattern to the second mask layer.

[0118] Step S103: Along the thickness direction of the material layer to be etched, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least part of the first mask layer.

[0119] Step S104: Using the etched first mask layer as a mask, etch the material layer to be etched to transfer the first pattern to the material layer to be etched to form a first structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, the second pattern is not transferred to the material layer to be etched, or the second pattern is transferred to the material layer to be etched to form a second structure, and the second structure does not penetrate the material layer to be etched.

[0120] It should be understood that, although Figure 4 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0121] The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0122] First, execute step S101, as follows: Figure 5 and Figure 11 As shown, a substrate 30 is provided, a material layer L to be etched is formed on the substrate 30, and a first mask layer 31 and a second mask layer 32 are sequentially formed on the material layer L to be etched.

[0123] Here, substrate 30 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 30 is a silicon substrate.

[0124] like Figure 5 and Figure 6 ,and Figure 11 and Figure 12 As shown, in some embodiments, the preparation method further includes the following steps before forming the material layer L to be etched:

[0125] The preset material layer 35 and the functional layer 33 are formed sequentially;

[0126] A preset structure 34 is formed, and the preset structure 34 is located on the functional layer 33;

[0127] After forming the preset structure 34, a material layer L to be etched is formed, including:

[0128] A material layer L to be etched is formed, which covers the surface of the preset structure 34.

[0129] In some embodiments, the material of the material layer L to be etched may include, but is not limited to, an oxide material layer, such as silicon oxide.

[0130] In some embodiments, the first mask layer 31 can be divided into two sub-layers from bottom to top. The material of the sub-layer adjacent to the substrate 30 can be, but is not limited to, a carbon layer (SOC). The material of the sub-layer above the carbon layer can be, but is not limited to, an anti-reflective layer (ARC) material, such as an oxide nitride layer, specifically a silicon nitride oxynitride layer (SiON). The material of the second mask layer 32 can be, but is not limited to, a photoresist layer.

[0131] In some embodiments, the thickness of the first mask layer 31 can be determined comprehensively based on the parameters of the structure to be obtained in the subsequent etching process and the etching conditions required by the main pattern 11, while the preset pattern 21 is generally not used as a reference factor for determining the thickness of the first mask layer 31. In this way, it can be ensured that the first mask layer 31 has sufficient etching resistance in the process of obtaining the structure corresponding to the main pattern 11.

[0132] In some embodiments, the preset structure 34 may include, but is not limited to, a capacitor structure, and a functional structure may be formed in the functional layer 33. The functional structure may include, but is not limited to, a transistor structure.

[0133] In some embodiments, the material of the preset material layer 35 includes, but is not limited to, tungsten metal or titanium nitride.

[0134] Next, proceed to step S102, as follows: Figure 6 and Figure 12 As shown, the mask structure M of any of the above embodiments is used to perform an exposure process on the second mask layer 32 to form an initial first pattern P1a and an initial second pattern P2a on the second mask layer 32 that expose the top of the first mask layer 31. The initial first pattern P1a is the pattern obtained by transferring the main pattern 11 to the second mask layer 32, and the initial second pattern P2a is the pattern obtained by transferring the preset pattern 21 to the second mask layer 32.

[0135] In this embodiment of the disclosure, the mask pattern Y included in the mask structure M includes: a main pattern array 10 and a preset pattern array 20. The main pattern array 10 includes a plurality of main patterns 11 arranged along a first direction and a second direction. The main pattern array 10 includes at least a first pattern array 12 located at the edge of the main pattern array 10. The first pattern array 12 further includes a reference main pattern A1 located on the outermost side and a secondary reference main pattern A2 located on the second outermost side. The preset pattern array 20 is located on at least one side of the first pattern array 12 and includes a plurality of preset patterns 21. In the preset direction, the size of the preset pattern 21 is smaller than the size of the reference main pattern A1. The sum of the distance between two adjacent preset patterns 21 and the size of the preset pattern 21 is a first pitch D1. The sum of the distance between the reference main pattern A1 and the secondary reference main pattern A2 and the size of the reference main pattern A1 is a second pitch D2. The first pitch D1 is smaller than the second pitch D2. The distance G between the preset pattern array 20 and the first pattern array 12 is smaller than the second pitch D2 in the same direction.

[0136] Thus, since the mask pattern Y contained in the mask structure M includes both the main pattern 11 for forming the desired target structure and the preset pattern array 20 with multiple preset patterns 21, and is constrained by the size relationship between the first pitch and the second pitch, as well as the size relationship between the second pitch and the spacing, the light intensity distribution of the main pattern 11 located at the edge during the exposure process can be effectively enhanced, the optical correction effect of the mask pattern Y after optical correction operations can be improved, the occurrence of pattern distortion can be reduced, and the lithography imaging quality can be improved. This helps to ensure that after the semiconductor structure has undergone exposure, development, etching, and other processes, it can also be understood that after step S104, in subsequent... Figure 9 or Figure 14 In this process, the first structure S1 obtained, whether in the middle region or the edge region, can have a significantly higher degree of matching with the main graphic 11.

[0137] Then, proceed with step S103, as follows: Figure 7 and Figure 13 As shown, along the thickness direction of the material layer L to be etched, the first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates at least part of the first mask layer 31.

[0138] In some embodiments, the second mask layer 32 and the first mask layer 31 may have a high etching selectivity ratio. For example, a ratio of 1:(5-10) (including endpoint values), such as 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10.

[0139] Here, the etching selectivity refers to the ratio of the etching amount of the material to be etched (first mask layer 31) to the etching amount of the etching mask material (second mask layer 32). It serves as an important reference for evaluating etching conditions (such as etching gas and flow rate) and the selection of matching materials (photoresist / hard mask) and thickness settings in the pattern conversion process. Simply put, as shown in the diagram, the material to be etched is a carbon layer, and the etching mask material (i.e., the pattern film layer) is a photoresist layer. During the process of etching the pattern from the photoresist layer onto the carbon layer, the thickness of the photoresist layer (second mask layer 32) is also consumed. Finally, after the carbon layer etching is completed, the photoresist layer thickness will be sacrificed.

[0140] In this embodiment of the present disclosure, when the second mask layer 32 and the first mask layer 31 can have a high etching selectivity ratio, the formation in this step... Figure 6 and Figure 12 During the process of the initial first pattern P1a and the initial second pattern P2a shown, the pattern is transferred from the second mask layer 32 to the first mask layer 31. Before the transfer process ends, the second mask layer 32 will not disappear due to natural consumption, so as to ensure the smooth progress of the pattern transfer process.

[0141] In some cases, the etching selectivity can be determined using a simplified method, such as the ratio of the thickness of the etching mask material to the thickness of the material to be etched. However, this is not the only possibility. In some situations, a more accurate figure can be obtained by comprehensively considering the thicknesses of the etching mask material and the material to be etched, along with etching conditions and other factors that may affect the etching rate. The specific method used can be chosen based on the actual situation, and no specific limitations are imposed here.

[0142] In some embodiments, the size of the preset pattern 21 is larger than the size of the sub-resolution pattern in the photolithography process.

[0143] It is understandable that when the size of a graphic is within the size range of a sub-resolution graphic, the graphic will not be transferred to the semiconductor structure in the actual photolithography process. However, in this embodiment of the present disclosure, the size of the preset graphic 21 is set to be larger than the size of the sub-resolution graphic in the photolithography process. This helps to obtain a graphic structure that is transferred or not transferred in actual operation by using the parameter settings in the process in combination with the structural requirements, which has high flexibility.

[0144] In some embodiments, when the material layer L to be etched on the substrate 30 is a dielectric layer, serving only as an insulating layer to isolate the circuit, and its thickness is in the range of 100–200 nm, the preset pattern 21 is generally selected to stop at the hard mask layer (first mask layer 31) on it, without etching to the dielectric layer. If the material layer L to be etched is a dielectric layer, and as Figure 5 or Figure 11 When the preset structure 34 is wrapped in the dielectric layer, and the radial depth of the wrapped structure is more than 500nm, and the top of the wrapped preset structure 34 is still more than 300nm away from the top of the dielectric layer, the preset pattern 21 can be etched into the dielectric layer, resulting in an incomplete etching phenomenon, that is, it does not completely penetrate the material layer L to be etched, and remains on this layer.

[0145] In some cases, the choice of whether to etch the second pattern P2 into the material layer L can be based on the type of material that fills the layer after the etching step is completed. For example:

[0146] In some embodiments, such as Figures 7 to 10 As shown, after performing the subsequent step S104, the preparation method further includes: forming a filling material layer 36 in the first structure S1, wherein,

[0147] When the filling material layer 36 is a conductive material, the first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates at least a portion of the first mask layer 31; including:

[0148] The first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, while the second pattern P2 penetrates part of the first mask layer 31 and does not expose the top of the material layer L to be etched.

[0149] Using the etched first mask layer 31 as a mask, the material layer L to be etched is etched to transfer the first pattern P1 into the material layer L to be etched, forming the first structure S1, including:

[0150] The first mask layer 31 after etching is used as a mask to etch the material layer L to be etched, so as to transfer the first pattern P1 to the material layer L to be etched to form the first structure S1. The first structure S1 penetrates the material layer L to be etched and exposes the top of the functional layer 33 on the substrate 30, and the second pattern P2 is not transferred to the material layer L to be etched.

[0151] In this embodiment, when the material filling the first structure S1 is a conductive material, the practice of not transferring the second pattern P2 to the material layer L to be etched helps to improve the breakdown resistance of the structure based on the conductive material, and improve the electrical performance and reliability of the finally obtained semiconductor structure.

[0152] In other embodiments, such as Figures 13 to 15 As shown, the preparation method further includes: forming a filling material layer 36 in the first structure S1, wherein,

[0153] When the filling material layer 36 is a non-conductive material, the first mask layer 31 is etched using the exposed second mask layer 32 as a mask to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates at least a portion of the first mask layer 31; including:

[0154] Using the exposed second mask layer 32 as a mask, the first mask layer 31 is etched to form a first pattern P1 and a second pattern P2. The first pattern P1 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched, and the second pattern P2 penetrates the first mask layer 31 and exposes the top of the material layer L to be etched.

[0155] Using the etched first mask layer 31 as a mask, the material layer L to be etched is etched to transfer the first pattern P1 into the material layer L to be etched, forming the first structure S1, including:

[0156] Using the etched first mask layer 31 as a mask, the material layer L to be etched is etched to transfer the first pattern P1 into the material layer L to form the first structure S1, and the second pattern P2 into the material to be etched to form the second structure S2; wherein, the first structure S1 penetrates the material layer L to be etched and exposes the top of the substrate 30, and the second structure S2 does not penetrate the material layer L to be etched, that is, the second structure S2 does not expose the top of the functional layer 33 located on the substrate 30.

[0157] In this embodiment, when the material filling the first structure S1 is a non-conductive material, the practice of transferring the second pattern P2 to the material layer L to be etched makes the pattern distribution density of the first structure S1 at the edge position closer to the pattern distribution density of the first structure S1 at the middle position, which helps to improve the filling performance when the filling material layer 36 is formed and improve the integrity of the semiconductor structure.

[0158] Finally, proceed with step S104, as follows: Figure 8 and Figure 9 ,as well as Figure 14 As shown, the first mask layer 31 after etching is used as a mask to etch the material layer L to be etched, so as to transfer the first pattern P1 to the material layer L to be etched to form the first structure S1; wherein, the first structure S1 penetrates the material layer L to be etched and exposes the top of the substrate 30, the second pattern P2 is not transferred to the material layer L to be etched, or the second pattern P2 is transferred to the material layer L to be etched to form the second structure S2, and the second structure S2 does not penetrate the material layer L to be etched.

[0159] In some embodiments, such as Figure 8 As shown, the thickness of the first mask layer 31 is reduced due to natural consumption during the etching process, and in this embodiment, the second pattern P2 in the first mask layer 31 is not transferred to the material layer L to be etched.

[0160] In other embodiments, such as Figure 14 As shown, the thickness of the first mask layer 31 is reduced due to natural consumption during the etching process, and in this embodiment, the second pattern P2 in the first mask layer 31 is transferred to the material layer L to be etched.

[0161] In some embodiments, Figure 7 and Figure 8 In the embodiment shown, in order to prevent the second pattern P2 from being transferred to the material layer L during the subsequent etching process, in the step of etching the material layer L using the etched first mask layer 31 as a mask, the etching selectivity ratio between the first mask layer 31 remaining at the bottom of the second pattern P2 and the material layer L is in the range of 1:(5-10) (including the endpoint value), such as 1:5, 1:6, 1:7, 1:8, 1:9 or 1:10, etc.

[0162] In this way, by controlling the etching selectivity ratio, a structure in which the second pattern P2 is not transferred to the material layer L to be etched can be obtained, so as to prevent the structure obtained by the conductive material subsequently filled in the first structure S1 from being at risk of breakdown, thereby improving the reliability of the semiconductor structure.

[0163] In some embodiments, such as Figure 10As shown, after forming the first structure S1, the preparation method further includes:

[0164] A filling material layer 36 is formed in the first structure S1. The filling material layer is a conductive material layer to form a conductive structure C.

[0165] The conductive material layer here can contain any suitable conductive material, and the conductive structure C can be used as a conductive plug.

[0166] In some embodiments, such as Figure 15 As shown, after forming the first structure S1, the preparation method further includes:

[0167] A filling material layer 36 is formed in the first structure S1. The filling material layer 36 is a non-conductive material layer to form a non-conductive structure D.

[0168] Here, the non-conductive material layer can include any suitable material, such as oxides, nitrides, or oxynitrides, etc., without specific limitations. The non-conductive structure D can be used as an insulating or insulating structure.

[0169] In any of the above embodiments, the selection of etching process and etching parameters in the etching step can be determined according to the structure to be formed corresponding to the main pattern 11, thereby ensuring that the main pattern 11 can be smoothly transferred from the second mask layer 32 to the first mask layer 31 and the material layer L to be etched.

[0170] In some embodiments, the etching process may employ at least one of reactive ion etching or deep reactive ion etching to ensure high-precision pattern transfer.

[0171] In some embodiments, after the etching process is completed, the etching parameters can be further adjusted based on the etching results to obtain the desired target structure.

[0172] In some embodiments, the conductive structure C in the semiconductor structure obtained by the preparation method of this disclosure can be a contact structure (CT), for example, a channel connecting the upper plate of the local interconnect (Metal0) metal layer and the capacitor (e.g., TCP capacitor) to the upper metal layer (e.g., Metal1, i.e., M1 layer).

[0173] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0174] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A photomask pattern, characterized in that, The mask pattern includes: A main graphic array, comprising a plurality of main graphics arranged along a first direction and a second direction, the main graphic array comprising at least a first graphic array located at the edge of the main graphic array, the first graphic array comprising a reference main graphic and a secondary reference main graphic, the reference main graphic being located at the outermost edge of the main graphic array, the secondary reference main graphic being located at the second outermost edge of the main graphic array, wherein the first direction and the second direction are parallel to the surface of the main graphics and intersect each other, and the edge of the main graphic array is the edge of the main graphic array in the first direction and / or the second direction; A preset graphic array, located on at least one side of the first graphic array and comprising multiple preset graphics, wherein, in a preset direction, the size of the preset graphics is smaller than the size of the reference main graphic, the sum of the distance between two adjacent preset graphics and the size of the preset graphics is a first pitch, the sum of the distance between the reference main graphic and the secondary reference main graphic and the size of the reference main graphic is a second pitch, and the first pitch is smaller than the second pitch; The preset direction includes at least one of the first direction and the second direction, and in the preset direction, the spacing between the preset graphic array and the first graphic array is smaller than the second pitch in the same direction.

2. The mask pattern according to claim 1, characterized in that, The ratio of the size of the preset graphic to the size of the reference main graphic has a first range, and the ratio of the first pitch to the second pitch has a second range. The first range and the second range are the same, and both the first range and the second range are between 1 / 5 and 1 / 3.

3. The mask pattern according to claim 2, characterized in that, The ratio of the spacing between the preset graphic array and the first graphic array to the second pitch ranges from 1 / 5 to 1 / 3.

4. The mask pattern according to claim 1, characterized in that, The boundary of the reference main graphic adjacent to the preset graphic array is defined as the first boundary; the number of columns of the preset graphics arranged in the preset graphic array in a direction extending parallel to the first boundary satisfies one of the following conditions: When the size of the reference master pattern is less than 0.5 times the exposure wavelength in the exposure process, the number of columns ranges from 5 to 6. When the size of the reference master pattern is 0.5 to 1 times the exposure wavelength in the exposure process, the number of columns ranges from 3 to 4. When the size of the reference master pattern is greater than 1 times the exposure wavelength in the exposure process, the number of columns ranges from 1 to 2.

5. The mask pattern according to any one of claims 1-4, characterized in that, The main graphic is evenly arranged in the main graphic array; or... The arrangement density of the main graphics gradually increases or decreases in the direction from the center of the main graphic array to its edge.

6. The mask pattern according to claim 4, characterized in that, All the preset graphics are of equal size; and / or In the direction extending parallel to the first boundary, there are multiple columns of the preset graphics, and in the direction extending perpendicular to the first boundary, the spacing between two adjacent preset graphics is equal. and / or In a direction extending parallel to the first boundary, the spacing between two adjacent preset patterns is equal.

7. The mask pattern according to any one of claims 1-4, characterized in that, The main graphic and the preset graphic have the same shape.

8. The mask pattern according to any one of claims 1-4, characterized in that, The size of the preset pattern is larger than the size of the sub-resolution pattern in the photolithography process.

9. A photomask structure, characterized in that, The mask structure includes the mask pattern as described in any one of claims 1-8.

10. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided, on which a material layer to be etched is formed, and a first mask layer and a second mask layer are sequentially formed on the material layer to be etched; An exposure process is performed on the second mask layer using the mask structure as described in claim 9 to form an initial first pattern and an initial second pattern on the second mask layer that expose the top of the first mask layer. The initial first pattern is a pattern obtained by transferring the main pattern onto the second mask layer, and the initial second pattern is a pattern obtained by transferring the preset pattern onto the second mask layer. Along the thickness direction of the material layer to be etched, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer. The first etched mask layer is used as a mask to etch the material layer to be etched, so as to transfer the first pattern to the material layer to be etched to form a first structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, the second pattern is not transferred to the material layer to be etched, or the second pattern is transferred to the material layer to be etched to form a second structure, and the second structure does not penetrate the material layer to be etched.

11. The preparation method according to claim 10, characterized in that, The preparation method further includes: forming a filling material layer in the first structure, wherein, When the filler material layer is a conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; including: The first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, while the second pattern penetrates a portion of the first mask layer and does not expose the top of the material layer to be etched. Using the etched first mask layer as a mask, the material layer to be etched is etched to transfer the first pattern into the material layer to be etched, forming a first structure, including: The first mask layer after etching is used as a mask to etch the material layer to be etched, so as to transfer the first pattern to the material layer to be etched to form a first structure. The first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second pattern is not transferred to the material layer to be etched.

12. The preparation method according to claim 10, characterized in that, The preparation method further includes: forming a filling material layer in the first structure, wherein, When the filler material layer is a non-conductive material, the first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates at least a portion of the first mask layer; including: The first mask layer is etched using the exposed second mask layer as a mask to form a first pattern and a second pattern. The first pattern penetrates the first mask layer and exposes the top of the material layer to be etched, and the second pattern penetrates the first mask layer and exposes the top of the material layer to be etched. Using the etched first mask layer as a mask, the material layer to be etched is etched to transfer the first pattern into the material layer to be etched, forming a first structure, including: The first etched mask layer is used as a mask to etch the material layer to be etched, so as to transfer the first pattern to the material layer to be etched to form a first structure, and transfer the second pattern to the material to be etched to form a second structure; wherein the first structure penetrates the material layer to be etched and exposes the top of the substrate, and the second structure does not penetrate the material layer to be etched.

13. The preparation method according to claim 11, characterized in that, After forming the first structure, the preparation method further includes: A conductive material layer is formed in the first structure to form a conductive structure.

14. The preparation method according to claim 12, characterized in that, After forming the first structure, the preparation method further includes: A non-conductive material layer is formed in the first structure to form a non-conductive structure.

15. The preparation method according to any one of claims 10-14, characterized in that, In the step of etching the material layer to be etched using the etched first mask layer as a mask, the etching selectivity ratio between the etched first mask layer and the material layer to be etched is in the range of 1:(5-10).

Images