Reconfigurable multi-mode intelligent computing circuit and computing device

Abstract

The application relates to a reconfigurable multi-mode intelligent computing circuit and a computing device, which comprises a reconfigurable adder circuit used for performing any one of the following operations under the control of a control circuit: addition, subtraction, straight-through, accumulation, comparison or cyclic comparison; a reconfigurable memory used for storing data under the control of the control circuit or performing numerical lookup under the control of the control circuit; a reconfigurable data channel comprising at least one handshake interface unit connected with the reconfigurable adder circuit and the reconfigurable memory and used for transmitting data under the control of the control circuit; and the control circuit used for controlling the reconfigurable adder circuit, the reconfigurable memory and the reconfigurable data channel according to configuration information. The circuit can effectively reduce the chip area and lower power consumption.

Description

Technical Field

[0001] This application relates to the field of digital circuit technology, and in particular to a reconfigurable multi-mode intelligent computing circuit and computing device. Background Technology

[0002] In neural network convolutional computation, after the convolution calculation is completed, post-processing calculations such as batch normalization, activation, pooling, and residual calculations are required. These calculations require separate circuit structures for each part.

[0003] In existing technologies, designing separate computational circuits for post-processing calculations such as batch normalization, activation, pooling, and residuals in neural networks results in larger chip areas and higher power consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide a reconfigurable multi-mode intelligent computing circuit and computing device that can effectively reduce chip area and power consumption.

[0005] In a first aspect, embodiments of this application provide a reconfigurable multi-mode intelligent computing circuit, comprising: a reconfigurable adder circuit, which is used to perform any of the following operations under the control of a control circuit: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison; a reconfigurable memory, which is used to store data under the control of the control circuit, or to perform numerical lookup under the control of the control circuit; a reconfigurable data path, which includes at least one handshake interface unit connected to both the reconfigurable adder circuit and the reconfigurable memory, and is used to transmit data under the control of the control circuit; and a control circuit, which is used to control the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information.

[0006] In one embodiment, the reconfigurable adder circuit includes: multiple selection circuits, an adder, a negation circuit, and a register; the selection circuits include a first selection circuit, a second selection circuit, a third selection circuit, and a fourth selection circuit; the input of the first selection circuit is connected to the output of the register and a first data input bus, respectively, and the output of the first selection circuit is connected to the input of the negation circuit, the input of the second selection circuit, and the input of the third selection circuit, respectively; the input of the second selection circuit is connected to the output of the negation circuit, the output of the first selection circuit, and the output of the register, respectively, and the output of the second selection circuit is connected to the input of the adder; the input of the third selection circuit is connected to the output of the first selection circuit, the output of the adder, and a second data input bus, and the output of the third selection circuit is connected to the input of the fourth selection circuit; the input of the fourth selection circuit is connected to the output of the adder, the output of the third selection circuit, and the second data input bus, and the output of the fourth selection circuit is connected to the input of the register.

[0007] In one embodiment, the reconfigurable multi-mode intelligent computing circuit further includes a multiplication circuit, which is connected to both the reconfigurable data path and the reconfigurable adder circuit. The reconfigurable data path includes a first handshake interface unit, a second handshake interface unit, a third handshake interface unit, a fourth handshake interface unit, a fifth handshake interface unit, and a sixth handshake interface unit. The first handshake interface unit is a one-to-many handshake interface unit, and its input terminal is used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminals of the second and third handshake interface units. The second handshake interface unit is a many-to-many handshake interface unit, and its input terminal... The first handshake interface unit is connected to the first coefficient, input data, the output of the multiplication circuit, and the output of the sixth handshake interface unit. The output of the second handshake interface unit is connected to the input of the reconfigurable adder circuit. The input of the second handshake interface unit is used to read at least one of the following data under the control of the control circuit: the first coefficient, input data, the output data of the multiplication circuit, and the output data of the sixth handshake interface unit. The third handshake interface unit is a many-to-many handshake interface unit. The input of the third handshake interface unit is connected to the second coefficient, the output of the first handshake interface unit, the output of the sixth handshake interface unit, and the output of the reconfigurable adder circuit. The output of the third handshake interface unit is connected to the input of the multiplication circuit. The input terminal of the third handshake interface unit is used to read at least one of the following data under the control of the control circuit: the second coefficient, input data, the output data of the sixth handshake interface unit, and the output data of the reconfigurable adder circuit; the fourth handshake interface unit is a many-to-one handshake interface unit, the input terminal of the fourth handshake interface unit is connected to the output terminal of both the multiplication circuit and the reconfigurable adder circuit, the output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory, and the input terminal of the fourth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the multiplication circuit and the output data of the reconfigurable adder circuit; the fifth handshake interface unit is a many-to-one handshake interface unit, the... The input terminal of the five-handshake interface unit is connected to the sixth handshake interface unit, the output terminal of the multiplication circuit, and the output terminal of the reconfigurable adder circuit. The output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The input terminal of the fifth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the sixth handshake interface unit, the output data of the multiplication circuit, and the output data of the reconfigurable adder circuit. The sixth handshake interface unit is a one-to-many handshake interface unit. The input terminal of the sixth handshake interface unit is connected to the output terminal of the reconfigurable memory. The output terminal of the sixth handshake interface unit is connected to the second handshake interface unit, the third handshake interface unit, and the fifth handshake interface unit.

[0008] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the first handshake interface unit is connected to the input terminal of the third handshake interface unit; the input terminal of the third handshake interface unit is specifically used to read input data and a second coefficient under the control of the control circuit, and the output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit, and the output terminal of the multiplication circuit is connected to the input terminal of the second handshake interface unit; the input terminal of the second handshake interface unit is specifically used to read the output data of the multiplication circuit and a first coefficient under the control of the control circuit, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform addition operations on the output data of the multiplication circuit and the first coefficient under the control of the control circuit; the input terminal of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output terminal of the fifth handshake interface unit is specifically used to output the output data of the reconfigurable adder circuit, wherein the output data of the reconfigurable adder circuit is the normalized result of the input data.

[0009] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit, and the input data is preset table data. The input terminal of the second handshake interface unit is specifically used to read a first coefficient and input data under the control of the control circuit. The first coefficient is 0. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform pass-through operations under the control of the control circuit. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the input data. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store preset table data under the control of the control circuit.

[0010] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit; the input terminal of the second handshake interface unit is specifically used to read a first coefficient and input data under the control of the control circuit, wherein the first coefficient is 0, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform addition operations on the input data and the first coefficient under the control of the control circuit; the input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, wherein the output data of the reconfigurable adder circuit is the input data, and the output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory; the reconfigurable memory is specifically used to perform numerical lookup based on the input data under the control of the control circuit, and the output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit; the input terminal of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit, and the output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, wherein the calculation result is the numerical lookup result.

[0011] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit; the output terminal of the first handshake interface unit is connected to the input terminal of the third handshake interface unit, and the input data is a first data group; the input terminal of the third handshake interface unit is specifically used to read input data and a second coefficient under the control of the control circuit; the output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit, and the output terminal of the multiplication circuit is connected to the input terminal of the fourth handshake interface unit; the input terminal of the fourth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit, and the output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory; the reconfigurable memory is specifically used to store the output data of the multiplication circuit under the control of the control circuit; the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the first handshake... The output of the handshake interface unit is connected to the input of the second handshake interface unit, and the input data is the second data group; the reconfigurable memory is also used to search for the output data of the multiplication circuit under the control of the control circuit, and the output of the reconfigurable memory is connected to the input of the sixth handshake interface unit; the input of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and the output of the second handshake interface unit is connected to the input of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform subtraction operations on the input data and the output data of the sixth handshake interface unit under the control of the control circuit; the input of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, and the calculation result is the residual calculation result.

[0012] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data is all data in the target feature map. The input terminal of the second handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform an accumulation operation on the input data under the control of the control circuit. The input terminal of the third handshake interface unit is specifically used to read the output result and the first coefficient of the reconfigurable adder circuit under the control of the control circuit. The output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit. The first coefficient is determined according to the number of data in the target feature map. The input terminal of the fifth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit. The output terminal of the fifth handshake interface unit is specifically used to output the output data of the multiplication circuit. The output data of the multiplication circuit is the global average pooling result of the input data.

[0013] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data includes one row of data from each pooling window in the target feature map. The input terminal of the second handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform a cyclic comparison operation on the input data under the control of the control circuit. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the temporary maximum or temporary minimum value of each pooling window. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the temporary maximum or temporary minimum value of each pooling window under the control of the control circuit.

[0014] In one embodiment, the input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data includes the next row of data for each pooling window in the target feature map. The reconfigurable memory is specifically used to find the temporary maximum or temporary minimum value of each pooling window under the control of the control circuit. The output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit. The input terminal of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform a comparison operation on the first value in the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and temporarily store the comparison result in a register. The comparison is performed based on the remaining value in the input data. The result is a cyclic comparison operation; the input of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the temporary maximum or minimum value of each pooling window. The output of the fourth handshake interface unit is connected to the input of the reconfigurable memory; the reconfigurable memory is specifically used to store the temporary maximum or minimum value of each pooling window under the control of the control circuit until the data comparison of each pooling window is completed. The reconfigurable memory is specifically used to output the temporary maximum or minimum value under the control of the control circuit. The output of the reconfigurable memory is connected to the input of the sixth handshake interface unit; the input of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit. The output of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The calculation result is the max pooling result or the min pooling result.

[0015] In a second aspect, embodiments of this application provide a computing device that includes the reconfigurable multi-mode intelligent computing circuit described in any one of the first aspects above.

[0016] The aforementioned reconfigurable multi-mode intelligent computing circuit includes a reconfigurable adder circuit, which performs any of the following operations under the control of a control circuit: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison; a reconfigurable memory, which stores data or performs numerical lookup under the control of the control circuit; a reconfigurable data path, which includes at least one handshake interface unit connected to both the reconfigurable adder circuit and the reconfigurable memory, for transmitting data under the control of the control circuit; and a control circuit, which controls the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information. By configuring the handshake interface, reconfigurable adder circuit, and reconfigurable memory in the data path through the control circuit, the direction of data flow can be changed, allowing flexible switching to any computing mode without requiring separate computing circuits for each post-processing step, effectively reducing chip area and power consumption. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit in one embodiment;

[0019] Figure 2 This is a schematic diagram of a one-to-many handshake interface unit structure in one embodiment;

[0020] Figure 3 This is a schematic diagram of a many-to-one handshake interface unit structure in one embodiment;

[0021] Figure 4 This is a schematic diagram of a many-to-many handshake interface unit structure in one embodiment;

[0022] Figure 5 This is a schematic diagram of a reconfigurable memory in one embodiment;

[0023] Figure 6 This is a schematic diagram of a reconfigurable adder circuit in one embodiment;

[0024] Figure 7 This is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit that performs normalized computation in one embodiment;

[0025] Figure 8This is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit that performs activation calculations in one embodiment;

[0026] Figure 9 This is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit that performs residual calculation in one embodiment;

[0027] Figure 10 This is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit that performs global mean pooling calculation in one embodiment;

[0028] Figure 11 This is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit that performs max-pooling or min-pooling computation in one embodiment. Detailed Implementation

[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0032] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0033] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0034] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0035] In neural network convolutional computation, after the convolution calculation is completed, post-processing calculations such as batch normalization, activation, pooling, and residual calculations are required. These calculations require separate circuit structures for each part.

[0036] In existing technologies, designing separate computational circuits for post-processing calculations such as batch normalization, activation, pooling, and residuals in neural networks results in larger chip areas and higher power consumption.

[0037] In view of this, embodiments of this application provide a reconfigurable multi-mode intelligent computing circuit that can effectively reduce chip area and power consumption.

[0038] In one exemplary embodiment, such as Figure 1 As shown, a reconfigurable multi-mode intelligent computing circuit 10 is provided. This circuit includes a reconfigurable adder circuit 100, a reconfigurable memory 200, a reconfigurable data path 300, and a control circuit 400. The reconfigurable adder circuit 100, under the control of the control circuit 400, performs any of the following operations: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison. The reconfigurable memory 200, under the control of the control circuit 400, stores data or performs numerical lookup. The reconfigurable data path 300 includes at least one handshake interface unit connected to both the reconfigurable adder circuit and the reconfigurable memory, and is used to transmit data under the control of the control circuit 400. The control circuit 400 controls the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information.

[0039] Optionally, the control circuit can receive external configuration information and control the reconfigurable adder circuit, reconfigurable memory, and reconfigurable data path according to the configuration information.

[0040] In one possible implementation, the configuration information can be a configuration instruction indicating the functions that the reconfigurable multi-mode intelligent computing circuit needs to implement. For example, the configuration information can be configuring the reconfigurable multi-mode intelligent computing circuit to implement normalized computing or to implement pooling computing. The control circuit can determine the configuration sub-information of the reconfigurable adder circuit, reconfigurable memory, and reconfigurable data path according to the configuration instruction.

[0041] In another possible implementation, the configuration information may include multiple configuration sub-information, corresponding to the configuration of the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path, respectively. For example, the configuration information may include configuring the reconfigurable adder circuit to perform addition operations and configuring the reconfigurable memory to store data.

[0042] Optionally, the handshake interface unit can be an interface mechanism based on a handshake protocol, used to transmit data between the reconfigurable adder, reconfigurable memory, input interface, and input interface, controlling data transmission through the handshake protocol. The handshake protocol can include the following signals: valid signal, ready signal, request signal, and acknowledge signal. The sender pulls the valid signal high to indicate that the data is valid; the receiver pulls the ready signal high to indicate that it is ready to receive data; the sender sends a request signal to indicate that it wishes to send data; and the receiver sends an acknowledge signal to indicate that it has successfully received the data.

[0043] Optionally, when transmitting data from the data source to the destination, the handshake interface unit may include a one-to-many handshake interface unit, a many-to-one handshake interface unit, and a many-to-many handshake interface unit.

[0044] Optionally, the handshake interface unit includes a data bus and at least one selection circuit.

[0045] For example, such as Figure 2 As shown, a one-to-many handshake interface unit can transmit data from one data source to multiple destinations, and during the transmission, one destination can receive the data; for example... Figure 3 As shown, a many-to-one handshake interface unit can transmit data from multiple data sources to a single destination. During the transmission process, data from one data source can be transmitted to the destination. Figure 4 As shown, the many-to-many handshake interface unit can transmit data from multiple data sources to multiple destinations, and can perform multiple one-to-one pairings for simultaneous transmission during the transmission process.

[0046] Optionally, the reconfigurable memory includes a selection circuit and memory, such as Figure 5As shown, the input terminal of the selection circuit is connected to the address bus or the write data bus, the output terminal of the selection circuit is connected to the address control signal of the memory, and the write data terminal of the memory is connected to the write data bus.

[0047] For example, when the reconfigurable memory stores data under the control of the control circuit, i.e. when the reconfigurable memory is in memory mode, the selection circuit selects the connection to the address bus under the control of the control circuit. Data is loaded by the write data bus and read data is output by the read data bus. The read / write enable terminal of the memory controls the memory to perform read and write operations.

[0048] For example, when the reconfigurable memory searches for data under the control of the control circuit, i.e. when the reconfigurable memory is in search mode, the selection circuit selects to connect to the write data bus under the control of the control circuit. The read / write enable terminal of the memory controls the memory to perform read operations. When writing data is input, the data at the corresponding address position is read out and output by the read data bus.

[0049] The aforementioned reconfigurable multi-mode intelligent computing circuit includes a reconfigurable adder circuit, which performs any of the following operations under the control of a control circuit: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison; a reconfigurable memory, which stores data or performs numerical lookup under the control of the control circuit; a reconfigurable data path, which includes at least one handshake interface unit connected to both the reconfigurable adder circuit and the reconfigurable memory, for transmitting data under the control of the control circuit; and a control circuit, which controls the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information. By configuring the handshake interface, reconfigurable adder circuit, and reconfigurable memory in the data path through the control circuit, the direction of data flow can be changed, allowing flexible switching to any computing mode without requiring separate computing circuits for each post-processing step, effectively reducing chip area and power consumption.

[0050] In one exemplary embodiment, such as Figure 6 As shown, the reconfigurable adder circuit includes: multiple selection circuits, an adder, a negation circuit, and a register.

[0051] Optionally, the selection circuit can be a multiplexer, which selects one of multiple input signals as the output according to the control of the control circuit.

[0052] Optional, such as Figure 6As shown, the selection circuit includes a first selection circuit Mux0, a second selection circuit Mux1, a third selection circuit Mux2, and a fourth selection circuit Mux3. The input terminal of the first selection circuit Mux0 is connected to the output terminal of the register and the first data input bus, respectively. The output terminal of the first selection circuit Mux0 is connected to the input terminal of the negation circuit, the input terminal of the second selection circuit Mux1, and the input terminal of the third selection circuit Mux2, respectively. The input terminal of the second selection circuit Mux1 is connected to the output terminal of the negation circuit, the output terminal of the first selection circuit Mux0, and the output terminal of the register, respectively. The output terminal of the second selection circuit Mux1 is connected to the input terminal of the adder. The input terminal of the third selection circuit Mux2 is connected to the output terminal of the first selection circuit Mux0, the output terminal of the adder, and the second data input bus. The output terminal of the third selection circuit Mux2 is connected to the input terminal of the fourth selection circuit Mux3. The input terminal of the fourth selection circuit Mux3 is connected to the output terminal of the adder, the output terminal of the third selection circuit Mux2, and the second data input bus. The output terminal of the fourth selection circuit Mux3 is connected to the input terminal of the register.

[0053] Optionally, the following section, using a schematic diagram of the reconfigurable adder circuit, explains the process of the reconfigurable adder performing different operations under the control of the control circuit.

[0054] When the reconfigurable adder performs addition, input 0 of the first selection circuit Mux0 is connected to the first data input bus, output of the first selection circuit Mux0 is connected to input 2 of the second selection circuit Mux1, output of the second selection circuit Mux1 is connected to the input of the adder, input of the adder is also connected to the second data input bus, output of the adder is connected to input 0 of the fourth selection circuit Mux3, and output of the fourth selection circuit Mux3 is connected to the input of the register. In this way, the reconfigurable adder can perform addition on the data of the first data input bus and the data of the second data input bus, store the calculated sum in the register, and output it.

[0055] When the reconfigurable adder performs a subtraction operation, input terminal 0 of the first selection circuit Mux0 is connected to the first data input bus, and the output terminal of the first selection circuit Mux0 is connected to the input terminal of the negation circuit to perform a negation operation on the data of the first data input bus. The output terminal of the negation circuit is connected to input terminal 1 of the second selection circuit Mux1, and the output terminal of the second selection circuit Mux1 is connected to the input terminal of the adder. The input terminal of the adder is also connected to the second data input bus, and the output terminal of the adder is connected to input terminal 0 of the fourth selection circuit Mux3. The output terminal of the fourth selection circuit Mux3 is connected to the input terminal of the register. In this way, the reconfigurable adder can calculate the difference between the data of the two data input buses and the data of the first data input bus, store the difference in the register, and output it.

[0056] When the reconfigurable adder performs a pass-through operation, input terminal 2 of the third selection circuit Mux4 is connected to the second data input bus, and the output terminal of the third selection circuit Mux4 is connected to the input terminal of the register. In this way, the data of the second data input bus can be directly stored in the register.

[0057] When the reconfigurable adder performs an accumulation operation, it can first be configured to perform a pass-through operation, storing the first value in a register. Then, the reconfigurable adder is configured to perform an addition operation, connecting the output of the register to input terminal 0 of the second selection circuit Mux1. The output of the second selection circuit is connected to the input of the adder, and the input of the adder is also connected to the second selection input bus. The addition operation is performed on the data input to the second selection input bus and the data output from the register. The output of the adder is connected to input terminal 0 of the fourth selection circuit Mux3, and the output of the fourth selection circuit Mux3 is connected to the input of the register. The above process is repeated, connecting the output of the register to the input of the second selection circuit Mux1 to perform the accumulation operation.

[0058] When the reconfigurable adder performs a comparison operation, it can first be configured to perform a subtraction operation, comparing the data on the first and second data input buses. The output of the adder is connected to the control terminal of the third selection circuit Mux2. When comparing the maximum value, if the sign bit of the adder's output is positive, then input terminal 1 of the third selection circuit Mux2 is connected to the second data input bus, the output of the third selection circuit Mux2 is connected to input terminal 1 of the fourth selection circuit Mux3, and the output of the fourth selection circuit Mux3 is connected to the input terminal of the register. That is, the larger value is the data on the second data input bus. If the sign bit of the adder's output is negative, then input terminal 0 of the third selection circuit Mux2 is connected to the output of the first selection circuit Mux0, the 0th input of the first selection circuit Mux0 is connected to the first data input bus, the output of the third selection circuit Mux2 is connected to input terminal 1 of the fourth selection circuit Mux3, and the output of the fourth selection circuit Mux3 is connected to the input terminal of the register. That is, the larger value is the data on the first data input bus. When comparing the minimum value, if the sign bit of the adder's output is positive, the third selection circuit Mux2 selects the data from the first data input bus and inputs it to the input of the fourth selection circuit Mux3; if the sign bit of the adder's output is negative, the third selection circuit Mux2 selects the data from the second data input bus and inputs it to the input of the fourth selection circuit Mux3.

[0059] When the reconfigurable adder performs a cyclic comparison operation, a set of data can be input through the second data input bus. First, the reconfigurable adder is configured to perform a pass-through operation, storing the first data in a register through the pass-through mode. The output of the register is connected to input terminal 1 of the first selection circuit Mux0. Then, the reconfigurable adder is configured to perform a comparison operation, comparing the first data with the second data and storing the comparison result in a register. This iterative comparison is performed until all data in a set has been compared.

[0060] By controlling each selection circuit through the controller and adjusting the data transmission direction, the reconfigurable adder circuit can perform any operation such as addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison.

[0061] In one exemplary embodiment, such as Figure 7 As shown, it also includes a multiplication circuit, which is connected to both the reconfigurable data path and the reconfigurable adder circuit.

[0062] Optional, such as Figure 7As shown, the reconfigurable data path includes a first handshake interface unit, a second handshake interface unit, a third handshake interface unit, a fourth handshake interface unit, a fifth handshake interface unit, and a sixth handshake interface unit. The first handshake interface unit is a one-to-many handshake interface unit; its input is used to read input data under the control of the control circuit, and its output is connected to the inputs of the second and third handshake interface units. The second handshake interface unit is a many-to-many handshake interface unit; its input is connected to the first coefficient, the input data, the output of the multiplication circuit, and the output of the sixth handshake interface unit. The output of the handshake interface unit is connected to the input of the reconfigurable adder circuit. The input of the second handshake interface unit is used to read at least one of the following data under the control of the control circuit: the first coefficient, input data, the output data of the multiplication circuit, and the output data of the sixth handshake interface unit. The third handshake interface unit is a many-to-many handshake interface unit. The input of the third handshake interface unit is connected to the second coefficient, the output of the first handshake interface unit, the output of the sixth handshake interface unit, and the output of the reconfigurable adder circuit. The output of the third handshake interface unit is connected to the input of the multiplication circuit. The input of the third handshake interface unit is used to read data under the control of the control circuit. At least one of the following data: second coefficient, input data, output data of the sixth handshake interface unit, and output data of the reconfigurable adder circuit; the fourth handshake interface unit is a many-to-one handshake interface unit, the input terminal of the fourth handshake interface unit is connected to the output terminal of both the multiplication circuit and the reconfigurable adder circuit, the output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory, and the input terminal of the fourth handshake interface unit is used to read at least one of the following data under the control of the control circuit: output data of the multiplication circuit and output data of the reconfigurable adder circuit; the fifth handshake interface unit is a many-to-one handshake interface unit, the input terminal of the fifth handshake interface unit is connected to the input terminal of the second handshake interface unit, and the output terminal of the fifth handshake interface unit is connected to the input terminal of the reconfigurable memory. The output terminals of the six-handshake interface unit, the multiplication circuit, and the reconfigurable adder circuit are all connected. The output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The input terminal of the fifth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the sixth handshake interface unit, the output data of the multiplication circuit, and the output data of the reconfigurable adder circuit. The sixth handshake interface unit is a one-to-many handshake interface unit. The input terminal of the sixth handshake interface unit is connected to the output terminal of the reconfigurable memory, and the output terminal of the sixth handshake interface unit is connected to the second handshake interface unit, the third handshake interface unit, and the fifth handshake interface unit.

[0063] Optional, such as Figure 7As shown, reconfigurable data can switch data paths under the control of the control circuit. When the configuration information changes with the data information, the data path is a dynamic path. When the configuration information is static, that is, the data path does not change for a period of time, it is a static path. In the embodiments of this application, any handshake interface unit supports both static and dynamic configurations.

[0064] Optionally, each handshake interface unit determines which type of data to read under the control of the control circuit.

[0065] The following section, using the circuit diagram of the reconfigurable multi-mode intelligent computing circuit, explains the process of the reconfigurable multi-mode intelligent computing circuit performing different modes of calculation under the control of the control circuit.

[0066] In one exemplary embodiment, when performing normalization calculations, such as Figure 7 As shown, exemplarily, the input terminal of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 1) of the first handshake interface unit HS-S-MUX0 is connected to the input terminal (input terminal 1) of the third handshake interface unit HS-SD-MUX2. The input terminal of the third handshake interface unit HS-SD-MUX2 is specifically used to read input data and the second coefficient under the control of the control circuit (input terminal 1 reads input data, input terminal 0 reads the second coefficient). The output terminals (output terminals 0 and 1) of the third handshake interface unit HS-SD-MUX2 are connected to the input terminal of the multiplication circuit. The output terminal of the multiplication circuit is connected to the input terminal (input terminal 2) of the second handshake interface unit HS-SD-MUX1. The input terminals of HS-SD-MUX1 are specifically used to read the output data and the first coefficient of the multiplication circuit under the control of the control circuit (input terminal 2 reads the input data, and input terminal 0 reads the first coefficient). The output terminals (output terminals 0 and 1) of the second handshake interface unit HS-SD-MUX1 are connected to the input terminals of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform addition operations on the output data and the first coefficient of the multiplication circuit under the control of the control circuit. The input terminal (input terminal 1) of the fifth handshake interface unit HS-D-MUX4 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output terminal of the fifth handshake interface unit is specifically used to output the output data of the reconfigurable adder circuit. The output data of the reconfigurable adder circuit is the normalized result of the input data.

[0067] Optionally, the normalization calculation formula can be expressed as: The second coefficient is The first coefficient is , For input data, To reconstruct the output data of the adder circuit.

[0068] In an exemplary embodiment, when performing activation calculations, there are complex activation functions such as sigmoid and tanh in the post-processing calculations of the neural network. Direct calculation would require a lot of computing resources. However, the direct mapping method based on lookup tables is easier to implement. When calculating activation values, the lookup table is used for mapping, which can be divided into two processes. First, the lookup table is stored in memory, and then the data to be processed is input as an address into the address bus of the memory for lookup.

[0069] For example, when implementing the storage of the lookup table in memory, such as Figure 8 As shown, the input terminal of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 0) of the first handshake interface unit HS-S-MUX0 is connected to the input terminal (input terminal 1) of the second handshake interface unit HS-SD-MUX1, and the input data is preset table data. The input terminal of the second handshake interface unit HS-SD-MUX1 is specifically used to read the first coefficient and input data under the control of the control circuit (input terminal 0 reads the first coefficient, and input terminal 1 reads the input data). The first coefficient is 0. The output of the second handshake interface unit is connected to the input of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform pass-through operations under the control of the control circuit; the input of the fourth handshake interface unit HS-D-MUX3 (input terminal 1) is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output data of the reconfigurable adder circuit is the input data; the output of the fourth handshake interface unit HS-D-MUX3 is connected to the input of the reconfigurable memory; the reconfigurable memory is specifically used to store preset table data under the control of the control circuit.

[0070] For example, when the data to be processed is input as an address into the memory's address bus for lookup, such as... Figure 8As shown, the input data at this time is the data to be calculated, not the preset table data. The input terminal of the first handshake interface unit HS-S-MUX0 is specifically used to read the input data under the control of the control circuit. The output terminal (output terminal 0) of the first handshake interface unit HS-S-MUX0 is connected to the input terminal (input terminal 1) of the second handshake interface unit HS-SD-MUX1. The input terminal of the second handshake interface unit HS-SD-MUX1 is specifically used to read the first coefficient and the input data (input terminal 0 reads the first coefficient, input terminal 1 reads the input data) under the control of the control circuit. The first coefficient is 0. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform addition operations on the input data and the first coefficient under the control of the control circuit. The fourth handshake interface unit HS- The input terminal (input terminal 1) of D-MUX3 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the input data. The output terminal of the fourth handshake interface unit HS-D-MUX3 is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to perform numerical lookup based on the input data under the control of the control circuit. The output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit HS-S-MUX5. The input terminal (input terminal 2) of the fifth handshake interface unit HS-D-MUX4 is specifically used to read the output data of the sixth handshake interface unit HS-D-MUX5 under the control of the control circuit. The output terminal of the fifth handshake interface unit HS-D-MUX4 is used to output the calculation result under the control of the control circuit. The calculation result is the numerical lookup result.

[0071] In an exemplary embodiment, when performing residual calculation, the first feature map FmapA and the second feature map FmapB need to be subtracted sequentially. The calculation formula can be expressed as follows: ,in, As a constant value, the feature map can be divided into multiple data groups according to the depth of the reconfigurable memory. The length of each data group does not exceed the depth of the reconfigurable memory. During residual calculation, it can be divided into two processes. First, a data group (the first data group) of the second feature map FmapB is input into the multiplier through the first and third handshake interface units. The third handshake interface unit reads the input data and the second coefficient, and outputs it to the multiplier for multiplication to obtain the result. The first data group is processed and its output is output from the multiplier. The result is then input into the reconfigurable memory through the fourth handshake interface unit to store the processing result corresponding to the first data group. In the second step, a set of data (the second data group) of the first feature map FmapA is input into the storable adder circuit through the first handshake interface unit and the second handshake interface unit. The storable adder performs a subtraction operation, reads the processing result of the first data group from the reconfigurable memory, and inputs it into the storable adder circuit through the sixth handshake interface unit and the second handshake interface unit. The two sets of data are subtracted sequentially, and the subtraction result is output through the fifth handshake node unit.

[0072] In this case, a set of data in feature map FmapA and a set of data in feature map FmapB are in the same position in the two feature maps.

[0073] For example, when processing a set of data of the second feature map, such as Figure 9 As shown, the input terminal of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 1) of the first handshake interface unit HS-S-MUX0 is connected to the input terminal (input terminal 1) of the third handshake interface unit HS-SD-MUX2, and the input data is the first data group. The input terminal of the third handshake interface unit HS-SD-MUX2 is specifically used to read the input data and the second coefficient under the control of the control circuit (input terminal 0 reads the first coefficient, and input terminal 1 reads the input data). The output terminal of the third handshake interface unit HS-SD-MUX2 is connected to the input terminal of the multiplication circuit, and the output terminal of the multiplication circuit is connected to the input terminal (input terminal 0) of the fourth handshake interface unit HS-SD-MUX3. The input terminal (input terminal 0) of the fourth handshake interface unit HS-D-MUX3 is specifically used to read the output data of the multiplication circuit under the control of the control circuit, and the output terminal of the fourth handshake interface unit HS-D-MUX3 is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the output data of the multiplication circuit under the control of the control circuit.

[0074] For example, during subtraction, the input terminal of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 0) of the first handshake interface unit HS-S-MUX0 is connected to the input terminal (input terminal 1) of the second handshake interface unit HS-SD-MUX1, and the input data is the second data group. The reconfigurable memory is also used to search for the output data of the multiplication circuit under the control of the control circuit. The output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit HS-DMUX5. The input terminal of the second handshake interface unit HS-SD-MUX1 is specifically used to read input data and the sixth handshake interface unit under the control of the control circuit. The output data (input terminal 1 reads input data, input terminal 3 is connected to output terminal 0 of the sixth handshake interface unit to read output data), the output terminal of the second handshake interface unit HS-SD-MUX1 is connected to the input terminal of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform subtraction operation on the input data and the output data of the sixth handshake interface unit under the control of the control circuit; the input terminal (input terminal 1) of the fifth handshake interface unit HS-D-MUX4 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output terminal of the fifth handshake interface unit HS-D-MUX4 is used to output the calculation result under the control of the control circuit, and the calculation result is the residual calculation result.

[0075] In an exemplary embodiment, when performing pooling calculations, since the pooling calculations in the neural network post-processing calculations include max pooling, min pooling, and mean pooling operations on the target feature map, pooling calculations of sliding windows and global windows can be performed. When there is only one sliding window, it can be understood as a global window.

[0076] Optionally, mean pooling can be achieved by summing all feature values ​​in the sliding window and then multiplying by a constant, where the constant is the reciprocal of the number of feature values ​​in the sliding window. For example, ... Figure 10 As shown, taking one sliding window as an example, the input terminal of the first handshake interface unit HS_S_MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 0) of the first handshake interface unit HS_S_MUX0 is connected to the input terminal (input terminal 1) of the second handshake interface unit HS_SD_MUX1. The input data is all the data in the target feature map. The input terminal of the second handshake interface unit HS_SD_MUX1 is specifically used to read input data under the control of the control circuit. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit.

[0077] The reconfigurable adder circuit is specifically used to perform accumulation operations on the input data under the control of the control circuit. The input terminal of the third handshake interface unit HS_SD_MUX2 is specifically used to read the output result and the first coefficient of the reconfigurable adder circuit under the control of the control circuit (the first coefficient is read at input terminal 0, and the output result of the reconfigurable adder circuit is read at input terminal 2). The output terminal of the third handshake interface unit HS_SD_MUX2 is connected to the input terminal of the multiplication circuit. The first coefficient is determined according to the number of data in the target feature map. The input terminal (output terminal 0) of the fifth handshake interface unit HS_D_MUX4 is specifically used to read the output data of the multiplication circuit under the control of the control circuit. The output terminal of the fifth handshake interface unit HS_D_MUX4 is specifically used to output the output data of the multiplication circuit. The output data of the multiplication circuit is the global average pooling result of the input data.

[0078] The first coefficient is the reciprocal of the number of data points in the target feature map.

[0079] Optionally, when performing maximum or minimum pooling on the target feature map, the maximum or minimum value of each window in the sliding window can be determined by first determining the temporary maximum or minimum value in the first row of data in the sliding window, storing the temporary maximum or minimum value in the reconfigurable memory, and then comparing the obtained temporary maximum or minimum value with the second row of data in the sliding window until all rows in the window have been compared.

[0080] For example, such as Figure 11As shown, taking three sliding windows as an example, when determining the temporary maximum or minimum value, the input terminal of the first handshake interface unit HS_S_MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 0) of the first handshake interface unit HS_S_MUX0 is connected to the input terminal (input terminal 1) of the second handshake interface unit HS_SD_MUX1. The input data includes one row of data from each pooling window in the target feature map. The input terminal (input terminal 1) of the second handshake interface unit HS_SD_MUX1 is specifically used to read input data under the control of the control circuit. The output of X1 is connected to the input of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform cyclic comparison operations on the input data under the control of the control circuit; the input of the fourth handshake interface unit HS_D_MUX3 (input terminal 1) is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the temporary maximum or minimum value of each pooling window. The output of the fourth handshake interface unit HS_D_MUX3 is connected to the input of the reconfigurable memory; the reconfigurable memory is specifically used to store the temporary maximum or minimum value of each pooling window under the control of the control circuit.

[0081] Optional, such as Figure 11 As shown, addresses 0, 1, and 2 sequentially store the temporary maximum or minimum value calculated for each sliding window.

[0082] Optionally, after completing the cyclic comparison of the first row of data in each sliding window, it is necessary to compare the temporary maximum or temporary minimum value of the other rows of data with the first row of data.

[0083] For example, such as Figure 11As shown, the input terminal of the first handshake interface unit HS_S_MUX0 is specifically used to read input data under the control of the control circuit. The output terminal (output terminal 0) of the first handshake interface unit HS_S_MUX0 is connected to the input terminal (input terminal 1) of the second handshake interface unit HS_SD_MUX1. The input data includes the next row of data for each pooling window in the target feature map. The reconfigurable memory is specifically used to find the temporary maximum or temporary minimum value of each pooling window under the control of the control circuit. The output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit HS_D_MUX5. The input terminals of the second handshake interface unit HS_SD_MUX1 are specifically used to read input data and the output data of the sixth handshake interface unit under the control of the control circuit (input terminal 1 reads input data, and input terminal 3 is connected to output terminal 0 of the sixth handshake interface unit to read output data). The output terminal of the second handshake interface unit HS_SD_MUX1 is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform a comparison operation on the first value in the input data and the output data of the sixth handshake interface unit HS_D_MUX5 under the control of the control circuit, and temporarily store the comparison result. The register stores the remaining value in the input data and performs a cyclic comparison operation based on the comparison result. The input terminal (input terminal 1) of the fourth handshake interface unit HS_D_MUX5 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the temporary maximum or minimum value of each pooling window. The output terminal of the fourth handshake interface unit HS_D_MUX3 is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the temporary maximum or minimum value of each pooling window under the control of the control circuit, until the number of pooling windows reaches the specified value. According to the comparison, the reconfigurable memory is specifically used to output temporary maximum or minimum values ​​under the control of the control circuit. The output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit HS_D_MUX5. The input terminal (input terminal 2) of the fifth handshake interface unit HS_D_MUX4 is specifically used to read the output data (output terminal 2) of the sixth handshake interface unit HS_D_MUX5 under the control of the control circuit. The output terminal of the fifth handshake interface unit HS_D_MUX4 is used to output the calculation result under the control of the control circuit. The calculation result is the max pooling result or the min pooling result.

[0084] In one embodiment, this application provides a computing device that includes the reconfigurable multi-mode intelligent computing circuit described in any of the above embodiments.

[0085] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A reconfigurable multi-mode intelligent computing circuit, characterized in that, include: A reconfigurable adder circuit, wherein the reconfigurable adder circuit is used to perform any of the following operations under the control of a control circuit: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison; A reconfigurable memory, which is used to store data under the control of a control circuit, or to perform numerical lookup under the control of the control circuit; A reconfigurable data path includes at least one handshake interface unit, which is connected to both the reconfigurable adder circuit and the reconfigurable memory, and is used to transmit data under the control of the control circuit. A control circuit is provided for controlling the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information. The reconfigurable adder circuit includes: multiple selection circuits, an adder, a negation circuit, and a register; the selection circuits include a first selection circuit, a second selection circuit, a third selection circuit, and a fourth selection circuit; the input terminal of the first selection circuit is connected to the output terminal of the register and a first data input bus, respectively; the output terminal of the first selection circuit is connected to the input terminals of the negation circuit, the second selection circuit, and the third selection circuit, respectively; the input terminal of the second selection circuit is connected to the output terminals of the negation circuit, the first selection circuit, and the register, respectively; the output terminal of the second selection circuit is connected to the input terminal of the adder; the input terminal of the third selection circuit is connected to the output terminal of the first selection circuit, the output terminal of the adder, and a second data input bus, respectively; the output terminal of the third selection circuit is connected to the input terminal of the fourth selection circuit; the input terminal of the fourth selection circuit is connected to the output terminal of the adder, the output terminal of the third selection circuit, and the second data input bus, respectively; the output terminal of the fourth selection circuit is connected to the input terminal of the register. The reconfigurable memory includes a selection circuit and a memory. The input terminal of the selection circuit is connected to an address bus or a write data bus, the output terminal of the selection circuit is connected to an address control signal of the memory, and the write data terminal of the memory is connected to a write data bus. A multiplication circuit is included, which is connected to both the reconfigurable data path and the reconfigurable adder circuit. The reconfigurable data path includes a first handshake interface unit, a second handshake interface unit, a third handshake interface unit, a fourth handshake interface unit, a fifth handshake interface unit, and a sixth handshake interface unit. The first handshake interface unit is a one-to-many handshake interface unit, whose input is used to read input data under the control of the control circuit, and whose output is connected to the inputs of the second and third handshake interface units. The second handshake interface unit is a many-to-many handshake interface unit, and its output... The input terminal of the second handshake interface unit is connected to the first coefficient, the input data, the output terminal of the multiplication circuit, and the output terminal of the sixth handshake interface unit. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The input terminal of the second handshake interface unit is used to read at least one of the following data under the control of the control circuit: the first coefficient, the input data, the output data of the multiplication circuit, and the output data of the sixth handshake interface unit. The third handshake interface unit is a many-to-many handshake interface unit. The input terminal of the third handshake interface unit is connected to the second coefficient, the output terminal of the first handshake interface unit, the output terminal of the sixth handshake interface unit, and the output terminal of the reconfigurable adder circuit. All output terminals are connected. The output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit. The input terminal of the third handshake interface unit is used to read at least one of the following data under the control of the control circuit: the second coefficient, input data, the output data of the sixth handshake interface unit, and the output data of the reconfigurable adder circuit. The fourth handshake interface unit is a many-to-one handshake interface unit. The input terminal of the fourth handshake interface unit is connected to both the output terminal of the multiplication circuit and the output terminal of the reconfigurable adder circuit. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The input terminal of the fourth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the second coefficient, input data, the output data of the sixth handshake interface unit, and the output data of the reconfigurable adder circuit. The control circuit reads at least one of the following data: the output data of the multiplication circuit and the output data of the reconfigurable adder circuit; the fifth handshake interface unit is a many-to-one handshake interface unit, and the input terminal of the fifth handshake interface unit is connected to the sixth handshake interface unit, the output terminal of the multiplication circuit, and the output terminal of the reconfigurable adder circuit. The output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, and the input terminal of the fifth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the sixth handshake interface unit, the output data of the multiplication circuit, and the output data of the reconfigurable adder circuit;The sixth handshake interface unit is a one-to-many handshake interface unit. The input terminal of the sixth handshake interface unit is connected to the output terminal of the reconfigurable memory, and the output terminal of the sixth handshake interface unit is connected to the second handshake interface unit, the third handshake interface unit, and the fifth handshake interface unit.

2. The reconfigurable multi-mode intelligent computing circuit according to claim 1, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the first handshake interface unit is connected to the input terminal of the third handshake interface unit. The input terminal of the third handshake interface unit is specifically used to read the input data and the second coefficient under the control of the control circuit. The output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit, and the output terminal of the multiplication circuit is connected to the input terminal of the second handshake interface unit. The input terminal of the second handshake interface unit is specifically used to read the output data of the multiplication circuit and the first coefficient under the control of the control circuit. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform an addition operation on the output data of the multiplication circuit and the first coefficient under the control of the control circuit. The input terminal of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output terminal of the fifth handshake interface unit is specifically used to output the output data of the reconfigurable adder circuit, and the output data of the reconfigurable adder circuit is the normalized result of the input data.

3. The reconfigurable multi-mode intelligent computing circuit according to claim 1, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data is preset table data. The input terminal of the second handshake interface unit is specifically used to read the first coefficient and input data under the control of the control circuit, wherein the first coefficient is 0, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform pass-through operations under the control of the control circuit. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the input data. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the preset table data under the control of the control circuit.

4. The reconfigurable multi-mode intelligent computing circuit according to claim 3, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input terminal of the second handshake interface unit is specifically used to read the first coefficient and input data under the control of the control circuit, wherein the first coefficient is 0, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform an addition operation on the input data and the first coefficient under the control of the control circuit. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the input data. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to perform numerical lookup based on the input data under the control of the control circuit, and the output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit. The input terminal of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit. The output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The calculation result is a numerical lookup result.

5. The reconfigurable multi-mode intelligent computing circuit according to claim 1, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the third handshake interface unit. The input data is a first data group. The input terminal of the third handshake interface unit is specifically used to read the input data and the second coefficient under the control of the control circuit. The output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit, and the output terminal of the multiplication circuit is connected to the input terminal of the fourth handshake interface unit. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit, and the output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the output data of the multiplication circuit under the control of the control circuit. The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data is a second data group. The reconfigurable memory also searches for the output data of the multiplication circuit under the control of the control circuit, and the output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit. The input terminal of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform a subtraction operation on the input data and the output data of the sixth handshake interface unit under the control of the control circuit. The input terminal of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The calculation result is the residual calculation result.

6. The reconfigurable multi-mode intelligent computing circuit according to claim 1, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data is all data in the target feature map. The input terminal of the second handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform an accumulation operation on the input data under the control of the control circuit. The input terminal of the third handshake interface unit is specifically used to read the output result of the reconfigurable adder circuit and the first coefficient under the control of the control circuit. The output terminal of the third handshake interface unit is connected to the input terminal of the multiplication circuit. The first coefficient is determined according to the number of data in the target feature map. The input terminal of the fifth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit. The output terminal of the fifth handshake interface unit is specifically used to output the output data of the multiplication circuit. The output data of the multiplication circuit is the global average pooling result of the input data.

7. The reconfigurable multi-mode intelligent computing circuit according to claim 1, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data includes one row of data from each pooling window in the target feature map. The input terminal of the second handshake interface unit is specifically used to read input data under the control of the control circuit, and the output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform a cyclic comparison operation on the input data under the control of the control circuit. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the temporary maximum or temporary minimum value of each pooling window. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the temporary maximum or temporary minimum value of each pooling window under the control of the control circuit.

8. The reconfigurable multi-mode intelligent computing circuit according to claim 7, characterized in that, The input terminal of the first handshake interface unit is specifically used to read input data under the control of the control circuit. The output terminal of the first handshake interface unit is connected to the input terminal of the second handshake interface unit. The input data includes the next row of data of each pooling window in the target feature map. The reconfigurable memory is specifically used to find the temporary maximum or temporary minimum value of each pooling window under the control of the control circuit. The output of the reconfigurable memory is connected to the input of the sixth handshake interface unit. The input terminal of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit. The output terminal of the second handshake interface unit is connected to the input terminal of the reconfigurable adder circuit. The reconfigurable adder circuit is specifically used to perform a comparison operation on the first value in the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and temporarily store the comparison result in a register, and perform a cyclic comparison operation on the remaining value in the input data and the comparison result. The input terminal of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the temporary maximum or temporary minimum value of each pooling window. The output terminal of the fourth handshake interface unit is connected to the input terminal of the reconfigurable memory. The reconfigurable memory is specifically used to store the temporary maximum or temporary minimum value of each pooling window under the control of the control circuit until the data comparison of each pooling window is completed. The reconfigurable memory is specifically used to output the temporary maximum or temporary minimum value under the control of the control circuit. The output terminal of the reconfigurable memory is connected to the input terminal of the sixth handshake interface unit. The input terminal of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit. The output terminal of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The calculation result is either the maximum pooling result or the minimum pooling result.

9. A computing device, characterized in that, The computing device includes the reconfigurable multi-mode intelligent computing circuit according to any one of claims 1-8.

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