Multi-connected air conditioner communication system

Abstract

The application discloses a multi-connected air conditioner communication system, which comprises a plurality of outdoor units and a plurality of indoor units connected to a Homebus bus, and the outdoor units or the indoor units are communication nodes, wherein the communication node comprises a main controller, a communication chip for receiving communication signals from the Homebus bus, and a demodulation circuit arranged between the communication chip and the main controller and used for converting signals output by the communication chip into binary output signals corresponding to AMI signals on the Homebus bus; the demodulation circuit can delay the high level output by the communication chip for a first time starting from the moment when the output end of the communication chip changes from low level to high level; and the first time is determined based on at least a period required for transmitting 1-bit binary data. The application can improve the decoding accuracy of the main controller by designing the demodulation circuit.

Description

Technical Field

[0001] This invention relates to the field of communication technology for multi-split air conditioners, and more particularly to a communication system for multi-split air conditioners. Background Technology

[0002] Multi-split air conditioning systems consist of an indoor unit system with multiple indoor units and an outdoor unit system with multiple outdoor units. Communication between the indoor and outdoor units typically uses the Homebus (i.e., home bus system) communication protocol. Currently, most multi-split air conditioning systems use the Sanmei Electric MM1192 communication chip or its similar HH1198 chip as the core, with various communication circuits, drive circuits, and protection circuits integrated in the periphery to form a Homebus communication system.

[0003] Existing Homebus communication systems that rely on the MM1192 communication chip or its similar HH1198 chip typically use a communication frequency of 9.6kHz. Due to design limitations of the communication hardware circuit, they often cannot support higher communication frequencies. With the integration of Bluetooth MESH (i.e., wireless mesh networking), NFC, and WIFI functions with multi-split air conditioners, the low communication frequency of the Homebus communication system results in low information transmission efficiency, which can no longer meet the functional interaction requirements of multi-split air conditioners with emerging communication technologies, thus hindering the development of multi-split air conditioners.

[0004] When the existing Homebus communication system is communicating, because the range of sound that the human ear can hear is between 20Hz and 20kHz, users may sometimes hear a ticking sound during communication.

[0005] Therefore, this application aims to address the pain point of generating ticking sounds and improve the application scenarios of multi-split air conditioners, which requires increasing the communication frequency to above 20KHz.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this application, and therefore may include prior art that is not known to those skilled in the art. Summary of the Invention

[0007] To address the problems mentioned in the background art, this application provides a multi-split air conditioning communication system. Considering the communication frequency, a demodulation circuit between the communication chip and the main controller is used to delay the high level when the communication chip changes from low to high level, thereby improving the accuracy of the main controller in acquiring communication signals and thus improving the decoding accuracy of the main controller.

[0008] To achieve the above-mentioned objectives, the present invention employs the following technical solution: This application relates to a multi-split air conditioning communication system, comprising: Multiple outdoor units and multiple indoor units are connected to the Homebus bus, making the outdoor or indoor unit a communication node. The communication node includes: The master controller is used to control the communication node. A communication chip used to receive communication signals from the Homebus bus; The demodulation circuit is located between the communication chip and the main controller, and is used to convert the signal output by the communication chip into a binary output signal corresponding to the AMI signal on the Homebus bus. The demodulation circuit can synchronously transmit the signal output by the communication chip when the output of the communication chip is at a high level or changes from a high level to a low level. Furthermore, the demodulation circuit can start the moment the output of the communication chip changes from low to high, delaying the high level output of the communication chip to the first time. The first time is determined at least based on the period required to transmit 1 bit of binary data.

[0009] The multi-split air conditioning communication system involved in this application has a communication problem. If the communication signal transmitted on the Homebus cannot be correctly decoded by the main controller after being demodulated by the communication chip and demodulation circuit, it will lead to poor communication. Furthermore, as the number of communication nodes increases, the length of the bus cable increases, and the introduction of cable distributed capacitance also causes the communication signal waveform to be delayed. Therefore, the demodulation circuit delays the high level from the beginning of the change of the output signal of the communication chip from low level to high level, thereby improving the signal acquisition accuracy of the main controller.

[0010] The initial delay is related to the communication frequency, enabling the use of a wide range of frequency scenarios and improving communication quality at high frequencies.

[0011] With improved communication quality and frequency, it facilitates the deployment of multiple communication nodes over long distances.

[0012] In some embodiments of this application, the first time is determined based on the period, specifically as follows: The first time is the product of half of the cycle and the golden section point.

[0013] This design is the simplest and was discovered during testing.

[0014] In some embodiments of this application, the first time is determined based on the period and the maximum delay time generated by the Homebus bus; The maximum delay time was determined by testing the multi-split air conditioning system.

[0015] Under ideal waveform conditions, this represents the minimum delay time generated by the Homebus bus.

[0016] In some embodiments of this application, the delay time will be within the range of minimum and maximum delay time regardless of how the communication waveform changes, and therefore, it is determined based on both at the first moment.

[0017] In some embodiments of this application, the first time is the average of half of the cycle and the maximum delay time.

[0018] In some embodiments of the application, the average of half a cycle and the maximum delay time is taken, which is compatible with both the maximum and minimum delay times.

[0019] In some embodiments of this application, the demodulation circuit includes: The charging and discharging circuit receives the level output by the output terminal of the communication chip and can delay the high level for the first time from the moment the output signal of the communication chip changes from low level to high level. The first switch control circuit, wherein the level output by the charging and discharging circuit controls the on / off state of the first switch control circuit; The second switch control circuit controls the on / off state of the second switch control circuit, and the output of the second switch control circuit is connected to the signal receiving terminal of the main controller.

[0020] In some embodiments of this application, the multi-split air conditioning communication system further includes: A receiving-side AC coupling circuit, connected to the receiving side of the communication chip, is used to receive the transmission signal from the other side on the Homebus bus and send it to the communication chip. The transmitting side AC coupling circuit is connected to the transmitting side of the communication chip and is used to receive signals from the communication chip and output communication signals to the Homebus bus.

[0021] In some embodiments of this application, the multi-split air conditioning communication system further includes: The bus drive circuit is used to drive and amplify the signal output by the communication chip at the signal output terminal.

[0022] Other features and advantages of the present invention will become clearer after reading the detailed embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This refers to the connection method of existing multi-split air conditioning communication systems; Figure 2 A schematic diagram illustrating the communication principle of an existing multi-split air conditioning communication system; Figure 3 The ideal waveform diagram for communication in a multi-split air conditioning communication system under ideal conditions; Figure 4 This is a waveform diagram of a multi-split air conditioning communication system during actual communication. Figure 5 This is a circuit diagram of the demodulation circuit in an embodiment of a multi-split air conditioning communication system according to this application; Figure 6 The input and output waveforms are used to simulate the demodulation circuit in the multi-split air conditioning communication system embodiment proposed in this application. Figure 7 The waveform diagrams are actual test results from the multi-split air conditioning communication system embodiments proposed in this application. Figure 8 The maximum delay time tested when communicating with the multi-split air conditioning communication system proposed in this application; Figure 9 The waveform diagram shown is from an actual test in an embodiment of the multi-split air conditioning communication system proposed in this application, where the sampling points are shown; Figure 10 The schematic diagram of the existing impedance matching circuit; Figure 11 A schematic circuit diagram showing the characteristic impedance of a radio frequency transmission line; Figure 12 A schematic circuit diagram for obtaining the reflection coefficient; Figure 13 This is a schematic diagram of the impedance matching circuit in an embodiment of a multi-split air conditioning communication system proposed in this application. Figure 1 ; Figure 14 The diagrams show the bus waveform, the waveform of the transmitting end of the communication chip, and the waveform of the receiving end of the main controller in the embodiment of the multi-split air conditioning communication system proposed in this application. Figure 15 This is a model diagram of the cables in an embodiment of a multi-split air conditioning communication system according to this application; Figure 16This is a schematic diagram of the impedance matching circuit in an embodiment of a multi-split air conditioning communication system proposed in this application. Figure 2 ; Figure 17 This is a schematic diagram of the impedance matching circuit in an embodiment of a multi-split air conditioning communication system proposed in this application. Figure 3 ; Figure 18 This is a schematic diagram of the impedance matching circuit in an embodiment of a multi-split air conditioning communication system proposed in this application. Figure 4 . Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0027] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0030] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0031] Basic working principle of air conditioners Air conditioners execute a refrigeration cycle using a compressor, condenser, expansion valve, and evaporator. The refrigeration cycle involves a series of processes, including compression, condensation, expansion, and evaporation, to cool or heat an indoor space.

[0032] Low-temperature, low-pressure refrigerant enters the compressor, which compresses it into a high-temperature, high-pressure refrigerant gas and discharges the compressed refrigerant gas. The discharged refrigerant gas flows into the condenser. The condenser condenses the compressed refrigerant into a liquid phase, and the heat is released to the surrounding environment through the condensation process.

[0033] The expansion valve expands the high-temperature, high-pressure liquid refrigerant that condenses in the condenser into a low-pressure liquid refrigerant. The evaporator evaporates the expanded refrigerant in the expansion valve and returns the low-temperature, low-pressure refrigerant gas to the compressor. The evaporator achieves its cooling effect by utilizing the latent heat of refrigerant evaporation to exchange heat with the material being cooled. Throughout the cycle, the air conditioner regulates the temperature of the indoor space.

[0034] The outdoor unit of an air conditioner refers to the part of the refrigeration cycle that includes the compressor and the outdoor heat exchanger. The indoor unit of an air conditioner includes the indoor heat exchanger, and an expansion valve can be provided in either the indoor or outdoor unit.

[0035] The indoor and outdoor heat exchangers function as either condensers or evaporators. When the indoor heat exchanger is used as a condenser, the air conditioner functions as a heater in heating mode; when the indoor heat exchanger is used as an evaporator, the air conditioner functions as a cooler in cooling mode.

[0036] This application relates to a communication system for multi-split air conditioners, which is used in multi-split air conditioners. The basic working principle of multi-split air conditioners is described above as the basic working principle of air conditioners.

[0037] In some embodiments of this application, the multi-split air conditioner includes multiple indoor units and multiple outdoor units that are sequentially connected to a Homebus bus. The indoor units and outdoor units communicate using differential signals on the Homebus bus.

[0038] See Figure 1 It shows multiple indoor units (IDU, In Door Unit) and multiple outdoor units (ODU, Out Door Unit) connected to the Homebus bus.

[0039] The current solution allows for a maximum of 40 outdoor units and 160 indoor units, for a total of 200 nodes.

[0040] Existing solutions based on the MM1192 chip or its similar HH1198 chip have a communication frequency of 9.6KHz.

[0041] Both indoor and outdoor units can serve as transmitting communication nodes, and both can serve as receiving communication nodes that communicate with transmitting communication nodes. Therefore, indoor and outdoor units are collectively referred to as communication nodes.

[0042] That is, when the indoor unit acts as the transmitting communication node, the opposite communication node is the outdoor unit, which is also the receiving communication node; when the outdoor unit acts as the transmitting communication node, the opposite communication node is the indoor unit, which is also the receiving communication node.

[0043] The communication node includes the main controller, communication chip, and its peripheral circuitry.

[0044] In some embodiments of this application, the communication chip typically uses the MM1192 communication chip, which receives signals that have undergone Alternate Mark Inversion (AMI) (referred to as AMI signals). When the AMI signal is used and output in home bus systems, etc., it is composed of three values: high level, intermediate level and low level, and passes through the positive signal line and the negative signal line (i.e., bipolar signal line).

[0045] In communication methods that use this signal, a logic "1" is assigned to the middle level (e.g., +2.5V), and a logic "0" is alternately assigned to the high level (e.g., +5V) and the low level (e.g., 0V).

[0046] All communication chips have a Homebus interface for connecting to the Homebus bus. That is, the Homebus interface of the communication chip in the indoor unit and the Homebus interface of the communication chip in the outdoor unit are both connected to the Homebus bus.

[0047] The Homebus includes Bus A and Bus B (i.e., bipolar signal lines), and transmits differential bus signals (i.e., AMI signals) on the Homebus.

[0048] See Figure 2 Let's take the outdoor unit as an example for explanation.

[0049] The peripheral circuits described above include: signal coupling circuit, bus drive circuit, demodulation circuit, and modulation circuit.

[0050] Signal coupling circuit Signal coupling circuits are used to send and receive communication commands for communication chips.

[0051] The signal coupling circuit includes a receiving-side AC coupling circuit and a transmitting-side AC coupling circuit.

[0052] The receiving-side AC coupling circuit is used to receive communication signals from the indoor unit on the Homebus bus and send them to the communication chip.

[0053] The AC coupling circuit on the receiving side is implemented by selecting appropriate resistors and capacitors to ensure that the signal received from the Homebus bus is filtered out of noise such as DC signals.

[0054] The receiving-side AC coupling circuit can be implemented using coupling circuits known in the prior art.

[0055] The AC coupling circuit on the transmitting side is used to receive signals from the communication chip and output communication signals to the indoor unit via the Homebus bus.

[0056] The AC coupling circuit on the transmitting side is implemented by selecting appropriate resistors and capacitors to ensure that the signal sent to the Homebus bus is filtered out of noise such as DC signals.

[0057] The AC coupling circuit on the transmitting side can be implemented using coupling circuits known in the prior art.

[0058] Bus drive loop Due to the technical requirements of the MM1192 communication chip, a bus drive circuit is also connected between bus A and bus B of the Homebus bus to drive and amplify the signals output by the communication chip at signal output terminals OUT / A and OUT / B.

[0059] The AMI communication signal from the Homebus (i.e., the signal shown at IV) is received by the Homebus interface on the receiving side of the communication chip and outputs a command with a duty cycle of 50% corresponding to the logic "0" in the AMI signal at its output terminal. The command with logic "1" in the AMI signal is transmitted synchronously (i.e., the output signal is the signal shown at V).

[0060] See Figure 3 It shows the ideal waveform during communication.

[0061] Within a period T of transmitting one bit, the signal with a duty cycle of 50% for the logic "0" in the corresponding AMI signal output by the communication chip is converted into an instruction with a duty cycle of 100% after passing through the demodulation circuit. The signal with a logic "1" in the corresponding AMI signal output by the communication chip is transmitted synchronously through the demodulation circuit (i.e., the output signal is the signal shown at VI) and received at the receiving end RXD.

[0062] That is, under ideal waveform conditions, the high level delay ∆t'=1 / 2T begins the instant the signal output by the communication chip changes from low level to high level.

[0063] After being processed by the outdoor main controller, a signal with a duty cycle of 100% (i.e., the signal shown at point I) and a clock signal (i.e., the signal shown at point II) are output at the signal transmission terminal TXD of the outdoor main controller and sent to the modulation circuit.

[0064] During the transmission of 1 bit, the low level corresponding to logic "0" in the transmission signal has a duty cycle of 100% and is converted into an instruction with a duty cycle of 50% through the modulation circuit. The high level corresponding to logic "1" in the transmission signal is transmitted synchronously through the modulation circuit (that is, the output signal is the signal shown at point III).

[0065] The III signal is input to the input terminal of the communication chip, and then encoded by the communication chip into the AMI signal on the Homebus bus. In this way, a cycle of data transmission and reception is completed.

[0066] As mentioned above, see Figure 3 The ideal waveform shown requires the master controller to decode it correctly. To ensure that the master controller can decode it correctly, the demodulation circuit needs to delay the high level by 1 / 2T when the communication chip output changes from low to high level.

[0067] However, in actual communication, see Figure 4 The AMI waveform on the bus is affected by the distributed capacitance, which will cause the communication waveform to be delayed. If the delay is kept at 1 / 2T, it will exceed the sampling time of one cycle, resulting in an incorrect sampling period and incorrect sampling data. Similarly, accurate decoding cannot be achieved.

[0068] Therefore, in some embodiments of this application, to ensure correct decoding at higher communication frequencies (e.g., 48kHz), it is necessary to design the delay time ∆t of the demodulation circuit at the moment the signal output by the communication chip changes from low level to high level.

[0069] See below. Figure 5 Describe the structure of the demodulation circuit.

[0070] In some embodiments of this application, the demodulation circuit includes a charging / discharging circuit, a first switch control circuit, and a second switch control circuit.

[0071] The output terminal of the charging and discharging circuit is connected to the output terminal OUT of the communication chip, and the on / off state of the first switch control circuit is controlled according to the output level of the output terminal OUT.

[0072] The output of the first switch control circuit controls the on / off state of the second switch control circuit.

[0073] The output terminal (i.e., Vout) of the second switch control circuit is connected to the signal receiving terminal RXD of the main controller.

[0074] In some embodiments of this application, combined with Figure 5 The charging and discharging circuit includes resistors R2, R3, and R4, capacitor C1, diode D1, and diode D2.

[0075] The anodes of diodes D1 and D2 are connected together, and both are connected to one end of resistor R3 and one end of capacitor C1.

[0076] The cathode of diode D1 is connected between the other end of resistor R3 and one end of resistor R2, and the other end of capacitor C1 is grounded.

[0077] One end of resistor R2 is connected to the first power supply VCC01 (e.g., +5V DC power supply), and the other end is connected to the cathode of diode D1 and the output terminal OUT of the communication chip.

[0078] The cathode of diode D2 and one end of resistor R4 are connected to the control terminal of the first switch control circuit, and the other end of resistor R4 is grounded.

[0079] The second switch control circuit is connected to the rear end of the first switch control circuit, forming a two-stage amplification drive.

[0080] The first switch control circuit and the second switch control circuit are both high-level conduction switch circuits, such as NPN transistors.

[0081] In this embodiment, the first switch control circuit is exemplified by NPN transistor Q1 and the second switch control circuit is exemplified by NPN transistor Q2.

[0082] The base b of transistor Q1 is connected between one end of resistor R4 and the cathode of switching diode D2. The emitter e of transistor Q1 is grounded. The collector c of Q1 is connected to pull-up resistor R5 and is also connected to the base b of transistor Q2. The pull-up power supply connected to pull-up resistor R5 is the second power supply VCC02 (e.g., +5V DC power supply).

[0083] The emitter e of transistor Q2 is grounded, and the collector c of Q2 is connected to pull-up resistor R9 and to the signal receiving terminal RXD of the main controller. The pull-up power supply connected to pull-up resistor R9 is the third power supply VCC03 (e.g., +5V DC power supply).

[0084] Taking the period of transmitting 1 bit as T, the demodulation circuit is used to convert the signal output by the communication chip into a binary output signal corresponding to the AMI signal, which is received by the receiver RXD of the main controller.

[0085] The working process of the demodulation circuit is described below.

[0086] (1) When the signal output at the output terminal OUT of the communication chip is high (i.e., the corresponding binary data is 1), diode D1 is not conducting while diode D2 is conducting.

[0087] The first power supply VCC01 starts charging capacitor C1 through resistors R2 and R3 until the voltage across capacitor C1 is VC1 = VF(D2) + VBE(Q1), at which point the charging ends.

[0088] Where VF(D2) is the forward voltage of diode D2, and VBE(Q1) is the voltage between the base (b) and emitter (e) of Q1. At this time, transistor Q1 is turned on.

[0089] With Q1 turned on, the base voltage of transistor Q2 is pulled low, Q2 is turned off, and the third power supply VCC03 outputs a high level to the receiver RXD of the main controller through resistor R8, realizing the equal transmission of high levels by the communication chip.

[0090] (2) When the signal output from the OUT terminal of the communication chip changes from high level to low level, capacitor C1 discharges through diode D1 to the OUT terminal of the communication chip until VC1=VF(D2), at which point transistor Q1 is turned off.

[0091] Because Q1 is turned off, the base voltage of transistor Q2 is pulled high, Q2 is turned on, and the receiver terminal RXD of the main controller outputs a low level, realizing the equal transmission of low levels by the communication chip.

[0092] (3) When the signal at the output terminal OUT of the communication chip changes from low level to high level, diode D1 does not conduct while diode D2 conducts.

[0093] The first power supply VCC01 starts charging capacitor C1 through resistors R2 and R3. Since Q1 will only turn on when the voltage VC1 on capacitor C1 is charged from VF(D2) to VF(D2)+VBE(Q1), a high level will be transmitted as described in part (1).

[0094] Therefore, by using the time ∆t during which the voltage VC1 is charged from VF(D2) to VF(D2)+VBE(Q1), the high level output of the communication chip is delayed to avoid interference from the signal, so that the receiver RXD of the main controller can correctly decode the communication signal.

[0095] The following will explain how to calculate time ∆t.

[0096] According to the RC circuit charging formula, VBE(Q1) = VCC01 × (1 - e (-∆t / τ) ), where τ=(R2+R3)×C1, can be obtained as follows: Δt=-(R2+R3)×C1×ln{1- VBE(Q1) / VCC01)}.

[0097] In some embodiments of this application, VCC01 = 5V. Therefore, the specific values ​​of R2, R3, C1 and VBE(Q1) need to be determined by the specific selection of the device. This will delay the high level by ∆t when the communication chip output changes from low level to high level, that is, extend the low level time by ∆t.

[0098] The value of ∆t is a key issue in improving decoding accuracy, and it is also the problem that this application needs to solve.

[0099] After knowing the value of ∆t, the values ​​of the devices in the charging and discharging circuits of the demodulation circuit can be determined, so that when the communication chip outputs a signal, the demodulated waveform can be output correctly. In this way, the receiver RXD of the main controller can collect accurate communication data.

[0100] In some embodiments of this application, the demodulation loop can start at the instant the output of the communication chip changes from low to high level, and delay the high level output of the communication chip for a first time (i.e., ∆t as described above).

[0101] In some embodiments of this application, the first time is determined based on the period T.

[0102] In some embodiments of this application, the design is based on the golden ratio division point, which is the product of half a cycle 1 / 2T and the golden ratio point.

[0103] For example, when the communication frequency is increased to 48kHz, the period T is 20.8μs.

[0104] Therefore, the first time interval can be 1 / 2 * 20.8 * 0.618 = 6.42 μs.

[0105] Using the magnitude of this first time interval and the formula described above, a demodulation circuit can be designed with R2=1kΩ, R3=10kΩ, and C1=0.0033μF.

[0106] A simulation source can be designed using simulation software, which can generate the same waveform as the signal corresponding to the binary data 0 output by the communication chip.

[0107] That is, during testing, the simulation source is connected to Figure 5 The OUT terminal in the middle outputs... Figure 6 The green lines represent the waveform. Figure 6 The waveform shown in purple is... Figure 5 The waveform output from the Vout terminal.

[0108] Tests showed that the delay time ∆t was 6.6 μs (see [link]). Figure 6 This is not much different from the 6.42μs calculated above.

[0109] In actual use, testing has shown that... Figure 7 The communication waveform in the text.

[0110] exist Figure 7 In the diagram, the pink waveform represents the AMI waveform (shown in IV), the blue waveform represents the waveform output by the communication chip (shown in V), and the green waveform (shown in VI) represents the waveform received on the receiver RXD of the main controller.

[0111] It can be tested that when the signal output by the communication chip changes from low level to high level, the delay at the high level is ∆t=6.5μs.

[0112] This result verifies that the design of the delay time ∆t and the demodulation circuit are correct, which can avoid interference from interference signals and improve the decoding accuracy of the main controller.

[0113] With accurate delay time ∆t, the software can more accurately read the sampling and reading of the waveform output from the demodulation circuit, thus effectively improving communication efficiency.

[0114] In some embodiments of this application, the first time can also be determined based on the period T and the maximum delay time on the Homebus bus.

[0115] The maximum delay time on the Homebus can be determined based on testing of multi-split air conditioning systems.

[0116] In some embodiments of this application, half a cycle corresponds to the delay time under the ideal waveform (see...). Figure 3 The maximum delay time (Δt') shown in the figure corresponds to the delay time of the waveform when the distributed capacitance on the bus is at its maximum.

[0117] To ensure good communication between communication nodes on the bus, in some embodiments of this application, the first time can be selected as the average of half a cycle and the maximum delay time.

[0118] For example, at a communication frequency of 48kHz, the period is 20.8μs.

[0119] See Figure 8 It provides the AMI communication waveforms of actual tests under a bus length of 1000 meters and 200 communication nodes. The pink one is the AMI waveform of the outdoor unit bus, and the green one is the AMI waveform of the indoor unit bus. The maximum delay time was tested to be 3.2μs.

[0120] Therefore, the first time can be calculated as (1 / 2*20.8μs+3.2μs) / 2=6.8μs.

[0121] This timeframe can also be used for the selection and design of components in the charging and discharging circuit of the demodulation loop, and can also improve decoding accuracy.

[0122] In some embodiments of this application, since the delay time begins from the change from low to high level output by the communication chip, the first time ∆t can be selected to be greater than 1 / 4T.

[0123] Furthermore, since it is a change from low to high level corresponding to 1 bit of binary data, the first time ∆t is less than 1 / 2T.

[0124] To avoid the sampling period exceeding the period, ∆t is not set to 1 / 2T in the first time step.

[0125] In some embodiments of this application, based on the range of values ​​for the first time ∆t as described above, the first time ∆t may also be selected from other values ​​within that range.

[0126] See Figure 9 When the correct delay time ∆t is given, the software can sample the correct reading, thus improving the decoding accuracy.

[0127] In some embodiments of this application, the application relates to communication between the indoor unit side and the outdoor unit side. In order to improve the communication quality between the outdoor unit system and the indoor unit system, and to increase the communication distance between the outdoor unit and the indoor unit, impedance matching between the transmitting side and the receiving side can also be considered.

[0128] Impedance matching is a working state with maximum power output. By designing the structure of the impedance matching circuit of the multi-split air conditioning communication system, high-quality communication can be achieved at high communication frequencies (e.g., 48KHz).

[0129] Furthermore, since the cable distribution parameters are also taken into account in some embodiments of this application, the impedance matching circuit can improve communication quality and communication distance at the same time.

[0130] The increased communication distance allows for an increase in the number of communication nodes on the Homebus, enabling stable communication at high frequencies (e.g., 48kHz) over long distances with multiple communication nodes.

[0131] In some embodiments of this application, the preliminary theoretical knowledge for designing the structure of the impedance matching circuit will be described first.

[0132] Impedance matching refers to a working state in which the load impedance and the internal impedance of the excitation source are matched to obtain the maximum power output.

[0133] The matching conditions are different for circuits with different characteristics.

[0134] In a purely resistive circuit, the output power is at its maximum when the load resistance equals the internal resistance of the excitation source. This operating state is called matching; otherwise, it is called mismatch.

[0135] When both the internal impedance of the excitation source and the impedance of the load contain reactive components, in order to maximize the power delivered to the load, the load impedance and the internal impedance of the excitation source must satisfy a conjugate relationship. That is, the resistive components must be equal, and the reactive components must be equal in magnitude but opposite in sign. The equivalent diagram of the expression RS + jXS = RL - jXL is shown. This matching condition is called conjugate matching. See [link to diagram]. Figure 10 .

[0136] Where RS represents the resistive component of the excitation source's internal impedance, XS represents the reactive component of the excitation source's internal impedance, RL represents the resistive component of the load impedance, XL represents the reactive component of the load impedance, and RS = RL.

[0137] Considering that the length of the bus is also a factor affecting the signal or energy, the concept of characteristic impedance is introduced.

[0138] Characteristic impedance is an inherent property of radio frequency transmission lines. Its physical meaning is the ratio of incident wave voltage to incident wave current, or the ratio of reflected wave voltage to reflected wave current, on the radio frequency transmission line.

[0139] When the ratio of voltage to current at various points along an RF transmission line is constant, the characteristic impedance remains unchanged. Therefore, for a cable of a fixed type used as a bus, its characteristic impedance remains constant.

[0140] For a transmission line with a known characteristic impedance, it is independent of frequency.

[0141] Based on existing technology, see Figure 11 Based on the theory of distributed parameters of the transmission line, we obtain the characteristic impedance model of the transmission line shown in the figure.

[0142] The characteristic impedance Z0 is expressed as follows: Z0 = sqrt[(R + jωL) / (G + jωC)].

[0143] Where R is the resistance per unit length of the transmission line, in Ω / m; L is the inductance per unit length of the transmission line, in H / m; G is the parallel conductance per unit length of the transmission line, in S / m; C is the parallel capacitance per unit length of the transmission line, in F / m; and Z0 is in Ω.

[0144] Generally, the values ​​of R and G are very small, and the characteristic impedance of the transmission line can be simplified as: Z0 = sqrt(L / C).

[0145] As can be seen from the above formula, the factors affecting characteristic impedance include dielectric constant, dielectric thickness, linewidth, and copper foil thickness.

[0146] The reflection coefficient ΓL can reflect the characteristics of the load (such as admittance, gain, transconductance), and ΓL is more useful when dealing with RF frequency issues.

[0147] As is known in the art, the reflection coefficient ΓL is defined as the ratio of the reflected wave voltage to the incident wave voltage, and the intensity of the load reflected signal depends on the degree of mismatch between the excitation source impedance and the load impedance.

[0148] The model for the reflection coefficient ΓL is shown in [reference]. Figure 12 It can be defined using the following expression: ΓL=Vrefl / Vinc=(ZL-Z0) / (ZL+Z0).

[0149] Where Z0 is the characteristic impedance and ZL is the load impedance, both in Ω. The load impedance ZL includes the resistive component RL and the reactive component XL.

[0150] A good system requires a small absolute value of the reflection coefficient, such as less than 1 / 3, in order to reduce signal reflection during communication, improve communication quality, and increase communication distance.

[0151] Based on the above, if the Homebus cable is selected as communication cable VCTF05, then the characteristic impedance Z0 is 75Ω.

[0152] When other cables are selected, the corresponding characteristic impedance will also vary depending on the cable.

[0153] For multi-split air conditioners, the transmission and reception of data between the indoor and outdoor units is bidirectional. That is, the outdoor unit will send data to the indoor unit through the bus, and the indoor unit will also send data to the outdoor unit through the bus. Therefore, the "excitation source" and the "load" are interchangeable. That is, the "excitation source" can act as both a source and a load at a specific time, and the same applies to the "load".

[0154] The purpose of good impedance matching is to ensure the efficient transfer of signal or energy from the "excitation source" to the "load".

[0155] Therefore, after taking into account the load impedance and characteristic impedance, we can establish as follows: Figure 13 The impedance matching circuit model is shown.

[0156] In a multi-split air conditioning system, as mentioned above, the characteristic impedance of the selected cable is Z0=75Ω.

[0157] See Figure 13 If we take the outdoor unit as the signal source in the outdoor unit system, that is, the outdoor unit system is the transmitting side system, then the reflection coefficient of the impedance matching circuit is (ZL-Z0) / (ZL+Z0).

[0158] If the indoor unit in the indoor unit system is taken as the signal source, that is, the indoor unit system is the transmitting side system, then the reflection coefficient of the impedance matching circuit is (ZS-Z0) / (ZS+R0).

[0159] Where ZL represents the indoor unit system-side terminal impedance, and ZS represents the outdoor unit system-side terminal impedance.

[0160] From the two reflection coefficients obtained above, it can be seen that the reflection coefficients are minimized and the impedance is best matched only when ZL=ZS=Z0.

[0161] That is, ZL=ZS=Z0=75Ω.

[0162] In some embodiments of this application, during debugging, it was found that the impedance matching circuit described above worked fine when the number of connected systems was small (e.g., less than 64 units), but when the number of connected systems exceeded 100 units, the waveform on the bus (i.e., Figure 14The label IV shown in the figure will also oscillate a lot, causing the master controller to be unable to decode correctly and reducing the communication quality.

[0163] Therefore, for long-distance communication, the distributed parameters of the communication cable also need to be considered. The circuit model of the communication cable can be found here. Figure 15 .

[0164] Depending on the type of communication cable selected, the resistive component (e.g., 0.03Ω / 1m), distributed inductance component (e.g., 0.32uH / 1m), and distributed capacitance component (e.g., 80pF / 1m) of the cable can be determined.

[0165] The resistive components in the cable do not affect impedance matching; the distributed capacitance in the cable causes signal delay, but has virtually no impact on signal impedance matching.

[0166] The key component in a cable is the distributed inductance on the signal line. According to the conjugate principle, since there is inductance on the signal line, its impedance matching circuit needs to use a capacitor to eliminate the influence of the inductance. That is, the inductive reactance of the inductor and the capacitive reactance of the capacitor are equal.

[0167] The inductive reactance of the inductor is 2πfL, where f is the communication frequency and L is the inductance.

[0168] The capacitive reactance of the capacitor is 1 / (2πfc), where c is the capacitance.

[0169] In some embodiments of this application, the communication frequency f can be selected as a communication frequency greater than 20KHz, for example, the communication frequency f is selected as 48KHz.

[0170] Choose a cable length of 1000 meters.

[0171] Based on the communication cable model mentioned above, the total distributed inductance L on the cable can be calculated: for example, 1000 * 0.32 = 320 (uH); Let 2πfL = 1 / (2πfc), then the total distributed capacitance c on the cable is calculated to be 34.4nF.

[0172] This distributed capacitance is placed on the Homebus bus to eliminate the effect of the distributed inductance L on impedance matching in the cable.

[0173] The specific location of the distributed capacitors can be arranged according to the position of the terminal impedance ZL / ZS calculated above.

[0174] As mentioned above, one of the outdoor unit system and the indoor unit system is the transmitting side system, and the other of the outdoor unit system and the indoor unit system is the receiving side system.

[0175] Note that the first terminating impedance is set on the transmitting side of the transmitting system, and the second terminating impedance is set on the receiving side of the receiving system.

[0176] See Figure 13 When the outdoor unit system is the transmitting side system and the indoor unit system is the receiving side system, the terminating impedance ZS is the first terminating impedance and the terminating impedance ZL is the second terminating impedance.

[0177] When the outdoor unit system is the receiving side system and the indoor unit system is the transmitting side system, the terminating impedance ZL is the first terminating impedance and the terminating impedance ZS is the second terminating impedance.

[0178] In some embodiments of this application, the transmitting side and the receiving side are relative terms; therefore, the first terminating impedance and the second terminating impedance are also relative terms.

[0179] As described above, in some embodiments of this application, in order to solve the impedance matching problem, terminating impedance and distributed capacitance are introduced. The arrangement of terminating impedance and distributed capacitance will be described below.

[0180] When testing the waveform of a communication signal, it was found that the following conditions were met when the settings of the first terminal impedance and the second terminal impedance were different.

[0181] That is, the first terminal impedance is located on the transmitting side of the transmitting communication node between the two ends of the transmitting communication node in the transmitting side system, and the second terminal impedance is located on the receiving side of the receiving communication node between the two ends of the receiving side system.

[0182] See Figure 1 In some embodiments of this application, the transmitting side system is an outdoor unit system, and the outdoor unit system includes forty outdoor units connected in sequence, which are numbered ODU1, ODU2, ..., ODU40 in sequence according to the direction of communication signal transmission.

[0183] The receiving side system is an indoor unit system, which includes 160 indoor units connected in sequence, numbered IDU1, IDU2, ..., IDU160 according to the direction of communication signal transmission.

[0184] At this time, the head outdoor unit of the outdoor unit system is ODU1, and the tail outdoor unit of the outdoor unit system is ODU40.

[0185] The head indoor unit of the indoor unit system is IDU1, and the tail indoor unit of the indoor unit system is IDU160.

[0186] In some embodiments of this application, the following condition is satisfied when the positions of the first terminating impedance and the second terminating impedance are different: The first terminating impedance is located on the transmitting side of any one of ODU2 to ODU39, and the second terminating impedance is located on the receiving side of any one of IDU2 to ODU159.

[0187] See also Figure 1 In some embodiments of this application, the transmitting side system is an indoor unit system. In this case, the head indoor unit of the indoor unit system is IDU160, and the tail indoor unit of the indoor unit system is IDU1.

[0188] The receiving side system is an outdoor unit system. At this time, the head outdoor unit of the outdoor unit system is ODU40, and the tail outdoor unit of the outdoor unit system is ODU1.

[0189] In some embodiments of this application, the following condition is satisfied when the positions of the first terminating impedance and the second terminating impedance are different: The first terminating impedance is located on the transmitting side of any one of IDU2 to ODU159, and the second terminating impedance is located on the receiving side of any one of ODU2 to ODU39.

[0190] In some embodiments of this application, the outdoor units at both ends of the outdoor unit system include a head outdoor unit and a tail outdoor unit, and the indoor units at both ends of the indoor unit system include a head indoor unit and a tail indoor unit, with the head and tail being relative terms.

[0191] The following provides various arrangements of the first and second terminating impedances.

[0192] Taking the transmitting side system as an outdoor unit system and the receiving side system as an indoor unit system as an example.

[0193] In some embodiments of this application, the first terminating impedance is set on the transmitting side of the outdoor unit located at the end of the plurality of outdoor units. For example, the first terminating impedance is set on the transmitting side of ODU1 or the transmitting side of ODU40.

[0194] The second terminating impedance is set on the receiving side of any indoor unit. For example, the second terminating impedance is set on the receiving side of any one of IDU1 to IDU160.

[0195] In some embodiments of this application, the first terminating impedance is set on the transmitting side of any outdoor unit, for example, the first terminating impedance is set on the transmitting side of any one of ODU1 to ODU40.

[0196] The second terminating impedance is set on the receiving side of the indoor unit located at the end of the multiple indoor units. For example, the second terminating impedance is set on the receiving side of IDU1 or the receiving side of IDU160.

[0197] Similarly, when the transmitting side system is an indoor unit system and the receiving side system is an outdoor system, the arrangement of the first and second terminating impedances is similar to that above, and will not be repeated here.

[0198] After debugging the waveform, it was found that the terminal impedance of the outdoor unit system can be divided into two equal impedances, thus improving the bus waveform effect.

[0199] Therefore, in some embodiments of this application, the outdoor unit system will be described.

[0200] In some embodiments of this application, when the outdoor unit system is a transmitting side system, the first terminal impedance includes a first transmitting terminal impedance and a second transmitting terminal impedance.

[0201] The first transmitting terminal impedance is set on the transmitting side of one of the head outdoor unit and the tail outdoor unit. For example, the first transmitting terminal impedance is set on the transmitting side of one of the head outdoor unit ODU1 and the tail outdoor unit ODU40.

[0202] The second transmitting terminal impedance is set on the transmitting side of the other of the head outdoor unit and the tail outdoor unit. For example, the second transmitting terminal impedance is set on the transmitting side of the other of ODU1 and ODU40.

[0203] The resistance values ​​of the first transmitting terminal impedance and the second transmitting terminal impedance are equal, and the resistance value of the two connected in parallel is equal to the resistance value of the first terminal impedance.

[0204] The second terminating impedance is set on the receiving side of the rear indoor unit. For example, the second terminating impedance is set on the transmitting side of the rear indoor unit IDU160.

[0205] In some embodiments of this application, when the outdoor unit system is a receiving side system, the second terminal impedance includes the first receiving terminal impedance and the second receiving terminal impedance.

[0206] The first receiving terminal impedance is set on the receiving side of one of the head outdoor unit and the tail outdoor unit. For example, the first receiving terminal impedance is set on the receiving side of one of the head outdoor unit ODU40 and the tail outdoor unit ODU1.

[0207] The second receiving terminal impedance is set on the receiving side of one of the head outdoor unit and the tail outdoor unit. For example, the first receiving terminal impedance is set on the receiving side of the other of the head outdoor unit ODU40 and the tail outdoor unit ODU1.

[0208] The resistance values ​​of the first receiving terminal impedance and the second receiving terminal impedance are equal, and the resistance value of the two connected in parallel is equal to the resistance value of the second terminal impedance.

[0209] The first terminating impedance is set on the transmitting side of the head indoor unit. For example, the first terminating impedance is set on the transmitting side of the head indoor unit IDU160.

[0210] After the terminating impedance is set up, the distributed capacitance C is designed to be connected in parallel with the terminating impedance.

[0211] In some embodiments of this application, the distributed capacitance C can be arranged in parallel with the first terminating impedance, see [link to relevant documentation]. Figure 17 .

[0212] In some embodiments of this application, the distributed capacitance C can be arranged in parallel with the second terminating impedance. (See also...) Figure 18 .

[0213] For example, the capacitance value of the distributed capacitance C is 34.4nF as calculated above.

[0214] In some embodiments of this application, the distributed capacitance C can also be arranged as a first distributed capacitance CS and a second distributed capacitance CL connected in parallel, see [link to relevant documentation]. Figure 16 .

[0215] The first distributed capacitor CS is connected in parallel with the first terminating impedance ZS, and the second distributed capacitor CL is connected in parallel with the second terminating impedance ZL.

[0216] The capacitance of the first distributed capacitor CS and the second distributed capacitor CL connected in parallel is equal to the capacitance of the distributed capacitor C.

[0217] In some embodiments of this application, it was found during testing that the bus waveform performance was good when the capacitance values ​​of the first distributed capacitor CS and the second distributed capacitor CL were equal (i.e., CS=CL).

[0218] In some embodiments of this application, as described above, since the first terminal impedance can be divided into a first transmitting terminal impedance and a second transmitting terminal impedance connected in parallel, the first distributed capacitance can be correspondingly divided into a first distributed capacitance I and a first distributed capacitance II.

[0219] The first distributed capacitance I is connected in parallel with the first transmitting terminal impedance, and the first distributed capacitance II is connected in parallel with the second transmitting terminal impedance.

[0220] The capacitance of the first distributed capacitor I is connected in parallel with the second distributed capacitor I, and the capacitance of the parallel connection is equal to the capacitance of the first distributed capacitor.

[0221] In some embodiments of this application, the capacitance value of the first distributed capacitor I and the capacitance value of the second distributed capacitor I are equal.

[0222] As mentioned above, the terminating impedance is calculated considering the characteristic impedance of the signal line, and the distributed capacitance is calculated considering the communication frequency and cable length. Therefore, an impedance matching circuit that considers the terminating impedance and distributed capacitance can improve the impedance matching when the communication signal is transmitted over a long distance, thereby improving the communication quality.

[0223] Furthermore, long-distance transmission allows for the deployment of more communication nodes along long cables, thus expanding the communication range.

[0224] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0225] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-split air conditioning communication system, characterized in that, include: Multiple outdoor units and multiple indoor units are connected to the Homebus bus, making the outdoor or indoor unit a communication node. The communication node includes: The master controller is used to control the communication nodes; A communication chip used to receive communication signals from the Homebus bus; The demodulation circuit is located between the communication chip and the main controller, and is used to convert the signal output by the communication chip into a binary output signal corresponding to the AMI signal on the Homebus bus. The demodulation circuit can synchronously transmit the signal output by the communication chip when the output of the communication chip is at a high level or changes from a high level to a low level. Furthermore, starting from the instant the output of the communication chip changes from low to high, the high level output by the communication chip is delayed for a first time. The first time t ranges from 0.25T < t < 0.5T, where T is the period required to transmit 1 bit of binary data.

2. The multi-split air conditioning communication system according to claim 1, characterized in that, The first time is determined based on the period, specifically as follows: The first time is the product of half of the cycle and the golden section point.

3. The multi-split air conditioning communication system according to claim 1, characterized in that, The first time is determined based on the period and the maximum delay time generated by the Homebus bus. The maximum delay time was determined by testing the multi-split air conditioning system.

4. The multi-split air conditioning communication system according to claim 3, characterized in that, The first time is the average of half of the cycle and the maximum delay time.

5. The multi-split air conditioning communication system according to claim 1, characterized in that, The demodulation circuit includes: The charging and discharging circuit receives the level output by the output terminal of the communication chip, and can delay the high level for the first time from the moment the output signal of the communication chip changes from low level to high level. The first switch control circuit, wherein the level output by the charging and discharging circuit controls the on / off state of the first switch control circuit; The second switch control circuit controls the on / off state of the second switch control circuit, and the output of the second switch control circuit is connected to the signal receiving terminal of the main controller.

6. The multi-split air conditioning communication system according to claim 1, characterized in that, The multi-split air conditioning communication system also includes: A receiving-side AC coupling circuit, connected to the receiving side of the communication chip, is used to receive the transmission signal from the other side on the Homebus bus and send it to the communication chip. The transmitting side AC coupling circuit is connected to the transmitting side of the communication chip and is used to receive signals from the communication chip and output communication signals to the Homebus bus.

7. The multi-split air conditioning communication system according to claim 1, characterized in that, The multi-split air conditioning communication system also includes: The bus drive circuit is used to drive and amplify the signal output by the communication chip at the signal output terminal.

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