Method and related apparatus for mask rule violation based on inversion lithography technology

Abstract

This application discloses a mask rule violation constraint method and related apparatus based on inversion lithography technology, relating to the field of mask rule checking and correction technology in inversion lithography. The method includes obtaining an initial mask corresponding to a target pattern; performing rule checks on the initial mask for width violation, spacing violation, and minimum area violation to determine mask rule violation regions in the initial mask; performing level set optimization on the mask rule violation regions in the initial mask to obtain the currently optimized mask; during the level set optimization process, applying violation correction for the mask rule violation regions and / or introducing mask rule penalty terms; violation correction includes width violation correction, spacing violation correction, and minimum area correction for the mask rule violation regions. This application, by applying violation correction for the mask rule violation regions and / or introducing mask rule penalty terms during the level set optimization process, can solve the mask rule violation problem without reducing imaging performance.

Description

Technical Field

[0001] This application relates to the field of mask rule inspection and correction technology in inversion lithography, and in particular to a method and related apparatus for mask rule violation constraint based on inversion lithography. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes and the shrinking of feature sizes, Optical Proximity Correction (OPC) technology, which has been significantly developed in photolithography and mask manufacturing, has seen remarkable advancements. OPC is prompting the industry to adopt and implement the concept of curved features to improve printability and pattern fidelity.

[0003] Inverse Lithography Technology (ILT), as an advanced form of OPC technology, plays a crucial role in improving image fidelity. The curved mask shapes generated by ILT offer potential advantages in improving print quality and pattern fidelity compared to traditional straight-line masks. However, the manufacturability of curved features in actual production depends on reliable Mask Rule Check (MRC). Therefore, addressing mask rule check violations is critical in OPC engines. Summary of the Invention

[0004] The purpose of this application is to provide a mask optimization method and related apparatus in inversion lithography, which can solve the problem of mask rule violation without reducing imaging performance.

[0005] To achieve the above objectives, this application provides the following solution:

[0006] Firstly, this application provides a mask rule violation constraint method based on inversion lithography technology, including:

[0007] Obtain the initial mask corresponding to the target image;

[0008] Perform rule checks on the initial mask for width violations, spacing violations, and minimum area violations to identify areas in the initial mask where mask rules are violated;

[0009] The mask rule violation areas in the initial mask are optimized using a level set to obtain the current optimized mask. During the level set optimization process, violation corrections for mask rule violation areas are applied and / or mask rule penalty terms are introduced. Violation corrections include width violation correction, spacing violation correction, and minimum area correction for mask rule violation areas.

[0010] Using the optimized mask as the initial mask, if the current iteration count reaches the preset iteration count, return to the step "Check the width and spacing violations of the initial mask"; if the current iteration count does not reach the preset iteration count, return to the step "Optimize the level set of the mask rule violation area in the initial mask to obtain the current optimized mask"; until the maximum iteration count is reached, the final optimized mask is obtained.

[0011] Secondly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described mask rule violation constraint method based on inversion lithography technology.

[0012] Thirdly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the above-described mask rule violation constraint method based on inversion lithography technology.

[0013] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0014] This application provides a mask rule violation constraint method and related apparatus based on inversion lithography technology. It employs a skeleton distance map-based method to detect mask rule violations. On one hand, during level set optimization, it can correct width violations, spacing violations, and minimum area violations in the violating regions. On the other hand, it can utilize mask rule penalty terms introduced during level set optimization for width and spacing violation regions to penalize mask rule violations and prevent the evolution of level sets with local rule violations. The mask rule violation constraint method of this application applies violation correction for mask rule violation regions and / or introduces mask rule penalty terms during level set optimization, resolving mask rule violations without degrading imaging performance, and obtaining a mask that conforms to the mask rules. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating a mask rule violation constraint method based on inversion lithography technology in Embodiment 1 of this application;

[0017] Figure 2 A schematic diagram of the target layout for two parallel contact holes provided in Embodiment 1 of this application;

[0018] Figure 3 A schematic diagram of the CTM optimized mask layout and wafer image with mode error as the objective function provided in Embodiment 1 of this application;

[0019] Figure 4 The application provided in Embodiment 1 of this application Figure 3 A schematic diagram showing the result of adaptive binarization of a medium grayscale mask;

[0020] Figure 5 This is a flowchart illustrating a mask rule violation constraint method based on inversion lithography technology, provided in Embodiment 2 of this application.

[0021] Figure 6 The mask rule violation correction scheme provided in Embodiment 2 of this application is illustrated by the following diagrams: intra-feature slicing of width and inter-feature pushing of spacing.

[0022] Figure 7 This is a flowchart illustrating a mask rule violation constraint method based on inversion lithography technology provided in Embodiment 3 of this application.

[0023] Figure 8 This is a schematic diagram of the initial level set function for constructing a binary mask and the initial mask corresponding to the level set function, provided in Embodiment 3 of this application.

[0024] Figure 9 This is a flowchart illustrating a mask rule violation constraint method based on inversion lithography technology, provided in Embodiment 4 of this application.

[0025] Figure 10 This is a schematic diagram illustrating the technical concept of a mask rule violation constraint method based on inversion lithography technology provided in Embodiment 4 of this application;

[0026] Figure 11 This is a schematic diagram of the regions without mask rule violation correction and with mask rule violation correction provided in Embodiment 4 of this application;

[0027] Figure 12 Schematic diagrams of the optimized synthetic masks under the four strategies provided in this application;

[0028] Figure 13 Provided for this application Figure 12 Schematic diagram of wafer imaging corresponding to the four types of composite masks;

[0029] Figure 14 Provided for this application Figure 13 A schematic diagram illustrating the convergence of the four optimization strategies in the diagram.

[0030] Figure 15 Provided for this application Figure 13 A schematic diagram of the mask rule penalty terms corresponding to the four optimization strategies. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Example 1

[0034] This embodiment provides a mask rule violation constraint method based on inversion lithography technology. Please refer to [link to relevant documentation]. Figure 1 Specific methods include:

[0035] Step 101: Obtain the initial mask corresponding to the target graphic.

[0036] The initial mask corresponding to the target pattern refers to the mask layout of the semiconductor device to be fabricated; the semiconductor device to be fabricated includes various semiconductor devices that constitute the target chip, such as MOSFET transistors, insulated gate bipolar transistors, resistors, capacitors, etc.

[0037] Generally, after the designer designs the basic structure of the target chip, the mask manufacturer breaks down the basic structure of the target chip to obtain the mask layout of each semiconductor device.

[0038] Step 102: Perform mask rule checks on the initial mask for width violations, spacing violations, and minimum area violations to determine the mask rule violation areas in the initial mask; for width violations and spacing violations, a method based on skeleton distance map is used to perform mask rule checks.

[0039] Step 103: Perform level set optimization on the mask rule violation areas in the initial mask to obtain the current optimized mask; during the level set optimization process, apply violation correction for the mask rule violation areas and / or introduce mask rule penalty terms; violation correction includes width violation correction, spacing violation correction, and minimum area correction for the mask rule violation areas.

[0040] Step 104: Using the optimized mask as the initial mask, if the current iteration count reaches the preset iteration count, return to step 102 "Check the width and spacing violations of the initial mask"; if the current iteration count does not reach the preset iteration count, return to step 103 "Optimize the level set of the mask rule violation areas in the initial mask to obtain the current optimized mask"; until the maximum iteration count is reached, the final optimized mask is obtained and applied to the target chip fabrication process.

[0041] Mask manufacturers prepare physical masks based on the final optimized mask. After the physical mask is prepared, chip manufacturers apply the physical mask to the target chip fabrication process.

[0042] The technical solution in this application is mainly applied to the OPC process of mask layout, and is aimed at the requirement that the OPC or ILT optimized mask layout needs to meet the manufacturability requirements of mask manufacturing; the optimized mask without mask rule violations (the final optimized mask) is prepared by mask data and then written by an electron beam lithography machine.

[0043] For example, the final optimized mask can be applied to wafer lithography (a core step in chip manufacturing) to transfer design patterns to a photoresist layer on a silicon wafer, for example, by exposure, where light (DUV / EUV) passes through the mask to form a pattern on the wafer.

[0044] As an optional implementation, step 101, obtaining the initial mask corresponding to the target graphic, specifically includes:

[0045] (1) Obtain the target image. Figure 2 An example is shown, which is a target layout with two parallel contact holes.

[0046] (2) Based on the target graphic, apply CTM optimization technology to obtain a grayscale mask with sub-resolution auxiliary graphics.

[0047] CTM optimization technique aims to optimize a given target pattern I0∈R. N×N Find the mask that minimizes the loss function. It can be defined as follows:

[0048]

[0049] Where m is the mask pattern. The model is a forward imaging model, including a projection optics model and an S-shaped constant threshold corrosion resistance model.

[0050] The loss function can be defined as: Pattern Error (PE), Weighted PE, and Edge Placement Error (EPE). In this application, PE is chosen as the loss function, and its definition is as follows:

[0051]

[0052] Among them, F PE This is the calculated pattern error, where M and N represent the number of rows and columns of the target graphic, respectively, and i and j are the row and column indices, respectively. Represents the target graphic, z i,j Represents a wafer image.

[0053] The grayscale mask obtained based on the above objective function, with sub-resolution assist features (SRAFs), is as follows: Figure 3 As shown.

[0054] (3) Binarize the grayscale mask to obtain a binarized mask; the binarized mask is the initial mask.

[0055] CTM-generated grayscale masks theoretically possess optimal performance; however, grayscale masks are not fabricable. Chrome-on-glass (COG) masks or phase-shift masks (PSMs) must undergo appropriate binarization or ternaryization. Therefore, an adaptive binarization method will be employed to select suitable thresholds for binarizing grayscale masks of different orders of SRAFs, resulting in binarized masks, such as... Figure 4 As shown, although the obtained binarized mask is manufacturable, it is no longer the best performing mask after CTM optimization. Therefore, further optimization is needed, and step 102 and subsequent steps are performed.

[0056] Further, in step 102, the initial mask is checked for width violations, spacing violations, and minimum area violations to determine the mask rule violation areas in the initial mask, specifically including:

[0057] (1) Generate a feature skeleton distance map based on the minimum width from the initial mask; if a pixel position in the feature skeleton distance map based on the minimum width is bright and the corresponding pixel position in the initial mask is dark, then the corresponding pixel position in the initial mask has a width violation; the pixel positions with width violations constitute the width violation region. Figure 4 The rectangle in (b) indicates the location where a width violation occurs in a mask rule violation.

[0058] (2) Based on the initial mask and minimum spacing, generate a feature skeleton distance map of the mask's inverted pixel image; if a pixel position in both the feature skeleton distance map of the mask's inverted pixel image and the initial mask is bright, then the corresponding pixel position in the initial mask exhibits a spacing violation; the pixel positions exhibiting spacing violations constitute the spacing violation region. Wherein, Figure 4 The rectangle in (a) indicates the location where a mask rule violation occurs due to a spacing violation.

[0059] (3) Determine the sum of pixel intensities of a certain feature in the initial mask; if the sum of pixel intensities is less than the minimum area, the corresponding feature in the initial mask will have a minimum area violation; the position of the feature pixel that has a minimum area violation constitutes the minimum area violation region.

[0060] Further, in step 103, when applying width violation correction for mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including:

[0061] During the level set optimization process, the width violation region in the initial mask is expanded using the sum of the minimum spacing and the width; the pixel positions of the expanded region in the initial mask are set to dark.

[0062] Further, in step 103, when applying spacing violation correction to mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including:

[0063] During the level set optimization process, the minimum spacing and the sum of the width are used to dilate the spacing violation areas in the initial mask; the pixel positions of the dilated areas in the initial mask are set to dark colors.

[0064] Further, in step 103, when applying minimum area correction for mask rule violation regions during level set optimization, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including:

[0065] During the level set optimization process, the patterns corresponding to the minimum area violation regions in the initial mask are deleted.

[0066] Further, in step 103, when a mask rule penalty term is introduced during the level set optimization process, level set optimization is performed on the mask rule violation areas in the initial mask to obtain the currently optimized mask, specifically including:

[0067] (1) Construct a mask rule penalty term for each pixel position in the current width violation area and / or spacing violation area.

[0068] The expression for the mask rule penalty term is as follows:

[0069]

[0070] in,

[0071]

[0072] In the formula, P MRC Represents the mask rule penalty term; (x1,y1) and (x2,y2) are the pixel positions in the width violation region and / or spacing violation region, respectively; ω(x1,y1,x2,y2) is a weight function used to determine the points involved in the integration; and These are the level set functions corresponding to points (x1, y1) and (x2, y2), respectively; d * This is the parameter value corresponding to the violation type. For spacing violations, d * =d min spacing For width violations, d * =d min width d min spacing d is the preset minimum spacing value. min width The minimum width is a preset value; k is a preset value, and k can be sufficiently large, for example, k = 1000. When (x1, y1) and (x2, y2) are located on the zero level sets of φ1 and φ2 respectively, the exponential term... and The exponential term reaches its maximum value, and its value decreases rapidly as these points deviate from the zero level set.

[0073] (2) Construct an objective function for level set optimization based on the mask rule penalty term.

[0074] (3) Perform level set optimization on the initial mask according to the objective function of level set optimization. When the number of level set optimization iterations reaches the preset number of iterations, the current optimized mask is obtained.

[0075] Example 2

[0076] This embodiment provides a mask rule violation constraint method based on inversion lithography technology. In this method, only mask rule violation correction means are used during the level set optimization process, without introducing mask rule penalty terms. Please refer to [link to relevant documentation]. Figure 5 Specific methods include:

[0077] Step 201: Obtain the initial mask corresponding to the target graphic.

[0078] For details of step 201, please refer to the relevant part of embodiment 1, namely the details of step 101.

[0079] Step 202: Perform mask rule checks on the initial mask for width violations, spacing violations, and minimum area violations to determine the mask rule violation areas in the initial mask; for width violations and spacing violations, a method based on skeleton distance map is used to perform mask rule checks.

[0080] For details of step 202, please refer to the relevant part of embodiment 1, that is, the details of step 102.

[0081] Step 203: Perform level set optimization on the mask rule violation regions in the initial mask to obtain the current optimized mask; during the level set optimization process, apply violation correction to the mask rule violation regions; violation correction includes width violation correction, spacing violation correction, and minimum area correction for the mask rule violation regions. The specific process of level set optimization is as follows: 1) Level set initialization; 2) Calculation of spatial image and gradient; 3) Iterative optimization process, where each iteration of level set optimization includes level set initialization, calculation of spatial image and gradient, and gradient-based update. Violation correction is mainly added during the optimization process, and is performed after every certain number of iterations (after gradient-based update).

[0082] During a single iteration, after checking for mask rule violations, there may be one or more of the following: width violation, spacing violation, and minimum area violation. When a violation of the corresponding type occurs, the corresponding violation correction scheme can be executed during the level set optimization process.

[0083] (1) When applying width violation correction for mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the current optimized mask, specifically including:

[0084] During the level set optimization process, the width violation region in the initial mask is expanded using the sum of the minimum spacing and the width; the pixel positions of the expanded region in the initial mask are set to dark.

[0085] Intra-feature segmentation correction strategy: Generate a feature skeleton distance map based on the minimum width. If the distance map is bright while the original mask is dark, this indicates a width violation. These violation regions are then dilated using the sum of the minimum spacing and the width. Next, the positions of these dilated regions in the original mask are set to dark.

[0086] (2) When applying spacing violation correction to mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including:

[0087] During the level set optimization process, the minimum spacing and the sum of the width are used to dilate the spacing violation areas in the initial mask; the pixel positions of the dilated areas in the initial mask are set to dark colors.

[0088] Feature offset correction strategy: Based on the minimum spacing, a feature skeleton distance map is generated from the inverted pixel map of the mask. If both the inverted pixel distance map and the original mask are bright, it indicates a spacing violation. These violation regions are then dilated using the sum of the minimum spacing and the width. Next, the positions of these dilated regions in the original mask are set to dark.

[0089] (3) When applying minimum area correction for mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including:

[0090] During the level set optimization process, the patterns corresponding to the minimum area violation regions in the initial mask are deleted.

[0091] Based on different mask rule parameters, respectively Figure 4 The MRC correction results of the binarized mask shown are as follows: Figure 6 As shown. Among them, Figure 6 (a) in the middle shows the target Figure 4 The feature-in-feature segmentation result for the width violation in (a). Figure 6 (b) in the middle shows the specific targets. Figure 4 The characteristic spacing violation results in (b) are shown.

[0092] Step 204: Using the optimized mask as the initial mask, if the current iteration count reaches the preset iteration count, return to step 202 "Check the width and spacing violations of the initial mask"; if the current iteration count does not reach the preset iteration count, return to step 203 "Optimize the level set of the mask rule violation areas in the initial mask to obtain the current optimized mask"; until the maximum iteration count is reached, the final optimized mask is obtained.

[0093] In this embodiment, in order to improve computational efficiency, a mask rule violation check can be performed after a certain number of loop iterations. When a region with a violation is detected, a violation correction scheme is applied to the violating region during the level set optimization process to correct the violation.

[0094] Example 3

[0095] This embodiment provides a mask rule violation constraint method based on inversion lithography technology. In this method, only a mask rule penalty term is introduced during the level set optimization process; no mask rule violation correction means are employed. Please refer to [link to relevant documentation]. Figure 7 Specific methods include:

[0096] Step 301: Obtain the initial mask corresponding to the target graphic.

[0097] For details of step 301, please refer to the relevant part of embodiment 1, namely the details of step 101.

[0098] Step 302: Perform mask rule checks on the initial mask for width violations, spacing violations, and minimum area violations to determine the mask rule violation areas in the initial mask; for width violations and spacing violations, a method based on skeleton distance map is used to perform mask rule checks.

[0099] For details of step 302, please refer to the relevant part of embodiment 1, that is, the details of step 102.

[0100] Step 303: Perform level set optimization on the mask rule violation areas in the initial mask to obtain the current optimized mask; during the level set optimization process, introduce a mask rule penalty term corresponding to the mask rule violation area into the objective function.

[0101] If several mask rule violations are detected, corresponding mask rule penalty terms are introduced into the objective function. Once a mask rule penalty term is added to the objective function, it remains a term in the objective function until the final optimized mask is obtained. This serves two purposes: firstly, to automatically optimize and correct the corresponding mask rule violation regions during the level set optimization process; and secondly, to constrain the corrected regions to prevent mask rule violations from recurring.

[0102] During the level set optimization process, when introducing a mask rule penalty term, level set optimization is performed on the mask rule violation areas in the initial mask to obtain the current optimized mask, specifically including:

[0103] (1) Construct a mask rule penalty term for each pixel position in the current width violation area and / or spacing violation area.

[0104] Since inverse lithography technology (ILT) is pixel-based, and so is the level set function, a mask rule penalty term was designed. Its function is either to resolve violations without correction, or to prevent violations from recurring after correction. The specific form is as follows:

[0105]

[0106] in,

[0107]

[0108] In the formula, ω(x1,y1,x2,y2) is a weight function used to determine the points participating in the integration; φ1 and φ2 are the level set functions corresponding to points (x1,y1) and (x2,y2), respectively, and k takes a sufficiently large value, for example, k = 1000. When (x1,y1) and (x2,y2) are located on the zero level sets of φ1 and φ2, respectively, the exponential term... and The exponential term reaches its maximum value, and its value decreases rapidly as these points deviate from the zero level set.

[0109] (2) Construct an objective function for level set optimization based on the mask rule penalty term.

[0110] (3) Perform level set optimization on the initial mask according to the objective function of level set optimization. When the number of level set optimization iterations reaches the preset number of iterations, the current optimized mask is obtained.

[0111] The initial level set function φ and initial mask used for inversion lithography, such as Figure 8 As shown.

[0112] Step 304: Using the optimized mask as the initial mask, if the current iteration count reaches the preset iteration count, return to step 302 "Check the width and spacing violations of the initial mask"; if the current iteration count does not reach the preset iteration count, return to step 303 "Optimize the level set of the mask rule violation areas in the initial mask to obtain the current optimized mask"; until the maximum iteration count is reached, the final optimized mask is obtained.

[0113] The specific framework of the level set optimization method is as follows:

[0114] (1) The mapping relationship between the level set function φ and the mask m is defined as follows:

[0115]

[0116] Here, r represents the spatial coordinates (x, y). The mask profile is defined as the zero level set, i.e., φ(r) = 0. Therefore, mask optimization can be transformed into the evolution of the level set function.

[0117] (2) The evolution of the level set function is controlled by the following formula:

[0118]

[0119] in, It is the gradient, φ t It is the derivative with respect to the artificial time t. It is a velocity function perpendicular to the surface.

[0120] (3) The standard form of the Hamilton-Jacobi equation (HJE) is as follows:

[0121] φ t +H(x,y,t,φ x ,φ y ) = 0,

[0122] Where, φ x ,φ y These are the partial derivatives with respect to x and y. Solving the equations typically requires spatial discretization using the upwind scheme Essentially Non-Oscillatory (ENO) or Weighted Essentially Non-Oscillatory (WENO) method, and time discretization using the Total Variation Diminishing-Runge-Kutta (TVD-RK) method. In the simulation, the fifth-order accurate WENO method and the first-order accurate TVD-RK method were used. The semi-discrete form of the equations is defined as:

[0123]

[0124] in, It is a Lipschitz continuous monotonic flux consistent with H. Flux functions include the Godunov scheme, Lax-Friedrich scheme, Local Lax-Friedrichs scheme, Roe scheme, Engquist-Osher scheme, and Lax–Wendroff scheme. In this invention, the Godunov scheme is selected for simulating the process. These are the derivatives calculated using the right-biased template and the left-biased template, respectively. The definition is similar. H represents two different forms of the flux function, where H represents the original form of the flux. It represents the Lipschitz continuous monotonic flux consistent with H, and is a discretized or approximate form.

[0125] In this embodiment, to improve computational efficiency, mask rule violations can be checked after several iterations. When a violation is detected, a corresponding mask rule penalty term is added to the objective function of the level set optimization. Then, level set optimization is performed based on the modified objective function. During the iteration of level set optimization, mask violation regions are automatically optimized and corrected. The mask obtained after the level set optimization process is completed serves as the initial mask, and the next iteration is performed, i.e., the level set optimization process is re-executed based on the current initial mask. By intermittently checking for violations and continuously executing the level set optimization process until the preset maximum number of iterations is reached, the final optimized mask is obtained.

[0126] Example 4

[0127] This embodiment provides a mask rule violation constraint method based on inversion lithography technology. In this method, both a mask rule penalty term and a mask rule violation correction method are introduced during the level set optimization process. Please refer to [link to relevant documentation]. Figure 9 and Figure 10 Specific methods include:

[0128] Step 401: Obtain the initial mask corresponding to the target graphic.

[0129] For details of step 401, please refer to the relevant part of embodiment 1, namely the details of step 101.

[0130] Step 402: Perform mask rule checks on the initial mask for width violations, spacing violations, and minimum area violations to determine the mask rule violation areas in the initial mask; for width violations and spacing violations, a method based on skeleton distance map is used to perform mask rule checks.

[0131] For details of step 402, please refer to the relevant part of embodiment 1, that is, the details of step 102.

[0132] Step 403: Perform level set optimization on the mask rule violation areas in the initial mask to obtain the current optimized mask; during the level set optimization process, apply violation correction for the mask rule violation areas and / or introduce mask rule penalty terms; violation correction includes width violation correction, spacing violation correction, and minimum area correction for the mask rule violation areas.

[0133] Step 404: Using the optimized mask as the initial mask, if the current iteration count reaches the preset iteration count, return to step 402 "Check the width and spacing violations of the initial mask"; if the current iteration count does not reach the preset iteration count, return to step 403 "Optimize the level set of the mask rule violation areas in the initial mask to obtain the current optimized mask"; until the maximum iteration count is reached, the final optimized mask is obtained.

[0134] In this embodiment, to improve computational efficiency, mask rule violations can be checked after several iterations. Once a violation is detected, a violation correction operation is performed during level set optimization, and a penalty term for the violation region is added to the objective function. This penalty term is primarily added when calculating the gradient and loss during the entire level set optimization process (once before optimization and again during each iteration), specifically calculating the magnitude of the penalty term and its gradient with respect to the level set function. The violation correction operation during level set optimization can be performed once after several iterations.

[0135] After checking for mask rule violations, one or more of the following may be found: width violation, spacing violation, and minimum area violation. If a violation of the corresponding type occurs, the corresponding violation correction scheme can be executed.

[0136] (1) When applying width violation correction for mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the current optimized mask, specifically including:

[0137] During the level set optimization process, the width violation region in the initial mask is expanded using the sum of the minimum spacing and the width; the pixel positions of the expanded region in the initial mask are set to dark.

[0138] (2) When applying the spacing violation correction for mask rule violation regions during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the current optimized mask, specifically including:

[0139] During the level set optimization process, the minimum spacing and the sum of the width are used to dilate the spacing violation areas in the initial mask; the pixel positions of the dilated areas in the initial mask are set to dark colors.

[0140] (3) When applying minimum area correction for mask rule violation regions during the level set optimization process, mask optimization is performed on the mask rule violation regions in the initial mask to obtain the current optimized mask, specifically including:

[0141] During the level set optimization process, the patterns corresponding to the minimum area violation regions in the initial mask are deleted.

[0142] (4) When a mask rule penalty term is introduced during the level set optimization process, level set optimization is performed on the mask rule violation areas in the initial mask to obtain the current optimized mask, specifically including:

[0143] 1) Build a mask rule penalty term for each pixel location in the current width violation area and / or spacing violation area.

[0144] Penalty term for mask rule in curve construction:

[0145] The Euclidean distance between two points (x1, y1) and (x2, y2) is expressed as:

[0146]

[0147] Define the regularization term as:

[0148]

[0149] By comparing the distance d with d * The penalty is imposed by comparison, where d * This is the parameter value corresponding to the violation type, which appears in the region containing (x1, y1) and (x2, y2). Therefore, for spacing violations, d * =d min spacing For width violations, d * =d min width In a certain violation area, if the distance d between two feature contour points is less than d... * This indicates a violation of mask manufacturing rules, and ρ will grow exponentially. Conversely, if d between two feature contour points exceeds d... * If the result is 0, then it is guaranteed to comply with the rules.

[0150] The calculation of ρ(x1,y1,x2,y2) depends on whether corrections have been made at the violation locations. For masks that have not yet been corrected, the area to be penalized is the violation area of ​​the initial mask, such as... Figure 11 As shown in (a) and (b) in the figure. For a mask that has already undergone skeleton-based mask rule violation correction, the region to be penalized refers to the corrected region corresponding to the initial mask violation region, such as... Figure 11 As shown in (c) and (d) in the figure.

[0151] Figure 11 This shows the regions where mask rule violations were not corrected and those where they were corrected, i.e., the regions where penalties were applied. Figure 11 (a) and Figure 11 (b) shows the locations of spacing and width violations that were not corrected for mask rule violations. Figure 11 (c) and Figure 11 (d) in the figure shows the results after mask rule violation correction and the results after correction. Figure 11 (a) and Figure 11 The corresponding position is violated in (b) of the text.

[0152] 2) Construct an objective function for level set optimization based on the mask rule penalty term.

[0153] 3) Perform level set optimization on the initial mask according to the objective function of level set optimization. When the number of level set optimization iterations reaches the preset number of iterations, the current optimized mask is obtained.

[0154] In this application, the effectiveness of the constraint methods proposed in the above embodiments is evaluated by cross-applying mask rule violation correction and mask rule penalty terms. Specifically, four strategies are given as follows:

[0155] (a) No mask rule violation correction is performed, but mask rule penalty items are included, which are used to resolve mask rule violation issues;

[0156] (b) Neither mask rule violation correction nor mask rule penalty items are included;

[0157] (c) The correction includes a mask rule penalty, which is used to prevent mask rule violations from occurring again in areas that have already been corrected;

[0158] (d) Correction is performed but does not include mask rule penalties.

[0159] The optimization results for the above four scenarios are as follows: Figure 12 , Figure 13 , Figure 14 and Figure 15 As shown.

[0160] Figure 12 The optimized synthetic masks under the above four strategies are shown, from Figure 12 As can be seen in (a), without mask rule violation correction but with the addition of a mask rule penalty term, the width and spacing violations are resolved, and feature dilation and feature merging are successfully completed. Figure 12 As can be seen from (b) above, even without mask rule violation correction or the addition of mask rule penalty terms, the optimized mask still suffers from a large number of mask rule violations; from Figure 12As can be seen from (c), the mask after both mask rule violation correction and the addition of a mask rule penalty term retains the previous corrected features and does not have any mask rule violation issues; from Figure 12 As can be seen from (d), the mask optimized by only correcting mask rule violations but without adding mask rule penalty terms still retains the previous corrected features, but a small number of mask rule violations still exist. To address these specific issues, it is necessary to analyze the mask rule penalty term curve.

[0161] Figure 13 Showing Figure 12 Wafer imaging corresponding to four synthetic masks. Figure 14 for Figure 13 The convergence of the four optimization strategies is shown. Figure 14 The stability of level set optimization can be proven. All four strategies converge to an acceptable PE loss. In these cases, when neither skeleton-based MRC correction nor mask rule penalty terms are applied during level set optimization, Figure 13 In (b), the PE reaches a minimum of 36.9657, which is quite normal considering the fewer constraints in free-form masks. It can be observed that the pattern fidelity as PE is comparable, indicating that the imaging performance is not affected by incorporating the mask rule penalty term.

[0162] Figure 15 for Figure 13 The mask rule penalty terms corresponding to the four optimization strategies. Figure 15 It clearly shows that, in Figure 13 In cases (a) and (c) where a mask rule penalty term is present, the penalty term eventually converges to 0 regardless of whether skeleton-based MRC correction is applied, indicating that the violation has been resolved or prevented. In contrast, when no penalty term is included, the value of the mask rule penalty term does not disappear, meaning... Figure 13 In (b), there is a violation of the masking rule, or the violation recurs in a previously corrected position. From the above analysis, it can be seen that the masking rule penalty term proposed in this invention consistently performs well in constraining or resolving masking rule violations.

[0163] Based on inversion lithography, this application first generates a grayscale mask with SRAFs using CTM and then adaptively binarizes the mask. Next, it introduces correction schemes for width violation and spacing violation. Then, it proposes an MRC constraint method, namely a mask rule penalty term. Finally, the penalty term is added to the level set optimization process, and cross-validation of different strategies shows that the method effectively solves the mask rule violation problem while ensuring imaging quality.

[0164] This application proposes a constraint method to ensure that curve features conform to mask rule checks. It employs a skeleton distance map-based approach to detect and correct mask rule violations. Furthermore, during the level set-based optimization process, a mask rule penalty term with the mask contour as the distance metric is introduced for each correction to prevent the evolution of level sets with local rule violations. This constraint method can penalize mask rule violations and resolve the problem without degrading imaging performance.

[0165] For the same or similar parts among the above embodiments, please refer to each other.

[0166] Example 5

[0167] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the above-described mask rule violation constraint method based on inversion lithography technology.

[0168] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described mask rule violation constraint method based on inversion lithography technology.

[0169] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0170] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for mask rule violation based on inversion lithography technology, characterized in that, include: Obtain the initial mask corresponding to the target image; The initial mask corresponding to the target pattern refers to the mask layout of the semiconductor device to be fabricated; The initial mask is checked for width violations, spacing violations, and minimum area violations to identify areas where mask rules are violated. For width and spacing violations, a method based on skeleton distance maps is used for mask rule checks. The level set of the regions in the initial mask that violate the mask rules is optimized to obtain the current optimized mask; During the level set optimization process, violation correction of mask rule violation regions and introduction of mask rule penalty terms are applied. When the number of level set optimization iterations reaches the target number of iterations, the current optimized mask is obtained. Violation correction includes width violation correction, spacing violation correction, and minimum area correction of mask rule violation regions. Alternatively, a mask rule penalty term can be introduced during the level set optimization process; Using the optimized mask as the initial mask, if the current loop iteration count is the preset check loop iteration count, return to the step "Check the initial mask for width and spacing violations"; If the current loop iteration count is not the preset check loop iteration count, return to the step "perform level set optimization on the mask rule violation area in the initial mask to obtain the current optimized mask", until the maximum loop iteration count is reached to obtain the final optimized mask; Specifically, when a mask rule penalty term is introduced during the level set optimization process, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the current optimized mask, including: For each pixel location in the current width violation area and / or spacing violation area, construct a mask rule penalty term; Construct an objective function for level set optimization based on the aforementioned mask rule penalty term; Based on the objective function of level set optimization, level set optimization is performed on the initial mask. When the number of level set optimization iterations reaches the preset number of iterations, the current optimized mask is obtained. The expression for the mask rule penalty term is as follows: in, ; ； In the formula, This indicates the penalty item for the masking rule; and The pixel positions in the width violation area and / or spacing violation area, respectively; It is a weighting function; and They are points and The corresponding level set function; These are parameter values ​​corresponding to the violation type. For example, for spacing violations, For width violations, , This is the preset minimum spacing value. This is the preset minimum width value; This is the preset value.

2. The mask rule violation constraint method based on inversion lithography technology according to claim 1, characterized in that, Obtain the initial mask corresponding to the target image, specifically including: Obtain the target image; Based on the target image, a grayscale mask with sub-resolution auxiliary images is obtained by applying CTM optimization technology; The grayscale mask is binarized to obtain a binarized mask; the binarized mask is the initial mask.

3. The mask rule violation constraint method based on inversion lithography technology according to claim 1, characterized in that, The initial mask is checked for width violations, spacing violations, and minimum area violations to identify areas of mask rule violations within the initial mask. Specifically, this includes: Generate a feature skeleton distance map based on the minimum width from the initial mask; If a pixel in the feature skeleton distance map based on the minimum width is bright, and the corresponding pixel in the initial mask is dark, then the corresponding pixel in the initial mask has a width violation; the pixel position with the width violation constitutes the width violation region. Based on the initial mask and minimum spacing, generate a feature skeleton distance map of the mask inverted pixel map; If a pixel position in both the feature skeleton distance map of the inverted pixel image of the mask and the initial mask is a bright color, then the corresponding pixel position in the initial mask has a spacing violation; the pixel position with the spacing violation constitutes the spacing violation region. Determine the sum of pixel intensities of a certain feature in the initial mask; if the sum of pixel intensities is less than the minimum area, then the corresponding feature in the initial mask has a minimum area violation; the location of the feature pixel with the minimum area violation constitutes the minimum area violation region.

4. The mask rule violation constraint method based on inversion lithography technology according to claim 2, characterized in that, When applying width violation correction to mask rule violation regions during level set optimization, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including: During the level set optimization process, the width violation region in the initial mask is expanded using the sum of the minimum spacing and the width; the pixel positions of the expanded region in the initial mask are set to dark.

5. The mask rule violation constraint method based on inversion lithography technology according to claim 2, characterized in that, When applying spacing violation correction to mask rule violation regions during level set optimization, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the currently optimized mask, specifically including: During the level set optimization process, the minimum spacing and the sum of the width are used to dilate the spacing violation areas in the initial mask; the pixel positions of the dilated areas in the initial mask are set to dark colors.

6. The mask rule violation constraint method based on inversion lithography technology according to claim 2, characterized in that, When applying minimum area correction for mask rule violation regions during level set optimization, level set optimization is performed on the mask rule violation regions in the initial mask to obtain the current optimized mask, specifically including: During the level set optimization process, the patterns corresponding to the minimum area violation regions in the initial mask are deleted.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the mask rule violation constraint method based on inversion lithography technology as described in any one of claims 1-6.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the mask rule violation constraint method based on inversion lithography technology as described in any one of claims 1-6.

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