An intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method

Abstract

The application provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design. The system comprises an AXI interconnection matrix module provided with a crossbar switch, a master port and a slave port, wherein the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in a 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; an intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and a dynamic power management module adjusts the power consumption state according to a global power optimization signal and a local optimization signal. The application reduces the overall power consumption of the system on chip, and enhances the stability and efficiency of data transmission.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design technology, specifically relating to an intelligent clock-gated NoC system based on AXI interconnect and a dynamic power consumption management method. Background Technology

[0002] With the development of the integrated circuit industry, the integration level of System-on-a-Chip (SoC) is becoming increasingly higher. Multi-core processors, mobile devices, and automotive electronics are placing higher demands on the energy efficiency of SoCs. Traditional bus architectures are gradually being replaced by Network-on-Chip (NoC) due to bandwidth and latency issues. However, the introduction of NoC leads to an increase in the number of routers and links, resulting in a significant increase in dynamic power consumption (e.g., clock network switching) and static power consumption (e.g., leakage current), becoming a key issue restricting the design of high-performance SoCs.

[0003] While static clock gating and dynamic voltage regulation can reduce power consumption to some extent, they cannot adapt to dynamic load changes in real time. For example, the commonly used SMART-PG solution shuts down idle components under low load, but struggles to respond quickly to sudden traffic surges, leading to performance degradation. Tulip designs reduce power consumption by optimizing redirection logic, but sacrifice routing flexibility, limiting their applicability in complex application scenarios. Furthermore, existing routing optimization schemes (such as topology adaptive adjustment) can reduce power consumption, but they typically come with significant hardware overhead and struggle to maintain high efficiency under varying network load conditions.

[0004] Therefore, there is an urgent need for a dynamic, adaptive low-power NoC solution that can achieve intelligent power management while ensuring high performance. Summary of the Invention

[0005] In a first aspect, embodiments of this application provide an intelligent clock gating NoC system based on AXI interconnect, including an AXI interconnect matrix module, a 2D Mesh network module, an intelligent clock gating module, and a dynamic power management module;

[0006] The AXI interconnect matrix module is equipped with a crossbar switch, at least one master port and several slave ports. The master port and slave ports are connected to the crossbar switch via the AXI bus.

[0007] The 2D Mesh network module consists of a network array of M×N router nodes. Each router node has a local port and four peripheral ports in the outer direction. Each router node connects to adjacent router nodes through the peripheral ports using the AXI bus.

[0008] The slave ports of the AXI interconnect matrix module include Type I slave ports and Type II slave ports; the AXI interconnect matrix module is connected to the core components through the master port or Type I slave port, and the 2D Mesh network module is connected to the Type II slave port.

[0009] The local port connection of the 2D Mesh network module has auxiliary components;

[0010] The intelligent clock gating module monitors the channel traffic of the AXI interconnect matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls the clock signals of the AXI interconnect matrix module and the 2D Mesh network module.

[0011] The dynamic power management module adjusts the power consumption status of the AXI interconnect matrix module and the 2D Mesh network module based on the global power optimization signal and the local optimization signal.

[0012] Furthermore, the AXI interconnect matrix module includes an arbitration controller and a channel controller;

[0013] The arbitration controller uses a weighted round-robin arbitration algorithm to determine the priority of request events, and dynamically allocates bandwidth to the corresponding slave port according to the determined priority, ensuring that the bandwidth of the slave port meets at least the set proportion of the maximum bandwidth of the channel to which it belongs;

[0014] Dynamic bandwidth allocation ensures that the bandwidth of a port meets at least 20% of the maximum bandwidth of its channel.

[0015] The channel controller performs ECC verification on the data transmitted between the internal ports of the AXI interconnect matrix module according to the preset service level.

[0016] Furthermore, the four peripheral ports of the 2D Mesh network module are interconnected with adjacent router nodes via the AXI bus, and the network array of the 2D Mesh network module forms horizontal and vertical physical links.

[0017] The horizontal physical link uses P parallel AXI channels, and the vertical physical link uses Q parallel AXI channels, where P > Q;

[0018] Each peripheral port supports at least two virtual channels;

[0019] The router node corresponding to the peripheral port in one direction of the 2D Mesh network module is designated as the ingress router node, and each ingress router node is connected to a Type II slave port of the AXI interconnect matrix module.

[0020] Furthermore, the routing nodes of the 2D Mesh network module are configured with deterministic routing policies, cache prefetching logic, and self-healing routing policies.

[0021] The deterministic routing policy is configured as follows:

[0022] In the network array, routes are first routed to the target column according to the horizontal physical link, and then routed to the target routing node according to the vertical physical link;

[0023] The cache prefetch logic is configured as follows:

[0024] Monitor the local access history of the router node and record the address sequence of the most recent N accesses;

[0025] The prefetch step is dynamically calculated based on the cache miss rate (miss_rate).

[0026] prefetch_step = round(K * (miss_rate)^(-α));

[0027] Where K and α are configurable parameters;

[0028] When the cache utilization rate is lower than the threshold, a prefetch operation is triggered and a prefetch request is sent to the target router.

[0029] The self-healing routing policy is configured as follows:

[0030] Periodically perform link bit error rate tests to detect faulty links;

[0031] When a link failure in a certain direction is detected, update the routing table redirection policy of the local router node:

[0032] If the lateral physical link fails, the default lateral traffic will be redirected to the upper or lower level.

[0033] If the vertical physical link fails, the detour path on the left or right will be selected first.

[0034] Fault information is synchronized to neighboring router nodes via the Neighbor Status Broadcast Protocol.

[0035] Furthermore, the clock domain controlled by the intelligent clock gating module includes:

[0036] The channel clock of each slave port within the AXI interconnect matrix;

[0037] The internal logical clock of the router node in the 2D Mesh network module;

[0038] Transmission clocks for horizontal and vertical physical links between router nodes;

[0039] The router node's virtual channel buffer and arbitrator clock;

[0040] Each clock also has a bypass clock tree;

[0041] The intelligent clock gating module includes:

[0042] The real-time monitoring unit monitors the packet arrival rate, router node buffer utilization, and the number of invalid cycles of the AXI handshake signal, and triggers clock gating decisions when the threshold is met.

[0043] The clock gating decision unit filters and synchronizes the raw signal of the monitoring data, compares it with the gating conditions of the preset threshold, and generates a preliminary gating enable signal when the gating conditions are met. The preliminary gating enable signal and the external forced wake-up signal are combined with an AND gate to generate the final gating signal.

[0044] The clock control execution unit performs clock shut-off or clock-on for the corresponding clock according to the final gating signal. When a data packet is detected arriving on the channel where the clock is shut off, the bypass clock tree of the corresponding clock is activated.

[0045] Furthermore, the dynamic power management module includes:

[0046] The global voltage regulation unit responds to the global power optimization signal and uniformly adjusts the operating voltage of the AXI interconnect module and the 2D Mesh network module.

[0047] The local voltage regulation unit, in response to a local optimization signal, independently regulates the following supply voltages:

[0048] The power supply voltage of each slave port in the AXI interconnect matrix;

[0049] The power supply voltage of a single router node in a 2D Mesh network module;

[0050] The voltage and frequency coordination control unit synchronously adjusts the clock frequency of the corresponding module during voltage regulation.

[0051] Furthermore, the core components include the CPU, NPU, and memory controller;

[0052] Auxiliary components include the GPU, PCIe peripherals, and USB peripherals.

[0053] Secondly, embodiments of this application also provide a dynamic power management method for an AXI interconnect-based intelligent clock-gated NoC system based on the first aspect, comprising the following steps:

[0054] S1. Real-time acquisition of data traffic from each slave port in the AXI interconnect matrix module, periodic acquisition of data load from each router node in the 2D Mesh network module, and statistical analysis of data transmission time intervals in each virtual channel to obtain global load and idle time of local functional units; the local functional units include each slave port in the AXI interconnect matrix module, each router node in the 2D Mesh network module, and each virtual channel;

[0055] S2. When the global load is lower than the first threshold, a global power optimization signal is triggered to reduce the operating voltage, and when the idle time of a local functional unit exceeds a set period, a local optimization signal is generated.

[0056] S3. The dynamic power management module adjusts the supply voltage according to the global power optimization signal and adjusts the clock frequency synchronously.

[0057] S4. The intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, and restores the clock and voltage through the bypass clock tree of the corresponding local functional unit when a new data transmission request is detected.

[0058] Furthermore, the specific steps of step S2 are as follows:

[0059] S21. Based on the data traffic collected from each slave port in the AXI interconnect matrix module, calculate the average bandwidth utilization of all slave ports in the AXI interconnect matrix module. When the average bandwidth utilization is less than the first set proportional threshold for N consecutive cycles, activate the global power optimization signal.

[0060] S22. Based on the data load of each router node and the data transmission time interval in each virtual channel, calculate the buffer utilization and data transmission time interval in the virtual channel independently for each router node;

[0061] If the buffer utilization rate is less than the second set ratio threshold for M consecutive cycles, the local optimization signal of the corresponding router node is activated.

[0062] If there is no data transmission in the virtual channel for P consecutive cycles, activate the local optimization signal of the corresponding router node;

[0063] S23. When the global power optimization signal conflicts with the local optimization signal, the global optimization signal shall be given priority.

[0064] The specific steps of step S3 are as follows:

[0065] S31. Preset voltage adjustment step size;

[0066] S32. The dynamic power management module responds to the global power optimization signal and performs voltage regulation according to the voltage regulation step size, and blocks the global power voltage optimization signal for a set time period after voltage regulation;

[0067] S33. Perform frequency adjustment on the clock according to the following frequency synchronization adjustment formula:

[0068]

[0069] in, Indicates the adjusted clock frequency. Indicates the clock frequency before adjustment. This indicates the adjusted voltage. This indicates the voltage before adjustment;

[0070] In step S4, the intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, only shutting down the clock logic while retaining the power supply to the clock register;

[0071] When a data packet is detected arriving on a channel with a clock off, the bypass clock tree of the corresponding clock is first activated to perform data transmission, then the operating voltage of the corresponding clock is restored, and finally the main clock tree of that clock is unlocked.

[0072] Furthermore, it also includes the following steps:

[0073] Core component communication always occurs via a direct connection path through the AXI interconnect matrix module;

[0074] After the core components and auxiliary components communicate through the AXI interconnection matrix module and enter the entry router node of the 2D Mesh network module, they perform a jump according to the deterministic routing policy. When a routing failure occurs, a self-healing routing policy is executed to determine a new target router node.

[0075] When the clock of the new target router node is in a clock-off gated state, the gated state of the target router node is automatically released;

[0076] When the self-healing routing policy is executed, the router node on the bypassed faulty link triggers a local optimization signal and performs clock shutdown.

[0077] As can be seen from the above technical solutions, this application has the following advantages:

[0078] The intelligent clock-gated NoC system and dynamic power management method based on AXI interconnect provided in this application, through the synergistic effect of intelligent clock gating and dynamic power management, can dynamically adjust the clock signal and supply voltage according to real-time load conditions, achieving fine-grained power consumption control. This reduces power consumption under low load and ensures rapid response under high load, guaranteeing performance. This allows the SoC to achieve high energy efficiency operation in various application scenarios, extending the battery life of mobile devices and meeting the stringent energy efficiency requirements of multi-core processors and automotive electronics. Combining the high bandwidth and low latency characteristics of the AXI interconnect matrix with the distributed architecture advantages of the 2D Mesh network, it provides an efficient channel for data transmission between numerous components within the SoC. The AXI interconnect matrix is ​​responsible for high-speed interconnection between core components and the 2D Mesh network and other peripherals, while the 2D Mesh network, based on its scalability, addresses the communication needs of SoCs of different sizes, ensuring data transmission reliability and improving transmission efficiency. The self-healing routing strategy of the Mesh network module can detect link failures in a timely manner and automatically adjust the route to ensure continuous and complete data transmission. At the same time, the intelligent clock gating module retains register power supply when the clock is turned off to ensure that status information is not lost. When a data transmission request is detected, the clock and voltage can be quickly restored through the bypass clock tree, enhancing the stability and reliability of the system in complex working environments. Attached Figure Description

[0079] To more clearly illustrate the technical solution of this application, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0080] Figure 1 This is a schematic diagram of the intelligent clock gating NoC system based on AXI interconnect according to the present invention.

[0081] Figure 2 A schematic diagram of the connection between the AXI interconnect matrix module and the 2D Mesh network module of the present invention.

[0082] Figure 3 This is a flowchart illustrating the dynamic power consumption management method of the intelligent clock-gated NoC system based on AXI interconnect according to the present invention. Detailed Implementation

[0083] The various embodiments of this disclosure will be described more fully in the following detailed description of an AXI Interconnect-based smart clock gating NoC system. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0084] For example, with the development of the integrated circuit industry, the integration level of system-on-a-chip (SoC) continues to rise. In fields such as multi-core processors, mobile devices, and automotive electronics, the requirements for the energy efficiency of SoCs are becoming increasingly stringent. Traditional bus architectures, due to insufficient bandwidth and excessive latency, have been gradually replaced by networks on-chip (NoC). However, while the introduction of NoC has improved communication efficiency, the surge in the number of routers and links has led to a significant increase in dynamic power consumption (such as clock network switching) and static power consumption (such as leakage current), becoming a key bottleneck in the design of high-performance SoCs.

[0085] While current static clock gating and dynamic voltage regulation techniques can reduce power consumption to some extent, they struggle to adapt to dynamic load changes in real time. For example, the industry-standard SMART-PG solution, while shutting down idle components to reduce power consumption under low load, suffers from slow response and performance degradation during sudden traffic surges. Tulip designs, while reducing power consumption through optimized routing logic, sacrifice routing flexibility, limiting their applicability in complex application scenarios. Furthermore, existing routing optimization schemes (such as topology adaptive adjustment) can reduce power consumption, but they typically come with significant hardware overhead and struggle to maintain high efficiency under varying network load conditions.

[0086] Therefore, there is an urgent need for a dynamic and adaptive low-power NoC solution that can achieve intelligent power management while ensuring high performance, so as to meet the energy efficiency requirements of modern SoCs under varying load conditions.

[0087] To address the aforementioned issues, this embodiment provides an intelligent clock-gated NoC system based on AXI interconnect, achieving efficient integration and intelligent control of the system architecture. Through the collaborative work of the AXI interconnect matrix module, 2D Mesh network module, and intelligent clock gating module, coupled with the dynamic power management module, system performance and resource utilization are improved, overall system power consumption is reduced, and data transmission stability and efficiency are enhanced. This adapts to diverse application scenarios and realizes a high-performance, low-power on-chip system design.

[0088] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0089] Please see Figure 1 The diagram shown is a schematic of a smart clock gating NoC system based on AXI interconnect in a specific embodiment. The system includes an AXI interconnect matrix module, a 2D Mesh network module, a smart clock gating module, and a dynamic power management module.

[0090] The AXI interconnect matrix module is equipped with a crossbar switch, at least one master port and several slave ports. The master port and slave ports are connected to the crossbar switch via the AXI bus.

[0091] The 2D Mesh network module consists of a network array of M×N router nodes. Each router node has a local port and four peripheral ports in the four directions. Each router node connects to adjacent router nodes through the peripheral ports using the AXI bus.

[0092] The slave ports of the AXI interconnect matrix module include Type I slave ports and Type II slave ports; the AXI interconnect matrix module is connected to the core components through the master port or Type I slave port, and the 2D Mesh network module is connected to the Type II slave port.

[0093] The local port connection of the 2D Mesh network module has auxiliary components;

[0094] The intelligent clock gating module monitors the channel traffic of the AXI interconnect matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls the clock signals of the AXI interconnect matrix module and the 2D Mesh network module.

[0095] The dynamic power management module adjusts the power consumption status of the AXI interconnect matrix module and the 2D Mesh network module based on the global power optimization signal and the local optimization signal.

[0096] In this embodiment, the AXI interconnect matrix module connects the core components to the 2D Mesh network module through a crossbar switch, master port, and slave port design, ensuring data transmission efficiency. The router node architecture and connection method of the 2D Mesh network module construct a stable network topology, facilitating data routing and forwarding between modules. The intelligent clock gating module monitors traffic and load in real time and dynamically controls the clock signal to reduce system power consumption. The dynamic power management module adjusts the power consumption state according to the optimization signal, further improving the system's energy efficiency ratio.

[0097] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another intelligent clock gating NoC system based on AXI interconnect is provided. This system includes an AXI interconnect matrix module, a 2D Mesh network module, an intelligent clock gating module, and a dynamic power management module.

[0098] The AXI interconnect matrix module is equipped with a crossbar switch, at least one master port and several slave ports. The master port and slave ports are connected to the crossbar switch via the AXI bus.

[0099] The 2D Mesh network module consists of a network array of M×N router nodes. Each router node has a local port and four peripheral ports in the four directions. Each router node connects to adjacent router nodes through the peripheral ports using the AXI bus.

[0100] The slave ports of the AXI interconnect matrix module include Type I slave ports and Type II slave ports; the AXI interconnect matrix module is connected to the core components through the master port or Type I slave port, and the 2D Mesh network module is connected to the Type II slave port.

[0101] The local port connection of the 2D Mesh network module has auxiliary components;

[0102] The core components include the CPU, NPU, and memory controller;

[0103] Auxiliary components include the GPU, PCIe peripherals, and USB peripherals;

[0104] For example, such as Figure 2 As shown, taking an AXI interconnect matrix module with 8 master ports and 8 slave ports as an example, 4 of the 8 master ports are connected to the CPU core, 2 are connected to the NPU, and 2 are used as spare ports; among the 8 slave ports, 4 are directly connected to the DDR4 controller, and 4 are connected to the entry router node of the 2D Mesh network module.

[0105] The intelligent clock gating module monitors the channel traffic of the AXI interconnect matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls the clock signals of the AXI interconnect matrix module and the 2D Mesh network module.

[0106] The dynamic power management module adjusts the power consumption state of the AXI interconnect matrix module and the 2D Mesh network module based on the global power optimization signal and the local optimization signal;

[0107] The AXI interconnect matrix module includes an arbitration controller and a channel controller;

[0108] The arbitration controller uses a weighted round-robin arbitration algorithm to determine the priority of request events, and dynamically allocates bandwidth to the corresponding slave port according to the determined priority, ensuring that the bandwidth of the slave port meets at least the set proportion of the maximum bandwidth of the channel to which it belongs;

[0109] For example, the priority of request events is: urgent transactions > memory access > normal transactions;

[0110] Dynamic bandwidth allocation ensures that the bandwidth of a port meets at least 20% of the maximum bandwidth of its channel.

[0111] The channel controller performs ECC verification on the data transmitted between the internal ports of the AXI interconnect matrix module according to the preset service level.

[0112] For example, the preset service levels are arranged from high to low as follows: real-time, high, and normal.

[0113] The four peripheral ports of the 2D Mesh network module are interconnected with adjacent router nodes through the AXI bus. The network array of the 2D Mesh network module forms horizontal and vertical physical links.

[0114] The horizontal physical link uses P parallel AXI channels, and the vertical physical link uses Q parallel AXI channels, where P > Q;

[0115] For example, the horizontal physical link uses 4 parallel AXI channels, and the vertical physical link uses 2 parallel AXI channels;

[0116] The AXI bus width between adjacent router nodes is 128 bits@1 GHz, meaning each AXI channel width is 128 bits@1 GHz.

[0117] Each peripheral port supports at least two virtual channels;

[0118] The router node corresponding to the peripheral port in one direction of the 2D Mesh network module is set as the ingress router node, and each ingress router node is connected to a Type II slave port of the AXI interconnect matrix module.

[0119] The routing nodes of the 2D Mesh network module are configured with deterministic routing policies, cache prefetching logic, and self-healing routing policies.

[0120] The deterministic routing policy is configured as follows:

[0121] In the network array, routes are first routed to the target column according to the horizontal physical link, and then routed to the target routing node according to the vertical physical link;

[0122] The cache prefetch logic is configured as follows:

[0123] Monitor the local access history of the router node and record the address sequence of the most recent N accesses;

[0124] For example, the address sequence of the 16 most recent visits is recorded;

[0125] The prefetch step is dynamically calculated based on the cache miss rate (miss_rate).

[0126] prefetch_step = round(K * (miss_rate)^(-α));

[0127] Where K and α are configurable parameters;

[0128] It should be noted that `round` is the rounding function;

[0129] When the cache utilization rate is lower than the threshold, a prefetch operation is triggered and a prefetch request is sent to the target router.

[0130] The self-healing routing policy is configured as follows:

[0131] Periodically perform link bit error rate tests to detect faulty links;

[0132] When a link failure in a certain direction is detected, update the routing table redirection policy of the local router node:

[0133] If the lateral physical link fails, the default lateral traffic will be redirected to the upper or lower level.

[0134] If the vertical physical link fails, the detour path on the left or right will be selected first.

[0135] The fault information is synchronized to neighboring router nodes via the Neighbor Status Broadcast Protocol.

[0136] For example, such as Figure 2 As shown, when the bit error rate detected by BERT on the R01-R02 horizontal physical link is >1e-6, it is determined that the R01-R02 horizontal physical link is faulty.

[0137] Change the original path: R00→R01→R02→R03→R13 to the following new path: R00→R01→R11→R12→R13;

[0138] The clock domains controlled by the intelligent clock gating module include:

[0139] The channel clock of each slave port within the AXI interconnect matrix;

[0140] The internal logical clock of the router node in the 2D Mesh network module;

[0141] Transmission clocks for horizontal and vertical physical links between router nodes;

[0142] The router node's virtual channel buffer and arbitrator clock;

[0143] Each clock also has a bypass clock tree;

[0144] The intelligent clock gating module includes:

[0145] The real-time monitoring unit monitors the packet arrival rate, router node buffer utilization, and the number of invalid cycles of the AXI handshake signal, and triggers clock gating decisions when the threshold is met.

[0146] The clock gating decision unit filters and synchronizes the raw signal of the monitoring data, compares it with the gating conditions of the preset threshold, and generates a preliminary gating enable signal when the gating conditions are met. The preliminary gating enable signal and the external forced wake-up signal are combined with an AND gate to generate the final gating signal.

[0147] The clock control execution unit performs clock shut-off or clock-on for the corresponding clock according to the final gating signal. When a data packet is detected arriving on the channel where the clock is shut off, the bypass clock tree of the corresponding clock is activated.

[0148] It should be noted that when a clock is turned off, only the clock logic is turned off, while the clock register power supply is retained, and the wake-up delay of the bypass clock tree is <10ns;

[0149] The dynamic power management module includes:

[0150] The global voltage regulation unit responds to the global power optimization signal and uniformly adjusts the operating voltage of the AXI interconnect module and the 2D Mesh network module.

[0151] The local voltage regulation unit, in response to a local optimization signal, independently regulates the following supply voltages:

[0152] The power supply voltage of each slave port in the AXI interconnect matrix;

[0153] The power supply voltage of a single router node in a 2D Mesh network module;

[0154] The voltage and frequency coordination control unit synchronously adjusts the clock frequency of the corresponding module during voltage regulation.

[0155] like Figure 3As shown, the following are embodiments of the dynamic power management method for an AXI-connected smart clock-gated NoC system provided in this disclosure. This method belongs to the same inventive concept as the AXI-connected smart clock-gated NoC system in the above embodiments. For details not described in detail in the embodiments of the dynamic power management method for the AXI-connected smart clock-gated NoC system, please refer to the above embodiments of the AXI-connected smart clock-gated NoC system.

[0156] The method includes the following steps:

[0157] S1. Real-time acquisition of data traffic from each slave port in the AXI interconnect matrix module, periodic acquisition of data load from each router node in the 2D Mesh network module, and statistical analysis of data transmission time intervals in each virtual channel to obtain global load and idle time of local functional units; the local functional units include each slave port in the AXI interconnect matrix module, each router node in the 2D Mesh network module, and each virtual channel;

[0158] It should be noted that by collecting the data traffic of each slave port in the AXI interconnect matrix module in real time, periodically obtaining the data load of each router node in the 2D Mesh network module, and statistically analyzing the data transmission time interval in each virtual channel, the global load and the idle time of local functional units can be accurately identified, providing a data basis for subsequent power consumption optimization decisions and ensuring that the system can make accurate power consumption adjustments under different load conditions.

[0159] S2. When the global load is lower than the first threshold, a global power optimization signal is triggered to reduce the operating voltage. When the idle time of a local functional unit exceeds a set period, a local optimization signal is generated.

[0160] It should be noted that by triggering a global power optimization signal when the global load is below the first threshold, the operating voltage is reduced, thereby reducing the overall power consumption of the system. When the idle time of a local functional unit exceeds a set period, a local optimization signal is generated to optimize the power consumption of the specific unit. This threshold-based triggering method can respond to changes in system load in a timely manner, avoid unnecessary power waste, and take into account both global and local power management needs, thereby improving the system's energy efficiency ratio.

[0161] S3. The dynamic power management module adjusts the supply voltage according to the global power optimization signal and adjusts the clock frequency synchronously.

[0162] It should be noted that the dynamic power management module adjusts the supply voltage according to the global power optimization signal and adjusts the clock frequency synchronously. By pre-setting the voltage adjustment step size and adjusting the clock frequency according to the frequency synchronization formula, it ensures that the system can still operate stably at a suitable frequency while reducing the voltage, avoiding performance problems caused by voltage and frequency mismatch, and achieving a balance between power consumption and performance optimization.

[0163] S4. The intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, and restores the clock and voltage through the bypass clock tree of the corresponding local functional unit when a new data transmission request is detected.

[0164] It should be noted that the intelligent clock gating module shuts down the clock of the corresponding local functional unit based on the local optimization signal, only shutting down the clock logic while retaining the power supply to the register. When a new data transmission request is detected, the clock and voltage are quickly restored through the bypass clock tree. This ensures low power consumption while enabling a rapid response to data transmission needs, reducing system latency and improving system response speed and overall performance.

[0165] This embodiment accurately obtains the global load and the idle time of local functional units by collecting data traffic, load and time interval in real time, providing a data foundation for subsequent power consumption management; based on the load and idle time, the dynamic power management module and the intelligent clock gating module adjust the voltage and clock accordingly to achieve dynamic and precise control of system power consumption, reduce the overall power consumption of the system and improve energy utilization efficiency.

[0166] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another dynamic power consumption management method for an intelligent clock-gated NoC system based on AXI interconnect is provided. This method includes the following steps:

[0167] S1. Real-time acquisition of data traffic from each slave port in the AXI interconnect matrix module, periodic acquisition of data load from each router node in the 2D Mesh network module, and statistical analysis of data transmission time intervals in each virtual channel to obtain global load and idle time of local functional units; the local functional units include each slave port in the AXI interconnect matrix module, each router node in the 2D Mesh network module, and each virtual channel;

[0168] S2. When the global load is below the first threshold, a global power optimization signal is triggered to reduce the operating voltage. When the idle time of a local functional unit exceeds a set period, a local optimization signal is generated. The specific steps of step S2 are as follows:

[0169] S21. Based on the data traffic collected from each slave port in the AXI interconnect matrix module, calculate the average bandwidth utilization of all slave ports in the AXI interconnect matrix module. When the average bandwidth utilization is less than the first set proportional threshold for N consecutive cycles, activate the global power optimization signal.

[0170] For example, when the average bandwidth utilization is less than 15% for 16 consecutive cycles, the global power optimization signal is activated;

[0171] S22. Based on the data load of each router node and the data transmission time interval in each virtual channel, calculate the buffer utilization and data transmission time interval in the virtual channel independently for each router node;

[0172] If the buffer utilization rate is less than the second set ratio threshold for M consecutive cycles, the local optimization signal of the corresponding router node is activated.

[0173] For example, if the buffer utilization rate is less than 10% for 8 consecutive cycles, the local optimization signal of the corresponding router node is activated;

[0174] If there is no data transmission in the virtual channel for P consecutive cycles, activate the local optimization signal of the corresponding router node;

[0175] For example, if there is no data transmission in the virtual channel for 16 consecutive cycles, the local optimization signal of the corresponding router node is activated;

[0176] S23. When the global power optimization signal conflicts with the local optimization signal, the global optimization signal shall be given priority.

[0177] S3. The dynamic power management module adjusts the supply voltage according to the global power optimization signal and adjusts the clock frequency synchronously; the specific steps of step S3 are as follows:

[0178] S31. Preset the voltage adjustment step size; for example, set the voltage adjustment step size to 50mV;

[0179] S32. The dynamic power management module responds to the global power optimization signal and performs voltage regulation according to the voltage regulation step size, and blocks the global power voltage optimization signal for a set time period after voltage regulation;

[0180] For example, the voltage stabilizes for at least 100 ns after adjustment;

[0181] S33. Perform frequency adjustment on the clock according to the following frequency synchronization adjustment formula:

[0182]

[0183] in, Indicates the adjusted clock frequency. Indicates the clock frequency before adjustment. This indicates the adjusted voltage. This indicates the voltage before adjustment;

[0184] S4. The intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, and when a new data transmission request is detected, it restores the clock and voltage through the bypass clock tree of the corresponding local functional unit; in step S4, the intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, only shutting down the clock logic and retaining the power supply to the clock register;

[0185] When a data packet is detected arriving on a channel with the clock off, the bypass clock tree of the corresponding clock is first activated to perform data transmission, then the operating voltage of the corresponding clock is restored, and finally the main clock tree of the clock is unlocked.

[0186] It should be noted that the activation time of the bypass clock tree is less than 5ns, the time to restore the corresponding clock operating voltage is less than 20ns, and the unlocking time of the main clock tree is less than 2ns.

[0187] Unlike the above embodiments, a dynamic power management method for an intelligent clock-gated NoC system based on AXI interconnect further includes the following steps:

[0188] Core component communication always occurs via a direct connection path through the AXI interconnect matrix module;

[0189] After the core components and auxiliary components communicate through the AXI interconnection matrix module and enter the entry router node of the 2D Mesh network module, they perform a jump according to the deterministic routing policy. When a routing failure occurs, a self-healing routing policy is executed to determine a new target router node.

[0190] When the clock of the new target router node is in a clock-off gated state, the gated state of the target router node is automatically released;

[0191] When the self-healing routing policy is executed, the router node on the bypassed faulty link triggers a local optimization signal and performs clock shutdown.

[0192] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0193] The dynamic power management method for an AXI-connected smart clock-gated NoC system provided in this application can be applied to electronic devices. Those skilled in the art will understand that the electronic device structure described in this embodiment does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In this embodiment, the electronic device includes, but is not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments described and / or claimed herein.

[0194] Electronic devices may include processors, external memory interfaces, internal memory, universal serial bus (USB) interfaces, charging management modules, power management modules, batteries, wireless communication modules, audio modules, speakers, microphones, sensor modules, buttons, cameras, displays, and SIM card interfaces, etc.

[0195] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0196] A processor may include one or more processing units, such as a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0197] The processor can serve as the nerve center and command center of an electronic device. The controller can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0198] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can retrieve it directly from this memory. This avoids repeated accesses, reduces processor latency, and thus improves system efficiency.

[0199] The aforementioned electronic device implements the dynamic power management method of the intelligent clock gating NoC system based on AXI interconnection in this application. This method involves real-time acquisition of data traffic from each slave port in the AXI interconnection matrix module, periodic acquisition of data load from each router node in the 2D Mesh network module, and statistical analysis of data transmission time intervals in each virtual channel to obtain the global load and idle time of local functional units. The local functional units include each slave port in the AXI interconnection matrix module, each router node in the 2D Mesh network module, and each virtual channel. When the global load is below a first threshold, a global power optimization signal is triggered, reducing the operating voltage. When the idle time of a local functional unit exceeds a set period, a local optimization signal is generated. The dynamic power management module adjusts the supply voltage according to the global power optimization signal and synchronously adjusts the clock frequency. The intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal. Furthermore, when a new data transmission request is detected, the clock and voltage are restored through the bypass clock tree of the corresponding local functional unit. This achieves the goal of managing power consumption through the AXI interconnection matrix module and the 2D Mesh network module. The network module and the intelligent clock gating module work together, in conjunction with the dynamic power management module, to improve the performance and resource utilization of the on-chip system, reduce the overall power consumption of the system, and enhance the stability and efficiency of data transmission.

[0200] The storage medium provided in this application stores a program product capable of implementing a dynamic power management method for an intelligent clock-gated NoC system based on AXI interconnect.

[0201] The dynamic power management method of the intelligent clock gating NoC system based on AXI interconnect includes: real-time acquisition of data traffic from each slave port in the AXI interconnect matrix module, periodic acquisition of data load from each router node in the 2D Mesh network module, and statistical analysis of data transmission time intervals in each virtual channel to obtain the global load and idle time of local functional units; the local functional units include each slave port in the AXI interconnect matrix module, each router node in the 2D Mesh network module, and each virtual channel; when the global load is lower than a first threshold, a global power optimization signal is triggered to reduce the operating voltage, and when the idle time of a local functional unit exceeds a set period, a local optimization signal is generated; the dynamic power management module adjusts the supply voltage according to the global power optimization signal and synchronously adjusts the clock frequency; the intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, and when a new data transmission request is detected, restores the clock and voltage through the bypass clock tree of the corresponding local functional unit.

[0202] In some possible implementations, the dynamic power management method for an AXI Interconnect-based smart clock-gated NoC system disclosed herein can be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0203] The storage medium disclosed herein may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0204] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A smart clock gating NoC system based on AXI interconnect, characterized in that, Includes AXI interconnect matrix module, 2DMesh network module, intelligent clock gating module and dynamic power management module; The AXI interconnect matrix module is equipped with a crossbar switch, at least one master port and several slave ports. The master port and slave ports are connected to the crossbar switch via the AXI bus. The 2D Mesh network module consists of a network array of M×N router nodes. Each router node has a local port and four peripheral ports in the outer direction. Each router node connects to adjacent router nodes through the peripheral ports using the AXI bus. The slave ports of the AXI interconnect matrix module include Type I slave ports and Type II slave ports; the AXI interconnect matrix module is connected to the core components through the master port or Type I slave port, and the 2D Mesh network module is connected to the Type II slave port. The local port connection of the 2D Mesh network module has auxiliary components; The intelligent clock gating module monitors the channel traffic of the AXI interconnect matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls the clock signals of the AXI interconnect matrix module and the 2D Mesh network module. The dynamic power management module adjusts the power consumption status of the AXI interconnect matrix module and the 2DMesh network module based on the global power optimization signal and the local optimization signal.

2. The intelligent clock gating NoC system based on AXI interconnect according to claim 1, characterized in that, The AXI interconnect matrix module includes an arbitration controller and a channel controller; The arbitration controller uses a weighted round-robin arbitration algorithm to determine the priority of request events, and dynamically allocates bandwidth to the corresponding slave port according to the determined priority, ensuring that the bandwidth of the slave port meets at least the set proportion of the maximum bandwidth of the channel to which it belongs; Dynamic bandwidth allocation ensures that the bandwidth of a port meets at least 20% of the maximum bandwidth of its channel. The channel controller performs ECC verification on the data transmitted between the internal ports of the AXI interconnect matrix module according to the preset service level.

3. The intelligent clock gating NoC system based on AXI interconnect according to claim 1, characterized in that, The four peripheral ports of the 2D Mesh network module are interconnected with adjacent router nodes through the AXI bus, and the network array of the 2D Mesh network module forms horizontal and vertical physical links. The horizontal physical link uses P parallel AXI channels, and the vertical physical link uses Q parallel AXI channels, where P > Q; Each peripheral port supports at least two virtual channels; The router node corresponding to the peripheral port in one direction of the 2D Mesh network module is designated as the ingress router node, and each ingress router node is connected to a Type II slave port of the AXI interconnect matrix module.

4. The intelligent clock gating NoC system based on AXI interconnect according to claim 3, characterized in that, The routing nodes of the 2D Mesh network module are configured with deterministic routing policies, cache prefetching logic, and self-healing routing policies. The deterministic routing policy is configured as follows: In the network array, routes are first routed to the target column according to the horizontal physical link, and then routed to the target routing node according to the vertical physical link; The cache prefetch logic is configured as follows: Monitor the local access history of the router node and record the address sequence of the most recent N accesses; The prefetch step is dynamically calculated based on the cache miss rate (miss_rate). prefetch_step = round(K * (miss_rate)^(-α)); Where K and α are configurable parameters; When the cache utilization rate is lower than the threshold, a prefetch operation is triggered and a prefetch request is sent to the target router. The self-healing routing policy is configured as follows: Periodically perform link bit error rate tests to detect faulty links; When a link failure in a certain direction is detected, update the routing table redirection policy of the local router node: If the lateral physical link fails, the default lateral traffic will be redirected to the upper or lower level. If the vertical physical link fails, the detour path on the left or right will be selected first. Fault information is synchronized to neighboring router nodes via the Neighbor Status Broadcast Protocol.

5. The intelligent clock gating NoC system based on AXI interconnect according to claim 3, characterized in that, The clock domains controlled by the intelligent clock gating module include: The channel clock of each slave port within the AXI interconnect matrix; The internal logical clock of the router node in the 2D Mesh network module; Transmission clocks for horizontal and vertical physical links between router nodes; The router node's virtual channel buffer and arbitrator clock; Each clock also has a bypass clock tree; The intelligent clock gating module includes: The real-time monitoring unit monitors the packet arrival rate, router node buffer utilization, and the number of invalid cycles of the AXI handshake signal, and triggers clock gating decisions when the threshold is met. The clock gating decision unit filters and synchronizes the raw signal of the monitoring data, compares it with the gating conditions of the preset threshold, and generates a preliminary gating enable signal when the gating conditions are met. The preliminary gating enable signal and the external forced wake-up signal are combined with an AND gate to generate the final gating signal. The clock control execution unit performs clock shut-off or clock-on for the corresponding clock according to the final gating signal. When a data packet is detected arriving on the channel where the clock is shut off, the bypass clock tree of the corresponding clock is activated.

6. The intelligent clock gating NoC system based on AXI interconnect according to claim 1, characterized in that, The dynamic power management module includes: The global voltage regulation unit responds to the global power optimization signal and uniformly adjusts the operating voltage of the AXI interconnect module and the 2D Mesh network module. The local voltage regulation unit, in response to a local optimization signal, independently regulates the following supply voltages: The power supply voltage of each slave port in the AXI interconnect matrix; The power supply voltage of a single router node in a 2D Mesh network module; The voltage and frequency coordination control unit synchronously adjusts the clock frequency of the corresponding module during voltage regulation.

7. The intelligent clock gating NoC system based on AXI interconnect according to claim 1, characterized in that, The core components include the CPU, NPU, and memory controller; Auxiliary components include the GPU, PCIe peripherals, and USB peripherals.

8. A dynamic power consumption management method for an intelligent clock-gated NoC system based on AXI interconnect according to any one of claims 1-7, characterized in that, Includes the following steps: S1. Real-time acquisition of data traffic from each slave port in the AXI interconnect matrix module, periodic acquisition of data load from each router node in the 2D Mesh network module, and statistical analysis of data transmission time intervals in each virtual channel to obtain global load and idle time of local functional units; the local functional units include each slave port in the AXI interconnect matrix module, each router node in the 2D Mesh network module, and each virtual channel; S2. When the global load is lower than the first threshold, a global power optimization signal is triggered to reduce the operating voltage, and when the idle time of a local functional unit exceeds a set period, a local optimization signal is generated. S3. The dynamic power management module adjusts the supply voltage according to the global power optimization signal and adjusts the clock frequency synchronously. S4. The intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, and restores the clock and voltage through the bypass clock tree of the corresponding local functional unit when a new data transmission request is detected.

9. The dynamic power consumption management method according to claim 8, characterized in that, The specific steps of step S2 are as follows: S21. Based on the data traffic collected from each slave port in the AXI interconnect matrix module, calculate the average bandwidth utilization of all slave ports in the AXI interconnect matrix module. When the average bandwidth utilization is less than the first set proportional threshold for N consecutive cycles, activate the global power optimization signal. S22. Based on the data load of each router node and the data transmission time interval in each virtual channel, calculate the buffer utilization and data transmission time interval in the virtual channel independently for each router node; If the buffer utilization rate is less than the second set ratio threshold for M consecutive cycles, the local optimization signal of the corresponding router node is activated. If there is no data transmission in the virtual channel for P consecutive cycles, activate the local optimization signal of the corresponding router node; S23. When the global power optimization signal conflicts with the local optimization signal, the global optimization signal shall be given priority. The specific steps of step S3 are as follows: S31. Preset voltage adjustment step size; S32. The dynamic power management module responds to the global power optimization signal and performs voltage regulation according to the voltage regulation step size, and blocks the global power voltage optimization signal for a set time period after voltage regulation; S33. Perform frequency adjustment on the clock according to the following frequency synchronization adjustment formula: in, Indicates the adjusted clock frequency. Indicates the clock frequency before adjustment. This indicates the adjusted voltage. This indicates the voltage before adjustment; In step S4, the intelligent clock gating module shuts down the clock of the corresponding local functional unit according to the local optimization signal, only shutting down the clock logic while retaining the power supply to the clock register; When a data packet is detected arriving on a channel with a clock off, the bypass clock tree of the corresponding clock is first activated to perform data transmission, then the operating voltage of the corresponding clock is restored, and finally the main clock tree of that clock is unlocked.

10. The dynamic power consumption management method according to claim 8, characterized in that, It also includes the following steps: Core component communication always occurs via a direct connection path through the AXI interconnect matrix module; After the core components and auxiliary components communicate through the AXI interconnection matrix module and enter the entry router node of the 2D Mesh network module, they perform a jump according to the deterministic routing policy. When a routing failure occurs, a self-healing routing policy is executed to determine a new target router node. When the clock of the new target router node is in a clock-off gated state, the gated state of the target router node is automatically released; When the self-healing routing policy is executed, the router node on the bypassed faulty link triggers a local optimization signal and performs clock shutdown.

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