Gate driving device and display panel

Abstract

This application relates to a gate driving device and a display panel, belonging to the field of display driving technology. The gate driving device includes a first power line, a second power line, multiple cascaded first driving circuits, and multiple cascaded second driving circuits. The first driving circuits are connected to the first power line and are used to output a target driving signal to the pixel circuit. The second driving circuits include a stage transmission sub-circuit and an output sub-circuit. The stage transmission sub-circuit is connected to the first power line and is used to output a stage transmission signal to the subsequent circuit of the stage transmission sub-circuit based on a first power supply voltage transmitted from the first power line. The output sub-circuit is connected to the second power line and is used to output a threshold compensation signal to the pixel circuit based on a second power supply voltage transmitted from the second power line. This helps to reduce voltage drop on the second power line, making the threshold compensation signal more stable, reducing the coupling difference between odd and even row pixel circuits, thereby improving the fine horizontal stripe phenomenon in the displayed image.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and in particular to a gate driving device and a display panel. Background Technology

[0002] In the field of display technology, digital optical element (DOE) displays achieve precise control and processing of light through digital optical elements, possessing high resolution, high contrast and accurate color reproduction capabilities, and can present clearer image display effects. They are widely used in many fields such as industrial control, medical equipment, and professional monitoring.

[0003] Currently, driving the pixel circuits in a digital optical element display requires the combined control of multiple driving signals. Some driving signals can be shared by both rows of pixel circuits, while others require independent driving signals for each row of pixel circuits. However, due to interference, transmission delay, or signal strength, the driving signals will produce slight differences, resulting in a display error exhibiting a pattern of odd and even rows when the two rows of pixel circuits work together using both independent and shared driving signals.

[0004] Therefore, how to improve the fine horizontal stripe phenomenon caused by the difference between odd and even row signals during the display process, thereby improving the quality of the display image, is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving device that improves the fine horizontal stripe phenomenon caused by the difference between odd and even row signals during the display process, thereby improving the quality of the displayed image and at least partially solving the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a gate driving device is provided, comprising: a first power line, a second power line, a plurality of cascaded first driving circuits, and a plurality of cascaded second driving circuits; The first driving circuit is connected to the first power line and is used to output the target driving signal to the pixel circuit; The second driving circuit includes a stage transmission sub-circuit and an output sub-circuit; wherein, the stage transmission sub-circuit is connected to the first power line and is used to output a stage transmission signal to the subsequent circuit of the stage transmission sub-circuit according to the first power supply voltage transmitted by the first power line; the output sub-circuit is connected to the second power line and is used to output a threshold compensation signal to the pixel circuit according to the second power supply voltage transmitted by the second power line.

[0007] Optionally, it may also include multiple cascaded third driving circuits, each of which is used to output a scan signal to the corresponding row of pixel circuits; The output sub-circuit of each level is used to output the threshold compensation signal to the corresponding two rows of pixel circuits.

[0008] Optionally, the second driving circuit further includes a cascade control sub-circuit, used to output a first pull-down control signal, a second pull-down control signal, a cascade control signal and an output control signal according to the cascade signal output from the preceding circuit of the cascade sub-circuit; The stage transmission circuit outputs the stage transmission signal according to the first power supply voltage, the stage transmission control signal, the first pull-down control signal, and the second pull-down control signal; The output sub-circuit outputs the threshold compensation signal based on the second power supply voltage, the output control signal, the first pull-down control signal, and the second pull-down control signal.

[0009] Optionally, the stage-transfer circuit includes a first transistor, a second transistor, and a third transistor; The first transistor includes a control electrode connected to the third transistor and connected to the stage transmission control signal, a first electrode connected to the first power line, and a second electrode connected to the second transistor and outputting the stage transmission signal; The second transistor includes a control electrode connected to the first pull-down control signal, a first electrode connected to the first transistor, and a second electrode connected to the second power line; The third transistor includes a control electrode that receives the second pull-down control signal, a first electrode that is connected to the first transistor, and a second electrode that receives the third power supply voltage.

[0010] Optionally, the output sub-circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; The fourth transistor includes a control electrode connected to the fifth transistor and connected to the output control signal, a first electrode connected to the second power line, and a second electrode connected to the sixth transistor and connected to the threshold compensation signal. The fifth transistor includes a control electrode connected to the first pull-down control signal, a first electrode connected to the fourth transistor, and a second electrode connected to the second power line. The sixth transistor includes a control electrode that receives the second pull-down control signal, a first electrode that is connected to the fourth transistor, and a second electrode that receives the third power supply voltage.

[0011] Optionally, the pixel circuit includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a sixth thin-film transistor, a seventh thin-film transistor, and an eighth thin-film transistor. The first thin-film transistor includes a first electrode for receiving data signals, a first electrode connected to a first node, and a second electrode connected to the third driving circuit; The second thin-film transistor includes a first electrode connected to the first node, a second electrode connected to the first node, and a control electrode connected to the second node; The third thin-film transistor includes a first electrode connected to the third node, a second electrode connected to the second node, and a control electrode connected to the threshold compensation signal; The fourth thin-film transistor includes a first electrode connected to the fourth power supply voltage, a second electrode connected to the third node, and a control electrode connected to the first reset control signal. The fifth thin-film transistor includes a first electrode connected to a fifth power supply voltage, a second electrode connected to a light-emitting device, and a control electrode connected to a second reset control signal. The sixth thin-film transistor includes a first electrode connected to a sixth power supply voltage, a second electrode connected to the first node, and a control electrode connected to the second reset control signal. The seventh thin-film transistor includes a first electrode connected to a seventh power supply voltage, a second electrode connected to the first node, and a control electrode connected to a light emission control signal. The eighth thin-film transistor includes a first electrode connected to the second node, a second electrode connected to the light-emitting device, and a control electrode that receives the light-emitting control signal. The target driving signal is at least one of the first reset control signal, the second reset control signal, and the light emission control signal.

[0012] Optionally, the target driving signal is the first reset control signal, and the first driving circuit is connected to the fourth thin-film transistor to output the first reset control signal to the control electrode of the fourth thin-film transistor.

[0013] Optionally, the target driving signal is the second reset control signal, and the first driving circuit is connected to the fifth thin-film transistor and the sixth thin-film transistor, for outputting the second reset control signal to the control electrode of the fifth thin-film transistor and the control electrode of the sixth thin-film transistor.

[0014] Optionally, the target driving signal is the light emission control signal, and the first driving circuit is connected to the seventh thin-film transistor and the eighth thin-film transistor for outputting the light emission control signal to the seventh thin-film transistor and the eighth thin-film transistor.

[0015] According to a second aspect of this application, a display panel is provided, including the gate driving device described above.

[0016] In summary, in the gate driving device of this application embodiment, during the process of the output sub-circuit outputting a threshold compensation signal to compensate the pixel circuit, the voltage drop on the second power line changes. This is achieved by connecting the stage transmission sub-circuit to the first power line. On one hand, this avoids the influence of voltage fluctuations on the second power line on the stage transmission signal output by the stage transmission sub-circuit, resulting in a more stable stage transmission signal and reducing the impact of voltage drop on the stage transmission signal. On the other hand, compared to connecting both the stage transmission sub-circuit and the output sub-circuit to the second power line, the stage transmission sub-circuit borrows the first power line from the first driving circuit, which helps reduce the voltage drop phenomenon on the second power line. This makes the threshold compensation signal output by the output sub-circuit more stable, thereby reducing the difference in threshold compensation effect between adjacent row pixel circuits and reducing the coupling difference between odd and even row pixel circuits. This improves the appearance of fine horizontal lines in the displayed image. Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a schematic diagram illustrating an application scenario of the gate driving device provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of a gate driving device provided in an exemplary embodiment of the present disclosure; Figure 3 This is a schematic diagram of a gate driving device provided in another exemplary embodiment of this disclosure; Figure 4 This is a circuit connection diagram of the second driving circuit provided in an exemplary embodiment of this disclosure; Figure 5 This is a circuit connection diagram of the cascade control sub-circuit provided in an exemplary embodiment of this disclosure; Figure 6 This is a circuit connection diagram of the pixel circuit provided in an exemplary embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached figures: 1. First driving circuit; 2. Second driving circuit; 21. Stage transmission sub-circuit; 22. Output sub-circuit; 23. Stage transmission control sub-circuit; 231. Output unit; 232. First node control unit; 233. Second node control unit; 24. First frequency division control unit; 25. Second frequency division control unit; 3. Third driving circuit. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] Reference Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel in an embodiment of this application. The display panel includes a display area AA and a non-display area NA adjacent to the display area AA, with the non-display area NA surrounding the display area AA. The display area AA is the region within the display panel used for display functions, and it contains multiple display units that implement these functions. The non-display area NA may be a border area of ​​the display panel, and it may contain functional components that assist the display units within the display area AA in displaying their functions. Multiple light-emitting devices D1 and pixel circuits 30 for driving the light-emitting devices D1 may be arrayed within the display area AA.

[0023] Combination Figure 1A gate driving device is provided in the non-display area NA. The gate driving device may include a threshold compensation circuit 11, a first reset circuit 12, a second reset circuit 13, a light emission control circuit 14, and a scanning circuit 20 arranged in a cascaded manner. As an example, the threshold compensation circuit 11 is used to output a threshold compensation signal Nscan1. The threshold compensation circuit 11 can be located on one side of the display area AA. Each threshold compensation circuit 11 drives two rows of pixel circuits 30 in the display area AA. That is, the threshold compensation circuit 11 can be configured as one-to-two on one side, and the two rows of pixel circuits 30 share one threshold compensation signal Nscan1. The first reset circuit 12 is used to output a first reset signal Nscan2. The first reset circuit 12 can be located on the other side of the display area AA, opposite to the threshold compensation circuit 11. Each first reset circuit 12 drives two rows of pixel circuits 30 in the display area AA. That is, the first reset circuit 12 can be configured as one-to-two on one side. The second reset circuit 13 is used to output the second reset signal Pscan2. The second reset circuit 13 can be located on one side of the display area AA. Each second reset circuit 13 drives two rows of pixel circuits 30 in the display area AA, that is, the second reset circuit 13 can be configured as one-to-two on one side. The light emission control circuit 14 is used to output the light emission control signal EM. The light emission control circuit 14 can be located on the other side of the display area AA, opposite to the second reset circuit 13. As an example, each light emission control circuit 14 can drive two rows of pixel circuits 30 in the display area AA, and the light emission control circuit 14 can be configured as one-to-two on one side. The scanning circuit 20 is used to output the scanning signal Pscan1. The scanning circuits 20 are respectively located on both sides of the display area AA. The two scanning circuits 20 located on both sides of the same row of pixel circuits 30 share the same area of ​​pixel circuits 30, that is, the scanning circuit 20 can be configured as one-to-one on both sides.

[0024] Thus, the pixel circuit 30 can realize data writing and light emission control of the light-emitting device D1 based on the scan signal Pscan1, the threshold compensation signal Nscan1, the first reset signal Nscan2, the second reset signal Pscan2, and the light emission control signal EM.

[0025] Secondly, refer to Figure 2In conjunction with the aforementioned background technology, the background of this application will be further elaborated. The threshold compensation signal Nscan1 is used to control the driving transistor in the pixel circuit 30 to perform conduction threshold compensation, so as to avoid errors in the data signal writing process caused by differences in the conduction threshold of the driving transistor. Due to the influence of transistor manufacturing process, each transistor in the pixel circuit 30 usually has parasitic capacitance. When the threshold compensation signal Nscan1 controls the operation of the compensation transistor in the pixel circuit 30, the parasitic capacitance will acquire charge from or release charge to the voltage source. Therefore, the de-loading status of the voltage source that generates the threshold compensation signal Nscan1 will continuously change due to the charging and discharging behavior of the parasitic capacitance. Firstly, during the threshold compensation process of the driving transistor by the threshold compensation signal Nscan1, the conduction of the compensation transistor requires the voltage source to provide additional current for the charging and discharging of its parasitic capacitance, making it difficult for the threshold compensation signal Nscan1 to maintain a stable state, resulting in ripple phenomenon and affecting the threshold compensation effect of the driving transistor. Secondly, this voltage source is usually also used to generate other drive signals in the gate drive device. Therefore, when the voltage source is de-loaded, it will also affect other drive signals using the voltage source, resulting in more adverse effects due to the voltage source de-load phenomenon.

[0026] Furthermore, in the aforementioned gate driving device architecture, adjacent rows of pixel circuits 30 share a threshold compensation signal Nscan1. Each row of pixel circuits 30 writes data signals at different times through its corresponding scan signal Pscan1. However, due to the influence of voltage source de-loading, the threshold compensation signal Nscan1 is difficult to maintain stability, resulting in differences in the threshold compensation effect of adjacent rows of pixel circuits 30 at different times. Consequently, the coupling degree of the odd-numbered rows of pixel circuits 30 and the even-numbered rows of pixel circuits 30 is different, leading to differences in display effects. Ultimately, the displayed image shows regular fine horizontal stripes in odd and even rows.

[0027] According to the first aspect of this application, referring to Figure 2 This disclosure provides a gate driving device, including a first power line VGH1, a second power line VGH2, a plurality of cascaded first driving circuits 1, and a plurality of cascaded second driving circuits 2. The first driving circuits 1 are connected to the first power line VGH1 and are used to output a target driving signal CON to a pixel circuit. The second driving circuits 2 include a stage transmission sub-circuit 21 and an output sub-circuit 22. The stage transmission sub-circuit 21 is connected to the first power line VGH1 and is used to output a stage transmission signal N(n) to the subsequent circuit of the stage transmission sub-circuit 21 based on a first power supply voltage transmitted through the first power line VGH1. The output sub-circuit 22 is connected to the second power line VGH2 and is used to output a threshold compensation signal Nscan1(n) to the pixel circuit based on a second power supply voltage transmitted through the second power line VGH2.

[0028] In this context, the subsequent stage circuit refers to one or more stages of the second driving circuit 2 that are cascaded with the second driving circuit 2 of this stage. For example, if the second driving circuit 2 of this stage is the nth stage, the subsequent stage circuit can be the (n+1)th or (n+2)th stage of the second driving circuit 2.

[0029] As an example, the threshold compensation signal Nscan1(n) is used to control the pixel circuit to compensate the threshold voltage of the thin-film transistor in the pixel circuit during the data signal writing process.

[0030] In the above embodiments, during the process of outputting the threshold compensation signal Nscan1(n) of the output sub-circuit 22 to compensate the pixel circuit, the voltage drop on the second power line VGH2 will change. This is achieved by connecting the stage transmission sub-circuit 21 to the first power line VGH1. On the one hand, this avoids the influence of voltage fluctuations on the second power line VGH2 on the stage transmission signal output by the stage transmission sub-circuit 21, so as to output a more stable stage transmission signal and reduce the influence of voltage drop on the second power line VGH2 on the stage transmission signal. On the other hand, compared with the method where both the stage transmission sub-circuit 21 and the output sub-circuit 22 are connected to the second power line VGH2, the stage transmission sub-circuit 21 uses the first power line VGH1 of the first driving circuit 1, which helps to reduce the voltage drop phenomenon on the second power line VGH2. This makes the threshold compensation signal Nscan1(n) output by the output sub-circuit 22 more stable, thereby reducing the difference in threshold compensation effect between adjacent row pixel circuits and reducing the coupling difference between odd and even row pixel circuits, thus improving the fine horizontal stripe phenomenon in the displayed image.

[0031] Reference Figure 3 As a further embodiment of the gate driving device, the gate driving device also includes multiple cascaded third driving circuits 3, each third driving circuit 3 being used to output a scan signal Pscan1 to the corresponding row of pixel circuits. The output sub-circuit 22 of each second driving circuit 2 is used to output a threshold compensation signal Nscan1(n) to the corresponding two rows of pixel circuits.

[0032] In the above embodiments, multiple cascaded third driving circuits 3 are used to output scanning signals Pscan1 for each row of pixel circuits to ensure that each pixel circuit works normally. Each output sub-circuit 22 is used to output threshold compensation signals Nscan1(n) to the corresponding two rows of pixel circuits, so that the two rows of pixel circuits share the same threshold compensation signal Nscan1(n), which is beneficial to realizing the narrow bezel design of the display panel.

[0033] Reference Figure 4 and Figure 5As one embodiment of the second driving circuit 2, the second driving circuit 2 further includes a stage transmission control sub-circuit 23, which is connected to the preceding stage circuit of the stage transmission sub-circuit 21 and is used to output a first pull-down control signal, a second pull-down control signal, a stage transmission control signal, and an output control signal based on the stage transmission signal output from the preceding stage circuit of the stage transmission sub-circuit 21. The stage transmission sub-circuit 21 is also connected to the stage transmission control sub-circuit 23 and is used to output a stage transmission signal based on a first power supply voltage, the stage transmission control signal, the first pull-down control signal, and the second pull-down control signal. The output sub-circuit 22 outputs a threshold compensation signal Nscan1(n) based on a second power supply voltage, the output control signal, the first pull-down control signal, and the second pull-down control signal.

[0034] As an example, the stage transmission control circuit includes a first control unit 232, a second control unit 233, and an input unit 231. The stage transmission signal output by the stage transmission sub-circuit 21 in the second drive circuit 2 can be output to the input unit 231 and the second control unit 233 in the subsequent second drive circuit 2 to drive the subsequent stage transmission sub-circuit 21 to output the stage transmission signal, thereby realizing the stage transmission control of the second drive circuit 2.

[0035] Reference Figure 5 D represents the first node; C represents the second node; B represents the third node; and Q represents the fourth node. The input unit 231 includes a seventh transistor T7, which includes a control electrode that receives the first clock signal, a first electrode that receives the signal transmission stage, and a second electrode connected to the first node.

[0036] The first control unit 232 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The eighth transistor T8 includes a control electrode connected to a first clock signal, a first electrode connected to a third power line VGL, and a second electrode connected to a second node. The ninth transistor T9 includes a control electrode connected to the second electrode of the seventh transistor T7, a first electrode connected to the first clock signal, and a second electrode connected to a second node. The tenth transistor T10 includes a control electrode connected to a second clock signal, a second electrode connected to the eleventh transistor T11, and a control electrode connected to a third node. The eleventh transistor T11 includes a first electrode connected to the tenth transistor T10, a second electrode connected to the stage transmission circuit 21, and a control electrode connected to the second clock signal.

[0037] The second control unit 233 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The thirteenth transistor T13 includes a control stage connected to the second node, a first electrode connected to the second power line VGH2, and a second electrode connected to the fourteenth transistor T14. The fourteenth transistor T14 includes a first electrode connected to the thirteenth transistor T13, a first electrode receiving a second clock signal, and a second electrode connected to the fifteenth transistor T15. The fifteenth transistor T15 includes a second electrode connected to the fourth node, a first electrode connected to the fourteenth transistor T14, and a control electrode. The sixteenth transistor T16 includes a control electrode connected to the third power line VGL and a control electrode connected to the input unit 231. The first electrode and the second electrode connected to the fourth node; the seventeenth transistor T17 includes a first electrode connected to the input unit 231, a second electrode connected to the second power supply line VGH2, and a control electrode connected to the control signal; the eighteenth transistor T18 includes a first electrode connected to the front-end circuit of the second drive circuit 2, a second electrode connected to the nineteenth transistor T19, and a control electrode connected to the first clock signal; the nineteenth transistor T19 includes a first electrode connected to the eighteenth transistor T18, a second electrode connected to the control electrode of the fourteenth transistor T14, and a control electrode connected to the third power supply line VGLVGL.

[0038] In the above embodiment, the input unit 231 controls the potential of the first node according to the stage transmission signal output from the pre-stage circuit of the second driving circuit 2. Then, the first control unit 232, together with the first node, the first clock signal line, and the stage transmission sub-circuit 21, outputs a stage transmission control signal according to the potential of the first node and the first clock signal, and outputs the stage transmission control signal to the stage transmission sub-circuit 21. The second control unit 233 is then connected to the first clock signal line, the first node, the fourth node, and the pre-stage circuit, and controls the potential of the fourth node according to the potential of the first node, the first clock signal, and the stage transmission signal output from the pre-stage circuit of the second driving circuit 2, thereby obtaining a first pull-down control signal, and outputs the first pull-down control signal to the output sub-circuit 22.

[0039] As an example, the gate driving device may further include a first frequency divider control unit 24 and a second frequency divider control unit 25. The first frequency divider control unit 24 includes a twentieth transistor T20, which includes a first electrode connected to the first control unit 232, a second electrode controlled by the stage sub-circuit 21, and a control electrode connected to the first frequency divider signal to control the on / off state between the first control unit 232 and the stage sub-circuit 21 via the first frequency divider signal. The second frequency divider control unit 25 includes a twenty-first transistor T21 and a twenty-second transistor T22. The twenty-first transistor T21 includes a first electrode connected to the second frequency divider signal, a second electrode connected to the twenty-second transistor T22, and a control electrode connected to the first node. The twenty-second transistor T22 includes a control electrode connected to the twenty-first transistor T21, a first electrode connected to the first frequency divider control unit 24, and a second electrode connected to the output sub-circuit 22. Here, control1 is the first frequency divider signal, and control2 is the second frequency divider signal.

[0040] As one embodiment of the stage transmission circuit 21, the stage transmission circuit 21 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 includes a control electrode connected to the third transistor T3 and receiving a stage transmission control signal, a first electrode connected to a first power supply line VGH1, and a second electrode connected to the second transistor T2 and outputting a stage transmission signal. The second transistor T2 includes a control electrode receiving a first pull-down control signal, a first electrode connected to the first transistor T1, and a second electrode connected to a second power supply line VGH2. The third transistor T3 includes a control electrode receiving a second pull-down control signal, a first electrode connected to the first transistor T1, and a second electrode receiving a third power supply voltage.

[0041] As an example, assuming that the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors, the cascade control circuit, the control electrode of the first transistor T1, and the second electrode of the second transistor T2 are connected to the fifth node. When the cascade control circuit outputs a low-level cascade control signal, the first transistor T1 is turned on, and a high-level cascade signal is output according to the first power signal transmitted on the first power line VGH1.

[0042] As an example, when the seventh transistor T7 outputs a low-level first pull-down control signal according to the stage transmission signal transmitted by the preceding stage circuit, the second transistor T2 and the third transistor T3 are turned on. The second transistor T2 pulls up the control electrode of the first transistor T1 through the second power supply signal transmitted on the second power supply line VGH2, so that the first transistor T1 is turned off. At the same time, the third transistor T3 discharges the residual charge on the second electrode of the first transistor T1 through the third power supply signal transmitted on the third unit line, thereby rapidly pulling down the stage transmission signal.

[0043] The first and second power signals can be high-level signals, and the third power signal can be a low-level signal.

[0044] In the above embodiment, during the process of the first transistor T1 being turned on and outputting the stage transmission signal according to the first power signal, the first power signal borrows the energy of the first power line VGH1 of the first driving circuit 1. On the one hand, it can reduce the deload phenomenon on the second power line VGH2. On the other hand, when the second power line VGH2 is affected by the deload and the potential becomes unstable, it will not affect the output of the stage transmission signal, thereby enabling the second driving circuit 2 to perform stage transmission normally.

[0045] As one embodiment of the output sub-circuit 22, the output sub-circuit 22 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The fourth transistor T4 includes a control electrode connected to the fifth transistor T5 and receiving an output control signal, a first electrode connected to the second power supply line VGH2, and a second electrode connected to the sixth transistor T6 and outputting a threshold compensation signal Nscan1(n). The fifth transistor T5 includes a control electrode receiving a first pull-down control signal, a first electrode connected to the fourth transistor T4, and a second electrode connected to the second power supply line VGH2. The sixth transistor T6 includes a control electrode receiving a second pull-down control signal, a first electrode connected to the fourth transistor T4, and a second electrode receiving a third power supply voltage.

[0046] As an example, when the second frequency division control unit 25 outputs a low-level output control signal to the control electrode of the fourth transistor T4, the fourth transistor T4 is turned on to output a high-level threshold compensation signal Nscan1(n) according to the second power signal transmitted on the second power line VGH2. The fifth transistor T5 and the sixth transistor T6 are turned on according to the potential of the first node. The fifth transistor T5 pulls up the control electrode of the fourth transistor T4, and the sixth transistor T6 resets the residual charge on the second electrode of the fourth transistor T4, thereby realizing the rapid pull-down of the threshold compensation signal Nscan1(n).

[0047] In the above embodiment, the output control signal output by the second frequency division control circuit controls the on / off state of the fourth transistor T4, and causes the fourth transistor T4 to output a threshold compensation signal Nscan1(n) according to the second power signal transmitted on the second power line VGH2 when it is in the on state. When the corresponding thin film transistor in the pixel circuit operates to deload the second power line VGH2, it will not affect the operation of the stage transmission circuit 21.

[0048] Reference Figure 6As one implementation of a pixel circuit, the pixel circuit includes a first thin-film transistor T1A, a second thin-film transistor T2A, a third thin-film transistor T3A, a fourth thin-film transistor T4A, a fifth thin-film transistor T5A, a sixth thin-film transistor T6A, a seventh thin-film transistor T7A, and an eighth thin-film transistor T8A. The first thin-film transistor T1A includes a first electrode connected to a data signal, a first electrode connected to a first node, and a second electrode connected to a third driving circuit 3. The second thin-film transistor T2A includes a first electrode connected to a first node, a second electrode connected to a second node, and a control electrode connected to the third thin-film transistor T3A. The third thin-film transistor T3A includes a first electrode connected to a third node, a second electrode connected to a second node, and a control electrode connected to a threshold compensation signal Nscan1(n). The fourth thin-film transistor T4A includes a first electrode connected to a fourth power supply voltage, a second electrode connected to a third node, and a control electrode connected to a first reset control signal Nscan2. The fifth thin-film transistor T5A includes a first electrode connected to a fifth power supply voltage, a second electrode connected to a light-emitting device, and a control electrode connected to a second reset control signal Pscan2. The sixth thin-film transistor T6A includes a first electrode connected to a sixth power supply voltage, a second electrode connected to a first node, and a control electrode connected to a second reset control signal Pscan2. The seventh thin-film transistor T7A includes a first electrode connected to a seventh power supply voltage, a second electrode connected to a first node, and a control electrode connected to a light-emitting control signal EM. The eighth thin-film transistor T8A includes a first electrode connected to a second node, a second electrode connected to a light-emitting device, and a control electrode connected to a light-emitting control signal EM.

[0049] Among them, the fourth, fifth, and sixth power supply voltages can be reset voltages for low-level states, and the seventh power supply voltage is the voltage used to provide light-emitting energy. The first thin-film transistor T1A, the second thin-film transistor T2A, the fifth thin-film transistor T5A, the sixth thin-film transistor T6A, the seventh thin-film transistor T7A, and the eighth thin-film transistor T8A can be P-type transistors, while the third thin-film transistor T3A and the fourth thin-film transistor T4A can be N-type transistors. The second thin-film transistor T2A is the driving transistor in the pixel circuit.

[0050] As an example, the light emission control of the light-emitting device D1 is achieved through the scanning signal Pscan1, the threshold compensation signal Nscan1(n), the first reset control signal Nscan2, the second reset control signal Pscan2, and the light emission control signal EM. Specifically, firstly, the seventh thin-film transistor T7A and the eighth thin-film transistor T8A are turned off, while the fifth thin-film transistor T5A and the sixth thin-film transistor T6A are turned on to reset the anode of the light-emitting device and the second thin-film transistor T2A. Then, the fourth thin-film transistor T4A is turned on to reset the control electrode of the second thin-film transistor T2A, and the third thin-film transistor T3A is turned on to reset the first and second electrodes of the second thin-film transistor T2A. Next, the fourth thin-film transistor T4A is turned off, while the first thin-film transistor T1A and the third thin-film transistor T3A are turned on, so that the data signal passes through the first thin-film transistor T1A, the second thin-film transistor T2A, and the third thin-film transistor T3A to the control electrode of the second thin-film transistor T2A to perform threshold compensation on the second thin-film transistor T2A. Next, the fifth thin-film transistor T5A and the sixth thin-film transistor T6A are turned on, resetting the anode of the light-emitting device and the second thin-film transistor T2A. Finally, the seventh thin-film transistor T7A and the eighth thin-film transistor T8A are turned on, at which point the second thin-film transistor T2A is turned on according to the written data signal, causing the light-emitting device to start emitting light.

[0051] In the threshold compensation process for the second thin-film transistor T2A, the third thin-film transistor T3A needs to be continuously turned on, and the degree of conduction of the third thin-film transistor T3A is related to the effectiveness of the threshold compensation. This places high demands on the signal quality of the threshold compensation signal Nscan1(n). If the ripple of the threshold compensation signal Nscan1(n) is large due to the de-loading phenomenon of the second power line VGH2, it may lead to a potential difference at the control electrode of the second thin-film transistor T2A, resulting in inconsistent odd and even row light emission. Improving the de-loading phenomenon of the second power line VGH2 can reduce the ripple of the threshold compensation signal Nscan1(n), thereby improving the potential difference of the second thin-film transistor T2A and enhancing display consistency.

[0052] As an example, since the reset operation for the anode of the light-emitting device and the second thin-film transistor T2A requires a short time and only releases the residual charge on the anode of the light-emitting device and the second thin-film transistor T2A, there is no significant voltage change during the reset operation. Therefore, the voltage sources corresponding to the second reset control signal Pscan2 controlling the sixth thin-film transistor T6A and the fifth thin-film transistor T5A, and the first reset control signal Nscan2 controlling the fourth thin-film transistor T4A, are generally relatively stable and have small loads.

[0053] Thus, the target drive signal CON can be at least one of the first reset control signal Nscan2, the second reset control signal Pscan2, and the light emission control signal EM. When the stage transmission circuit 21 borrows energy from the voltage sources corresponding to the first reset control signal Nscan2, the second reset control signal Pscan2, and the light emission control signal EM through the first power supply line VGH1, it is less likely to affect the stability of the first reset control signal Nscan2, the second reset control signal Pscan2, and the light emission control signal EM.

[0054] In the first embodiment, the target drive signal CON is the first reset control signal Nscan2. The first drive circuit 1 is connected to the fourth thin film transistor T4A and is used to output the first reset control signal Nscan2 to the control electrode of the fourth thin film transistor T4A.

[0055] As an example, when the target drive signal CON is the first reset control signal Nscan2, the first drive circuit 1 can be the first reset circuit 12.

[0056] In the second embodiment, the target drive signal CON is the second reset control signal Pscan2. The first drive circuit 1 is connected to the fifth thin-film transistor T5A and the sixth thin-film transistor T6A, and is used to output the second reset control signal Pscan2 to the control electrode of the fifth thin-film transistor T5A and the control electrode of the sixth thin-film transistor T6A.

[0057] As an example, when the target drive signal CON is the second reset control signal Pscan2, the first drive circuit 1 can be the second reset circuit 13.

[0058] In the third embodiment, the target driving signal CON is the light emission control signal EM. The first driving circuit 1 is connected to the seventh thin film transistor T7A and the eighth thin film transistor T8A and is used to output the light emission control signal EM to the seventh thin film transistor T7A and the eighth thin film transistor T8A.

[0059] As an example, when the target driving signal CON is the light emission control signal EM, the first driving circuit 1 can be the light emission control circuit 14.

[0060] As an example, in a gate driving device, the first reset circuit 12, the second reset circuit 13, and the light emission control circuit 14 are usually equipped with independent power supplies. In this way, the stage transmission sub-circuit 21 can borrow any one of the power supplies corresponding to the first reset circuit 12, the second reset circuit 13, and the light emission control circuit 14 through the first power supply line VGH1, so that the stage transmission signal output by the stage transmission sub-circuit 21 is not affected by the deload on the second power supply line VGH2, and at the same time, the load on the second power supply line VGH2 is reduced, so that the second power supply line VGH2 can supply power to the output sub-circuit 22 more stably, thereby improving the quality of the threshold compensation signal Nscan1(n) output by the output sub-circuit 22, and thus improving the stability of the pixel circuit operation.

[0061] According to a second aspect of this disclosure, a display panel is provided that includes the gate driving device described above. This display panel possesses all the beneficial effects of the gate driving device described above, which will not be elaborated further herein.

[0062] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0064] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0065] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A gate driving device, characterized in that, It includes a first power line, a second power line, multiple cascaded first drive circuits, and multiple cascaded second drive circuits; The first driving circuit is connected to the first power line and is used to output the target driving signal to the pixel circuit; The second driving circuit includes a stage transmission sub-circuit and an output sub-circuit; wherein, the stage transmission sub-circuit is connected to the first power line and is used to output a stage transmission signal to the subsequent circuit of the stage transmission sub-circuit according to the first power supply voltage transmitted by the first power line; the output sub-circuit is connected to the second power line and is used to output a threshold compensation signal to the pixel circuit according to the second power supply voltage transmitted by the second power line; wherein, the first power supply voltage and the second power supply voltage are high-level signals, and are connected to the first power line through the stage transmission sub-circuit to reduce the voltage drop phenomenon on the second power line.

2. The gate driving device according to claim 1, characterized in that, It also includes multiple cascaded third driving circuits, each of which is used to output a scan signal to the corresponding row of pixel circuits; The output sub-circuit of each stage of the second driving circuit is used to output the threshold compensation signal to the corresponding two rows of pixel circuits.

3. The gate driving device according to claim 1, characterized in that, The second driving circuit further includes a stage transmission control sub-circuit, which is connected to the front-end circuit of the stage transmission sub-circuit, and is used to output a first pull-down control signal, a second pull-down control signal, a stage transmission control signal and an output control signal according to the stage transmission signal output from the front-end circuit of the stage transmission sub-circuit. The stage transmission sub-circuit is also connected to the stage transmission control sub-circuit, and is used to output the stage transmission signal according to the first power supply voltage, the stage transmission control signal, the first pull-down control signal and the second pull-down control signal; The output sub-circuit and the second power line output the threshold compensation signal according to the second power supply voltage, the output control signal, the first pull-down control signal and the second pull-down control signal.

4. The gate driving device according to claim 3, characterized in that, The stage-transfer circuit includes a first transistor, a second transistor, and a third transistor; The first transistor includes a control electrode connected to the third transistor and connected to the stage transmission control signal, a first electrode connected to the first power line, and a second electrode connected to the second transistor and outputting the stage transmission signal; The second transistor includes a control electrode connected to the first pull-down control signal, a first electrode connected to the first transistor, and a second electrode connected to the second power line; The third transistor includes a control electrode that receives the second pull-down control signal, a first electrode that is connected to the first transistor, and a second electrode that receives the third power supply voltage.

5. The gate driving device according to claim 4, characterized in that, The output sub-circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; The fourth transistor includes a control electrode connected to the fifth transistor and connected to the output control signal, a first electrode connected to the second power line, and a second electrode connected to the sixth transistor and connected to the threshold compensation signal. The fifth transistor includes a control electrode connected to the first pull-down control signal, a first electrode connected to the fourth transistor, and a second electrode connected to the second power line. The sixth transistor includes a control electrode that receives the second pull-down control signal, a first electrode that is connected to the fourth transistor, and a second electrode that receives the third power supply voltage.

6. The gate driving device according to claim 2, characterized in that, The pixel circuit includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a sixth thin-film transistor, a seventh thin-film transistor, and an eighth thin-film transistor. The first thin-film transistor includes a first electrode for receiving data signals, a first electrode connected to a first node, and a second electrode connected to the third driving circuit; The second thin-film transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to the third thin-film transistor; The third thin-film transistor includes a first electrode connected to the third node, a second electrode connected to the second node, and a control electrode connected to the threshold compensation signal; The fourth thin-film transistor includes a first electrode connected to a fourth power supply voltage, a second electrode connected to the third node, and a control electrode connected to a first reset control signal. The fifth thin-film transistor includes a first electrode connected to a fifth power supply voltage, a second electrode connected to a light-emitting device, and a control electrode connected to a second reset control signal. The sixth thin-film transistor includes a first electrode connected to a sixth power supply voltage, a second electrode connected to the first node, and a control electrode connected to the second reset control signal. The seventh thin-film transistor includes a first electrode connected to a seventh power supply voltage, a second electrode connected to the first node, and a control electrode connected to a light emission control signal. The eighth thin-film transistor includes a first electrode connected to the second node, a second electrode connected to the light-emitting device, and a control electrode that receives the light-emitting control signal. The target driving signal is at least one of the first reset control signal, the second reset control signal, and the light emission control signal.

7. The gate driving device according to claim 6, characterized in that, The target driving signal is the first reset control signal. The first driving circuit is connected to the fourth thin-film transistor and is used to output the first reset control signal to the control electrode of the fourth thin-film transistor.

8. The gate driving device according to claim 6, characterized in that, The target driving signal is the second reset control signal. The first driving circuit is connected to the fifth thin-film transistor and the sixth thin-film transistor, and is used to output the second reset control signal to the control electrode of the fifth thin-film transistor and the control electrode of the sixth thin-film transistor.

9. The gate driving device according to claim 6, characterized in that, The target driving signal is the light emission control signal. The first driving circuit is connected to the seventh thin-film transistor and the eighth thin-film transistor and is used to output the light emission control signal to the seventh thin-film transistor and the eighth thin-film transistor.

10. A display panel, characterized in that, Includes the gate driving device according to any one of claims 1 to 9.

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