Semiconductor structure and method of manufacturing the same, electronic device

Abstract

The application relates to a semiconductor structure and a preparation method thereof and an electronic device, and comprises the following steps: providing a substrate, wherein the substrate comprises a gate oxide layer and a gate conductive layer; forming a patterned buffer layer, a barrier layer, a sacrificial layer and a photoresist layer in sequence on the top surface of the gate conductive layer; the barrier layer blocks the outward diffusion of N elements in the gate oxide layer, so that the width difference of adjacent photoresist layers in the direction towards the substrate is within a first target accuracy range; after the adjacent photoresist layer and the sacrificial layer are removed, a gate is formed based on the patterned buffer layer and the barrier layer; the width difference of adjacent gates in the direction towards the substrate is within a second target accuracy range; and the second target accuracy range is related to the first target accuracy range. The application can effectively solve the problem that the CD uniformity is difficult to accurately control in the existing process; and the barrier layer and the buffer layer can effectively block the outward diffusion of N elements in the gate oxide layer, reduce the risk of photoresist poisoning, and thus improve the poly gate CD uniformity.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] With the continuous miniaturization of integrated circuits, the critical dimension (CD) of devices continues to shrink, and the requirements for photolithography accuracy are becoming increasingly stringent.

[0003] In existing technologies, the gate oxide layer is typically subjected to decoupled plasma nitridation (DPN) to improve the stability of ultrathin gate oxides.

[0004] However, the existing anti-reflective layer (BARC) cannot effectively block the spillover and diffusion of nitrogen elements in the gate oxide layer after DPN, resulting in photoresist poisoning. This causes the photoresist pattern to exhibit asymmetrical sidewall morphology and bottom critical size loss after development, severely damaging the pattern transfer fidelity and greatly affecting the uniformity of polysilicon gate current distribution (CD). This leads to adverse effects such as unstable device threshold voltage, abnormal current characteristics, and increased leakage current. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method, as well as an electronic device, to address the technical problems in the existing technology, so as to at least reduce the risk of photoresist poisoning caused by DPN.

[0006] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate, wherein a first surface of the substrate includes a gate oxide layer and a gate conductive layer;

[0007] A patterned buffer layer, barrier layer, sacrificial layer, and photoresist layer are formed on the top surface of the gate conductive layer in a direction away from the substrate. The barrier layer prevents the N element in the gate oxide layer from overflowing and diffusing, so that the width difference between adjacent photoresist layers in the direction toward the substrate is within the first target accuracy range.

[0008] After removing the adjacent photoresist layer and sacrificial layer, a gate is formed based on a patterned buffer layer and a barrier layer; the width difference between adjacent gates in the direction toward the substrate is within the second target accuracy range;

[0009] The width is used to characterize the dimension along a first direction parallel to the first surface; the second target accuracy range is associated with the first target accuracy range.

[0010] In the semiconductor structure fabrication method described in the above embodiments, the precision of the photoresist layer directly affects the precision of the gate (i.e., the second target precision range is related to the first target precision range), involving the transmission of process errors. By adding a barrier layer as a transition layer for the poly gate CD window, the influence of etching angle deviation on the pattern is suppressed, greatly improving the controllability of the poly gate CD and effectively solving the problem of difficulty in precisely controlling CD uniformity in existing processes. In addition, the newly added barrier layer and buffer layer between the poly and sacrificial layers can effectively block the spillover diffusion of N elements in the gate oxide layer, reducing the risk of photoresist poisoning, thereby achieving the goal of improving the uniformity of the poly gate CD.

[0011] In some embodiments, a patterned buffer layer, barrier layer, sacrificial layer, and photoresist layer are formed, including:

[0012] A buffer layer, a barrier layer, a sacrificial layer, and a photoresist layer are formed sequentially on the top surface of the gate conductive layer along the direction away from the substrate.

[0013] Patterned photoresist layer;

[0014] Based on the photoresist layer, patterned buffer layers, barrier layers, and sacrificial layers are formed, as well as trenches located between adjacent patterned barrier layers and sacrificial layers; the bottom surface of the trenches is lower than the bottom surface of the barrier layers.

[0015] In some embodiments, the width of the trench is the same in the direction toward the substrate.

[0016] In some embodiments, the accuracy range of the second target is not greater than the accuracy range of the first target.

[0017] In some embodiments, the thickness of the barrier layer ranges from 100 Å to 500 Å;

[0018] The thickness of the buffer layer ranges from 100 Å to 500 Å.

[0019] In some embodiments, the sacrificial layer includes a mask layer, a nitrogen-free dielectric antireflective coating (NFDARC), and a dielectric antireflective coating (BARC) arranged sequentially in the direction away from the substrate.

[0020] In some embodiments, the material of the barrier layer includes silicon nitride, titanium nitride, silicon oxynitride, oxygen-doped silicon carbide, silicon carbide, or a combination thereof;

[0021] The material of the buffer layer includes oxides or doped oxides.

[0022] In some embodiments, after the gate oxide layer is formed, a decoupled plasma nitriding process is performed on the gate oxide layer.

[0023] Secondly, this application also provides a semiconductor structure prepared by the preparation method described in any of the above embodiments.

[0024] Thirdly, this application also provides an electronic device, including the semiconductor structure as described in the above embodiments.

[0025] Since the semiconductor structure and electronic device described above are based on the same inventive concept as the semiconductor structure preparation method provided by the present invention, the semiconductor structure prepared by this preparation method or the electronic device including the semiconductor structure has all the advantages of the semiconductor structure preparation method provided by the present invention, which will not be elaborated here.

[0026] The semiconductor structure, its fabrication method, and the electronic device provided in this application have the following unexpected technical effects:

[0027] Based on existing wafer fabrication, a composite functional structure of barrier layer and buffer layer is introduced to effectively suppress the spillover diffusion of N element after DPN of gate oxide layer, thereby eliminating pattern distortion caused by photoresist poisoning.

[0028] In addition, a segmented etching strategy is adopted, and a barrier layer is used to fix the outline of the etching window, which effectively resists the pattern distortion caused by etching angle deviation. Combined with the etching stop protection function of the buffer layer, the dimensional accuracy and structural integrity of the gate conductive layer are ensured, and the uniformity of critical dimensions (CD) is significantly improved. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart of a semiconductor structure fabrication method provided in one embodiment;

[0031] Figure 2 This is a schematic cross-sectional view of the structure obtained after forming the gate oxide layer and the gate conductive layer in step S102 of the preparation method provided in one embodiment;

[0032] Figure 3 This is a cross-sectional schematic diagram of the structure obtained after forming a buffer layer, a barrier layer, a sacrificial layer and a photoresist layer in step S202 of the preparation method provided in one embodiment;

[0033] Figure 4 for Figure 3 A cross-sectional schematic diagram of the structure obtained by patterning the buffer layer, barrier layer, sacrificial layer and photoresist layer;

[0034] Figure 5 This is a schematic cross-sectional view of the structure obtained after removing the photoresist layer and the sacrificial layer in step S302 of the preparation method provided in one embodiment;

[0035] Figure 6 This is a schematic cross-sectional view of the structure obtained after etching the gate conductive layer in step S304 of the preparation method provided in one embodiment;

[0036] Figure 7 This is a cross-sectional schematic diagram of the structure obtained after removing the buffer layer and the barrier layer in step S306 of the preparation method provided in one embodiment.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10. Substrate; 11. Gate oxide layer; 12. Gate conductive layer; 13. Buffer layer; 14. Barrier layer; 15. Sacrificial layer; 151. Mask layer; 152. Nitrogen-free dielectric antireflective coating; 153. Dielectric antireflective coating; 16. Photoresist layer; 20. Trench; 30. Gate. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0045] Aside from the incomplete pattern transfer issue caused by photoresist poisoning, current mainstream semiconductor device gate structures generally employ single-pass etching technology. However, constrained by both photolithography resolution and the dry etching process window, coupled with the mechanical stress introduced during wafer loading, the etching angle is difficult to control precisely. This angular deviation directly leads to distortion of the process window, severely reducing the fidelity during pattern transfer and affecting the accuracy of critical device dimensions and electrical performance.

[0046] Therefore, how to reduce the impact of the etching process on the process window without affecting the transfer of the photoresist layer pattern has become a technical problem that needs to be solved by people in this field.

[0047] Based on this, please refer to Figure 1 This application provides a method for fabricating a semiconductor structure, including steps S102-S106. It should be noted that, in this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. The first and second directions are perpendicular to each other. In this embodiment, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction.

[0048] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0049] The following is a detailed explanation of the above steps, with reference to the accompanying diagram.

[0050] Step S102: Provide a substrate 10, the first surface 10a of the substrate 10 including a gate oxide layer 11 and a gate conductive layer 12.

[0051] For example, the substrate can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate can include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can also include Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrates. In this embodiment, the material of the substrate 10 includes silicon (Si), and the gate conductive layer 12 includes doped polycrystalline silicon material.

[0052] Specifically, please refer to Figure 2 First, an in-situ steam generation (ISSG) process is used to form a gate oxide layer 11. Then, one or more processes, including but not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), and high density plasma deposition (HDP), can be used to form a gate conductive layer 12 covering the top surface of the gate oxide layer 11.

[0053] Furthermore, in some embodiments, after forming the gate oxide layer 11, a decoupling plasma nitriding process is performed on the gate oxide layer 11. Oxide nitrides or oxynitrides are used instead of pure silicon dioxide (SiO2) generated via ISSG, thereby increasing the dielectric constant of the gate oxide layer and repairing internal oxygen vacancy defects.

[0054] Step S104: A patterned buffer layer 13, barrier layer 14, sacrificial layer 15 and photoresist layer 16 are formed on the top surface of the gate conductive layer 12 in a direction away from the substrate (the opposite direction of the XO direction and the OX direction); the barrier layer 14 blocks the outflow and diffusion of N element in the gate oxide layer 11, so that the width difference between adjacent photoresist layers 16 in the direction toward the substrate is within the first target accuracy range.

[0055] Please see Figures 3-4 The extension step of step S104 includes:

[0056] Please see Figure 3 Step S202: A buffer layer 13, a barrier layer 14, a sacrificial layer 15 and a photoresist layer 16 are formed sequentially on the top surface of the gate conductive layer 12 along the direction away from the substrate. The buffer layer 13, the barrier layer 14 and the sacrificial layer 15 can be formed by any of the deposition process or the process of coating a dielectric layer (Spin-on Dielectric, SOD). Subsequently, the photoresist layer 16 is coated on the top surface of the sacrificial layer 15.

[0057] In some embodiments, the thickness of the buffer layer 13 ranges from 100 Å to 500 Å.

[0058] The thickness of the barrier layer 14 ranges from 100 Å to 500 Å.

[0059] For example, in some embodiments, the material of the buffer layer 13 includes, but is not limited to, oxides, doped oxides, or low-temperature deposited oxides;

[0060] The material of the barrier layer 14 includes, but is not limited to, silicon nitride (SiNx), titanium nitride (TiN), silicon oxynitride (SiON), oxygen-doped silicon carbide (ODC), silicon carbide (SiC), or combinations thereof.

[0061] In the above embodiments, the barrier layer 14 is used to prevent the leakage of N element in the gate oxide layer 11 along the XO direction; the gate conductive layer 12 (polysilicon) and the barrier layer 14 have different coefficients of thermal expansion, and the buffer layer 13 can relieve thermal stress, prevent delamination or cracking, improve the adhesion between polysilicon and the barrier layer, and prevent peeling.

[0062] Furthermore, in some embodiments, the sacrificial layer 15 includes a mask layer 151, a nitrogen-free dielectric antireflective coating 152, and a dielectric antireflective coating 153 arranged sequentially along the direction away from the substrate (XO direction). The sum of the thicknesses of the nitrogen-free dielectric antireflective coating 152 and the dielectric antireflective coating 153 is equal to the standard thickness of a normal antireflective coating required for the process.

[0063] In the above embodiments, since the nitrogen-containing components in the lower layer materials (gate oxide layer 11, barrier layer 14, or buffer layer 13, etc.) evaporate upward during the preparation of the anti-reflective coating, and accumulate on the surface of the anti-reflective coating and combine with moisture in the air to form alkaline chemical substances, this embodiment uses a nitrogen-free dielectric anti-reflective coating 152 instead of the traditional NDC (silicon carbide) to prevent the diffusion of active nitrogen components in nitrogen-doped silicon carbide. At the same time, the preparation process of the anti-reflective coating is optimized by using a batch deposition method and interspersing the deionized water wetting, cleaning and drying process of the wafer substrate between batches, effectively removing alkaline contaminants adsorbed on the surface of the anti-reflective coating, thereby further reducing the risk of photoresist poisoning during the patterning process.

[0064] Please see Figure 4 Step S204: Patterning photoresist layer 16;

[0065] Step S206: Based on the photoresist layer 16, a patterned buffer layer 13, a barrier layer 14, and a sacrificial layer 15 are formed, as well as a trench 20 located between adjacent patterned barrier layers 14 and sacrificial layers 15; the bottom surface of the trench 20 is lower than the bottom surface of the barrier layer 14.

[0066] In this embodiment, the width of the trench 20 is the same along the OX direction. Therefore, in the above embodiment, the barrier layer 14 can stably fix the pattern outline of the etching window, effectively resisting interference caused by changes in the tilt angle during the etching process, ensuring the accuracy and consistency of the pattern size. The buffer layer 13, as an etching stop layer, protects the surface of the gate conductive layer 12 from etching damage, thereby ensuring the integrity of the gate structure and the reliability of the device's electrical performance.

[0067] Step S106: After removing the adjacent photoresist layer 16 and sacrificial layer 15, a gate 30 is formed based on the patterned buffer layer 13 and barrier layer 14; the width difference between adjacent gates 30 in the direction toward the substrate is within the second target accuracy range; wherein, the width is used to characterize the dimension along the first direction (OY direction) parallel to the first surface 10a; the second target accuracy range is associated with the first target accuracy range.

[0068] Please see Figures 5-7 The extension step of step S106 includes:

[0069] Step S302: Remove the photoresist layer 16 and sacrificial layer 15 using a wet stripping process to obtain the following... Figure 5 The structure shown.

[0070] Step S304: Etch the buffer layer 13 and the gate conductive layer 12 along the trench 20 to transfer the pattern to the gate conductive layer 12, resulting in... Figure 6 The structure shown.

[0071] Step S306: Etch and wet strip to remove the buffer layer 13 and the barrier layer 14, forming gates 30 spaced apart along the first direction (OY direction), resulting in... Figure 7 The structure shown.

[0072] The second target accuracy range is related to the first target accuracy range. In some embodiments, the second target accuracy range is not greater than the first target accuracy range.

[0073] Since the precision of the photoresist layer directly affects the precision of the gate and involves the transmission of process errors, in the above embodiment, by reducing the risk of photoresist poisoning, the contour uniformity of the photoresist layer is significantly improved. At the same time, the buffer layer 13 and the barrier layer 14 are used to fix the etching window, suppress the influence of etching angle deviation on the pattern, and greatly improve the pattern transfer precision of the photolithography and etching processes. This effectively improves CD uniformity and enhances the stability and yield of the process.

[0074] The semiconductor structure obtained after steps S102-S106 can be found in [reference]. Figure 7 For ease of understanding this application, Figure 7 This application provides an example of a semiconductor structure prepared using the method described herein. Other suitable examples of semiconductor structures prepared using this application are also possible, and no limitations are imposed herein.

[0075] In some embodiments, this application also provides a semiconductor structure prepared by the preparation method described in any of the above embodiments.

[0076] In the above embodiments, compared with the existing structure, the preparation method provided by this application can achieve higher fidelity in the photolithography pattern transfer process, and effectively improve the problems of threshold voltage instability, abnormal current characteristics and increased leakage current caused by poor CD uniformity.

[0077] In some embodiments, this application also provides an electronic device including the semiconductor structure described in the above embodiments.

[0078] In the above embodiments, due to the improvement in the accuracy and stability of key dimensions, the electrical performance dispersion of semiconductor devices in electronic devices is reduced, and the performance consistency between devices is significantly enhanced, thereby optimizing the overall operational stability and reliability of electronic devices. Compared with traditional devices, it shows obvious advantages in power consumption control and signal transmission stability.

[0079] The semiconductor structure, its fabrication method, and the electronic device provided in this application have the following unexpected technical effects:

[0080] In the fabrication method provided in this application, in order to address the photoresist poisoning problem caused by nitrogen diffusion after decoupling plasma nitriding (DPN) of the gate oxide layer in traditional processes, a composite functional structure of a barrier layer and a buffer layer is introduced on the basis of existing wafer fabrication. This effectively suppresses the spillover diffusion of N elements after DPN of the gate oxide layer, thereby eliminating the pattern distortion caused by photoresist poisoning.

[0081] In addition, a segmented etching strategy is adopted, and a barrier layer is used to fix the outline of the etching window, which effectively resists the pattern distortion caused by etching angle deviation. Combined with the etching stop protection function of the buffer layer, the dimensional accuracy and structural integrity of the gate conductive layer are ensured, and the uniformity of critical dimensions (CD) is significantly improved.

[0082] Through the synergistic effect of the above technologies, the propagation of process errors is systematically reduced, ultimately achieving a significant improvement in the uniformity of critical dimensions (CD) of semiconductor devices. This greatly reduces defects such as threshold voltage fluctuations and abnormal leakage currents, improves process stability and device yield, and provides a reliable technical path for high-performance integrated circuit manufacturing.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a gate oxide layer and a gate conductive layer are included on a first surface of the substrate; A patterned buffer layer, a barrier layer, a sacrificial layer, and a photoresist layer are formed on the top surface of the gate conductive layer in a direction away from the substrate; the barrier layer prevents the outflow and diffusion of N element in the gate oxide layer, so that the width difference between adjacent photoresist layers in the direction toward the substrate is within a first target accuracy range; After removing the adjacent photoresist layers and the sacrificial layer, a gate is formed based on the patterned buffer layer and barrier layer; the width difference between adjacent gates in the direction toward the substrate is within the second target accuracy range; The width is used to characterize the dimension along a first direction parallel to the first surface; the second target accuracy range is associated with the first target accuracy range.

2. The preparation method according to claim 1, characterized in that, The formation of the patterned buffer layer, the barrier layer, the sacrificial layer, and the photoresist layer includes: A buffer layer, a barrier layer, a sacrificial layer, and a photoresist layer are formed sequentially on the top surface of the gate conductive layer along a direction away from the substrate; Pattern the photoresist layer; Based on the photoresist layer, a patterned buffer layer, a barrier layer, and a sacrificial layer are formed, as well as a trench located between adjacent patterned barrier layers and sacrificial layers; the bottom surface of the trench is lower than the bottom surface of the barrier layer.

3. The preparation method according to claim 2, characterized in that, The width of the trench is the same in the direction toward the substrate.

4. The preparation method according to claim 1, characterized in that, The accuracy range of the second target is not greater than the accuracy range of the first target.

5. The preparation method according to claim 1, characterized in that, The thickness of the barrier layer ranges from 100 Å to 500 Å; The thickness of the buffer layer ranges from 100 Å to 500 Å.

6. The preparation method according to claim 1, characterized in that, The sacrificial layer comprises a mask layer, a nitrogen-free dielectric antireflective coating, and a dielectric antireflective coating arranged sequentially in a direction away from the substrate.

7. The preparation method according to any one of claims 1-4, characterized in that, The material of the barrier layer includes silicon nitride, titanium nitride, silicon oxynitride, oxygen-doped silicon carbide, silicon carbide, or a combination thereof; The material of the buffer layer includes oxides or doped oxides.

8. The preparation method according to any one of claims 1-4, characterized in that, After the gate oxide layer is formed, a decoupled plasma nitriding process is performed on the gate oxide layer.

9. A semiconductor structure, characterized in that, It is prepared by the preparation method described in any one of claims 1-8.

10. An electronic device, characterized in that, include: The semiconductor structure as described in claim 9.

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