Capacitor open-short circuit test architecture, method and platform suitable for boundary scanning

Abstract

The invention discloses a capacitor open and short circuit test architecture, method and platform suitable for boundary scanning. The architecture comprises a simulation test card unit, and a to-be-tested board unit and a boundary scanning controller unit which are electrically connected with the simulation test card unit; the boundary scanning controller unit is used for providing a clock driving signal TCK, a state driving signal TMS, a data driving signal TDI, a data receiving signal TDO and a driving signal DO3; a TCK pin, a TMS pin and a TDI pin of the boundary scan controller unit are respectively connected to a JTAG clock receiving TCK1 pin, a state receiving TMS1 pin and a data receiving TDI1 pin of a first BS chip in the to-be-tested board unit; according to the framework, the method and the platform corresponding to the framework, no matter whether the IEEE 1149.6 protocol is supported or not, the purpose that the open circuit and the short circuit of the coupling capacitor connection relation can be tested through the IEEE 1149.1 protocol can be achieved, the test coverage rate is increased, and the test design cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of boundary scan testing technology, and in particular relates to a capacitor open-circuit and short-circuit testing architecture, method and platform suitable for boundary scan. Background Art

[0002] In the field of boundary scan test fixtures, the pin of the boundary scan chip (BS chip) on the board under test (DUT) is connected to one leg of a capacitor, and the other leg of the capacitor is connected to the HDMI, USB, PCIE and other test connectors. The connection relationship from the BS chip on the DUT to the capacitor and then to the test connector is called the coupling capacitor connection relationship. The signal connected to the capacitor by the BS chip is usually a low voltage differential signal (LVDS signal). It is necessary to use a chip that supports the IEEE 1149.6 protocol to complete the open and short circuit test to achieve the purpose of measuring the open circuit (cold solder joint) and short circuit (breakdown) of the capacitive coupling link. However, not all tests with coupling capacitor signal connection relationships on the DUT can be completed through the IEEE 1149.6 protocol. For example, common FPGA chips on the market, such as the model: LCMXO3LF-4300C-5BG256C chip, do not support the IEEE 1149.6 protocol, but support the coupling capacitor signal function. The open and short circuit test of the coupling capacitor signal connection relationship of this type of chip cannot be completed through the IEEE 1149.6 protocol. When encountering this practical problem, it is necessary to propose a method to use the IEEE 1149.1 achieves testability to meet customer testing needs.

[0003] There are two testing methods for the boundary scan open-short circuit test of the coupling capacitor connection scenario, in the case of testing that supports the IEEE 1149.6 protocol. One method is to short-circuit the LVDS transmitting signal and receiving signal of the BS chip of the DUT to form a loop, thereby completing the signal transmission and reception between the transmitting and receiving ends to achieve the test purpose. However, making a short circuit to form a loop may protect the short circuit fault between the transmitting and receiving ends. Therefore, this method has its defects. The other method is to connect the output and input ends of the LVDS signal to the boundary scan simulation test card (DUMMY card) that supports the IEEE 1149.6 protocol respectively. The DUMMY card that supports the IEEE 1149.6 protocol requires IEEE Chips that support the 1149.6 protocol, such as the low-voltage differential (LVDS) chip: SCAN15MB200TSQ / NOPB, only have 6 pairs of LVDS transmit and 6 pairs of LVDS receive. LVDS resources are limited. Faced with a large number of LVDS signal test scenarios, many chips need to be connected in series to form a combination chain. The unit price of a SCAN15MB200TSQ / NOPB chip is more than 100 yuan, which is relatively expensive. Therefore, it is urgent to find a way to solve the above problems and defects and reduce costs.

[0004] The open-circuit and short-circuit test of the coupling capacitor involves open-circuit and short-circuit fault tests. The open-circuit fault test is relatively simple, requiring only the sending and receiving of high and low levels between two IO ports. The presence of a fault is determined by whether the reception meets expectations. The short-circuit fault is relatively complex, involving a short-circuit fault caused by the breakdown of the capacitor itself and a short-circuit fault between the coupling capacitor signals. Effective testing is required to achieve the best test coverage.

[0005] Therefore, in view of the above technical problems and defects, it is urgent to design and develop a capacitor open-short circuit test architecture, method and platform suitable for boundary scan. Summary of the Invention

[0006] To overcome the shortcomings and difficulties of the above-mentioned prior art, the purpose of the present invention is to provide a capacitor open-circuit and short-circuit test architecture, method and platform suitable for boundary scan. Regardless of whether the IEEE 1149.6 protocol is supported, the open-circuit and short-circuit test relationship of the coupling capacitor connection relationship can be measured through the IEEE 1149.1 protocol, thereby improving test coverage and reducing test design costs.

[0007] The first purpose of the present invention is to provide a capacitor open-short circuit test architecture suitable for boundary scanning; the second purpose of the present invention is to provide a capacitor open-short circuit test method suitable for boundary scanning; the third purpose of the present invention is to provide a capacitor open-short circuit test platform suitable for boundary scanning.

[0008] The first object of the present invention is achieved as follows: the architecture comprises: an analog test card unit, and a board under test unit and a boundary scan controller unit electrically connected to the analog test card unit;

[0009] The boundary scan controller unit is used to provide a clock driving signal TCK, a state driving signal TMS, a data driving signal TDI, a data receiving signal TDO and a driving signal DO3;

[0010] The TCK, TMS, and TDI pins of the boundary scan controller unit are respectively connected to the JTAG clock receiving TCK1, status receiving TMS1, and data receiving TDI1 pins of the first BS chip in the board under test unit; wherein the TCK and TMS pins of the boundary scan controller unit are also respectively connected to the JTAG clock receiving TCK2 and status receiving TMS2 of the second BS chip in the analog test card unit;

[0011] The data output TDO1 pin of the first BS chip in the board under test unit is connected to the data receiving TDI2 pin of the second BS chip in the analog test card unit; the data output pin TDO2 of the second BS chip in the analog test card unit is connected to the data receiving TDO pin of the boundary scan controller unit;

[0012] The DO3 terminal of the boundary scan controller unit is connected to the RD pins of the first D flip-flop and the second D flip-flop of the analog test card unit respectively.

[0013] Furthermore, the first point-110 terminal of the first BS chip in the board under test unit is connected to one end of the first capacitor; the other end of the first capacitor is sequentially connected to the first connector and the second gold finger in the analog test card unit; the first point-210 terminal of the first BS chip in the board under test unit is connected to one end of the second capacitor; the other end of the second capacitor is sequentially connected to the first connector and the second gold finger in the analog test card unit;

[0014] One side of the second golden finger is connected to the positive input terminal of the first operational amplifier and the positive input terminal of the second operational amplifier respectively; the output terminal of the first operational amplifier is connected to the positive input terminal of the first comparator; the output terminal of the second operational amplifier is connected to the positive input terminal of the second comparator;

[0015] The output end of the first comparator is connected to the CP pin of the first D flip-flop; the Q pin of the first D flip-flop is connected to the second point-1 IO end of the second BS chip; the output end of the second comparator is connected to the CP pin of the second D flip-flop; the Q pin of the second D flip-flop is connected to the second point-3 IO end of the second BS chip.

[0016] Furthermore, the negative input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor respectively; the other end of the second resistor is connected to the output terminal of the first operational amplifier, the positive input terminal of the first comparator, and one end of the sixth resistor respectively; the other end of the sixth resistor is connected to one end of the fifth resistor and the second point 2 IO terminal of the second BS chip respectively;

[0017] The other end of the first resistor and the other end of the fifth resistor are grounded together;

[0018] The negative input terminal of the second operational amplifier is connected to one end of the seventh resistor and one end of the eighth resistor respectively; the other end of the eighth resistor is connected to the output terminal of the second operational amplifier, the positive input terminal of the second comparator, and one end of the twelfth resistor respectively; the other end of the twelfth resistor is connected to one end of the eleventh resistor and the second point four IO terminal of the second BS chip respectively;

[0019] The other end of the seventh resistor and the other end of the eleventh resistor are commonly grounded.

[0020] Furthermore, the Q pin of the first D flip-flop is connected to one end of a thirteenth resistor; the other end of the thirteenth resistor is connected to the second point-IO terminal of the second BS chip and one end of a fourteenth resistor respectively;

[0021] The Q pin of the second D flip-flop is connected to one end of the fifteenth resistor; the other end of the fifteenth resistor is connected to the second point-IO terminal of the second BS chip and one end of the sixteenth resistor respectively;

[0022] The other end of the fourteenth resistor and the other end of the sixteenth resistor are commonly grounded.

[0023] Furthermore, the negative input terminal of the first comparator is connected to one end of the third resistor and one end of the fourth resistor respectively; the other end of the third resistor is connected to the power supply terminal, the first D flip-flop, the second D flip-flop, and one end of the ninth resistor respectively;

[0024] The negative input terminal of the second comparator is connected to the other end of the ninth resistor and one end of the tenth resistor respectively; the other end of the tenth resistor and the other end of the fourth resistor are grounded in common.

[0025] Furthermore, the models of the first operational amplifier and the second operational amplifier are AD8066.

[0026] Furthermore, the models of the first comparator and the second comparator are LM393; the models of the first D flip-flop and the second D flip-flop are 74LVC1G74.

[0027] Furthermore, the model of the second BS chip is 10M25DAF484I7G.

[0028] The second object of the present invention is achieved as follows: the method is applied to a capacitor open-short circuit test architecture suitable for boundary scan; the method comprises the following steps:

[0029] The DO3 output of the boundary scan controller unit is set to low level 0. Combined with the conditions and principles of the D flip-flop, the Q outputs of the first D flip-flop and the second D flip-flop are both low level 0. The first point 1 IO terminal and the first point 2 IO terminal of the first BS chip in the test board unit do not output. The second point 1 IO terminal and the second point 2 IO terminal of the second BS chip in the simulation test card unit only input and receive. If the second point 1 IO terminal and the second point 2 IO terminal of the second BS chip both receive low level 0, it indicates that the open circuit test of the path where the capacitor is located is fault-free. Otherwise, a fault is reported.

[0030] Control the JTAG combination chain of the board under test unit and the analog test card unit, so that the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip respectively output a high level 1, thereby causing the rising edge of CP of the first D flip-flop and the second D flip-flop to respectively arrive, and the output level Q of the first D flip-flop and the second D flip-flop is flipped from the original level 0 to the level 1;

[0031] Based on the previous step, the second IO terminal of the second BS chip and the second IO terminal of the second BS chip both receive a valid high level 1, indicating that the open circuit test of the capacitor path is fault-free, otherwise a fault is reported;

[0032] Control the JTAG combination chain of the test board unit and the simulation test card unit, and drive the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip to a high level 1 and maintain them respectively; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a high level, it indicates that there is no short circuit fault in the first capacitor and the second capacitor; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a low level, it indicates that there is a short circuit fault in the first capacitor and the second capacitor.

[0033] The third object of the present invention is achieved as follows: the platform includes a processor, a memory and a capacitor open-short circuit test platform control program suitable for boundary scanning; wherein, the capacitor open-short circuit test platform control program suitable for boundary scanning is executed by the processor, the capacitor open-short circuit test platform control program suitable for boundary scanning is stored in the memory, and the capacitor open-short circuit test platform control program suitable for boundary scanning implements the capacitor open-short circuit test method suitable for boundary scanning.

[0034] The present invention includes an analog test card unit through an architecture, and a board under test unit and a boundary scan controller unit electrically connected to the analog test card unit respectively; the boundary scan controller unit is used to provide a clock drive signal TCK, a state drive signal TMS, a data drive signal TDI, a data receiving signal TDO and a drive signal DO3; the TCK, TMS and TDI pins of the boundary scan controller unit are respectively connected to the JTAG clock receiving TCK1, state receiving TMS1 and data receiving TDI1 pins of the first BS chip in the board under test unit; wherein the TCK and TMS pins of the boundary scan controller unit are also respectively connected to the JTAG clock receiving TCK2 and state receiving TMS2 of the second BS chip in the analog test card unit; the data output TDO1 pin of the first BS chip in the board under test unit is connected to the data receiving TDI2 pin of the second BS chip in the analog test card unit, and the data output pin TDO2 of the second BS chip in the analog test card unit is connected to the data receiving TDO pin of the boundary scan controller unit; the DO3 end of the boundary scan controller unit is respectively connected to the RD pins of the first D flip-flop and the second D flip-flop of the analog test card unit. The method and platform corresponding to the architecture can achieve the purpose of open-circuit and short-circuit testability of coupling capacitor connection relationships through the IEEE 1149.1 protocol, regardless of whether the IEEE 1149.6 protocol is supported, thereby improving test coverage and reducing test design costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of LVDS signal output and capacitor output waveforms for a capacitor open / short circuit test using boundary scan according to the present invention;

[0037] Figure 2 A schematic diagram of a capacitor open-short circuit test architecture suitable for boundary scan in the present invention;

[0038] Figure 3 This is a flow chart of a capacitor open-short circuit test method suitable for boundary scan according to the present invention;

[0039] Figure 4 This is a structural schematic diagram of a capacitor open-short circuit test platform suitable for boundary scanning in the present invention;

[0040] In the figure: R1-first resistor; R2-second resistor; R3-third resistor; R4-fourth resistor; R5-fifth resistor; R6-sixth resistor; R7-seventh resistor; R8-eighth resistor; R9-ninth resistor; R10-tenth resistor; R11-eleventh resistor; R12-twelfth resistor; R13-thirteenth resistor; R14-fourteenth resistor; R15-fifteenth resistor; R16-sixteenth resistor; C1-first capacitor; C2-second capacitor; BS chip 1-first S chip; BS chip 2-second BS chip; IO1.1-first point one IO terminal; IO1.2-first point two IO terminal; IO2.1-second point one IO terminal; IO2.2-second point two IO terminal; IO2.3-second point three IO terminal; IO2.4-second point four IO terminal; D flip-flop 1-first D flip-flop; D flip-flop 2-second D flip-flop; op amp 1-first op amp; op amp 2-second op amp. DETAILED DESCRIPTION

[0041] In order to better understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below with reference to the accompanying drawings and specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0042] The present invention may also be implemented or applied through other different specific examples, and the details in this specification may also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0044] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. Secondly, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0045] Preferably, the present invention is a method for testing capacitor open and short circuits using boundary scanning, which is applied to one or more terminals or servers. The terminal is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc.

[0046] The terminal can be a computing device such as a desktop computer, notebook, PDA, cloud server, etc. The terminal can interact with the client through a keyboard, mouse, remote control, touchpad, or voice control device.

[0047] The present invention is to realize a capacitor open-short circuit test architecture, method and platform suitable for boundary scanning.

[0048] like Figure 3 , which is a flow chart of a capacitor open-short circuit test method applicable to boundary scan provided by an embodiment of the present invention.

[0049] In this embodiment, the capacitor open-short circuit test method suitable for boundary scanning can be applied to terminals with display functions or fixed terminals. The terminals are not limited to personal computers, smart phones, tablet computers, desktop computers or all-in-one computers equipped with cameras, etc.

[0050] The capacitor open / short circuit test method applicable to boundary scan can also be applied in a hardware environment consisting of a terminal and a server connected to the terminal via a network. The network includes, but is not limited to, a wide area network, a metropolitan area network, or a local area network. The capacitor open / short circuit test method applicable to boundary scan according to the embodiments of the present invention can be executed by a server, a terminal, or both.

[0051] For example, for the capacitor open and short circuit test terminal that needs to be applicable to boundary scan, the capacitor open and short circuit test function applicable to boundary scan provided by the method of the present invention can be directly integrated on the terminal, or the client for realizing the method of the present invention can be installed. For another example, the method provided by the present invention can also be run on devices such as servers in the form of a software development kit (Software Development Kit, SDK), and an interface for the capacitor open and short circuit test function applicable to boundary scan is provided in the form of SDK, and the terminal or other devices can realize the capacitor open and short circuit test function applicable to boundary scan through the interface provided. Below in conjunction with accompanying drawings, the present invention will be further elaborated.

[0052] The present invention will be described in further detail below with reference to the accompanying drawings. Figure 2 As shown, the present invention provides a capacitor open-short circuit test architecture suitable for boundary scan, the architecture comprising: an analog test card unit, and a board under test unit and a boundary scan controller unit electrically connected to the analog test card unit respectively;

[0053] The boundary scan controller unit is used to provide a clock driving signal TCK, a state driving signal TMS, a data driving signal TDI, a data receiving signal TDO and a driving signal DO3;

[0054] The TCK, TMS, and TDI pins of the boundary scan controller unit are respectively connected to the JTAG clock receiving TCK1, status receiving TMS1, and data receiving TDI1 pins of the first BS chip in the board under test unit; wherein the TCK and TMS pins of the boundary scan controller unit are also respectively connected to the JTAG clock receiving TCK2 and status receiving TMS2 of the second BS chip in the analog test card unit;

[0055] The data output TDO1 pin of the first BS chip in the board under test unit is connected to the data receiving TDI2 pin of the second BS chip in the analog test card unit; the data output pin TDO2 of the second BS chip in the analog test card unit is connected to the data receiving TDO pin of the boundary scan controller unit;

[0056] The DO3 terminal of the boundary scan controller unit is connected to the RD pins of the first D flip-flop and the second D flip-flop of the analog test card unit respectively.

[0057] The first point-110 terminal of the first BS chip in the board under test unit is connected to one end of the first capacitor; the other end of the first capacitor is sequentially connected to the first connector and the second gold finger in the analog test card unit; the first point-210 terminal of the first BS chip in the board under test unit is connected to one end of the second capacitor; the other end of the second capacitor is sequentially connected to the first connector and the second gold finger in the analog test card unit;

[0058] One side of the second golden finger is connected to the positive input terminal of the first operational amplifier and the positive input terminal of the second operational amplifier respectively; the output terminal of the first operational amplifier is connected to the positive input terminal of the first comparator; the output terminal of the second operational amplifier is connected to the positive input terminal of the second comparator;

[0059] The output end of the first comparator is connected to the CP pin of the first D flip-flop; the Q pin of the first D flip-flop is connected to the second point-1 IO end of the second BS chip; the output end of the second comparator is connected to the CP pin of the second D flip-flop; the Q pin of the second D flip-flop is connected to the second point-3 IO end of the second BS chip.

[0060] The negative input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor respectively; the other end of the second resistor is connected to the output terminal of the first operational amplifier, the positive input terminal of the first comparator, and one end of the sixth resistor respectively; the other end of the sixth resistor is connected to one end of the fifth resistor and the second point 2 IO terminal of the second BS chip respectively;

[0061] The other end of the first resistor and the other end of the fifth resistor are grounded together;

[0062] The negative input terminal of the second operational amplifier is connected to one end of the seventh resistor and one end of the eighth resistor respectively; the other end of the eighth resistor is connected to the output terminal of the second operational amplifier, the positive input terminal of the second comparator, and one end of the twelfth resistor respectively; the other end of the twelfth resistor is connected to one end of the eleventh resistor and the second point four IO terminal of the second BS chip respectively;

[0063] The other end of the seventh resistor and the other end of the eleventh resistor are commonly grounded.

[0064] The Q pin of the first D flip-flop is connected to one end of a thirteenth resistor; the other end of the thirteenth resistor is connected to the second point-IO terminal of the second BS chip and one end of a fourteenth resistor respectively;

[0065] The Q pin of the second D flip-flop is connected to one end of the fifteenth resistor; the other end of the fifteenth resistor is connected to the second point-IO terminal of the second BS chip and one end of the sixteenth resistor respectively;

[0066] The other end of the fourteenth resistor and the other end of the sixteenth resistor are commonly grounded.

[0067] The negative input terminal of the first comparator is connected to one end of the third resistor and one end of the fourth resistor respectively; the other end of the third resistor is connected to the power supply terminal, the first D flip-flop, the second D flip-flop, and one end of the ninth resistor respectively;

[0068] The negative input terminal of the second comparator is connected to the other end of the ninth resistor and one end of the tenth resistor respectively; the other end of the tenth resistor and the other end of the fourth resistor are grounded in common.

[0069] The models of the first operational amplifier and the second operational amplifier are AD8066.

[0070] The models of the first comparator and the second comparator are LM393; the models of the first D flip-flop and the second D flip-flop are 74LVC1G74.

[0071] The model of the second BS chip is 10M25DAF484I7G.

[0072] Specifically, in the embodiment of the present invention, Figure 1 As shown in FIG, a schematic diagram of the LVDS signal output and capacitor output waveforms according to an embodiment of the present invention is shown. Figure 1 , LVDS signal exists in the form of differential pair, the LVDS output signal is centered on the bias of 1.2V, the two square wave signals exist complementary, the highest amplitude is 1.375V, the lowest amplitude is 1.025V; after the LVDS signal passes through the coupling capacitor, the DC component is eliminated, and only the AC component can pass through the coupling capacitor. At this time, the amplitude of the LVDS signal is only 0.35V. The LVDS high-speed signal changes slowly in the boundary scan test, and the coupling capacitor output is usually Figure 1 The spike signal shown.

[0073] like Figure 2 As shown in FIG, a block diagram of a boundary scan capacitor open-short circuit test system according to an embodiment of the present invention is shown. The block diagram is mainly divided into three parts: the board under test (DUT), the analog test card (DUMMY card), and the boundary scan controller (BS controller).

[0074] Boundary scan controller, providing JTAG clock drive signal TCK, status drive signal TMS, data drive signal TDI, data receive signal TDO; also provides drive signal DO3 (DO output with strong drive capability);

[0075] The TCK, TMS, and TDI pins of the BS controller are respectively connected to the JTAG clock receiving TCK1, status receiving TMS1, and data receiving TDI1 pins of the DUT BS chip 1. The TCK and TMS pins of the BS controller are also respectively connected to the JTAG clock receiving TCK2 and status receiving TMS2 of the DUMMY card BS chip 2. The data output TDO1 pin of the BS chip 1 of the board under test (DUT) is connected to the data receiving TDI2 pin of the BS chip 2 of the DUMMY card. The data output pin TDO2 of the BS chip 2 of the DUMMY card is connected to the data receiving TDO pin of the BS controller, thereby realizing a JTAG combination chain from BS chip 1 to BS chip 2, also known as a daisy chain in the industry. The IO of BS chips 1 and 2 can be operated through the JTAG combination chain.

[0076] DO3 of the BS controller is connected to the RD pin of D flip-flop 1 and D flip-flop 2 of the DUMMY card;

[0077] The above is the connection between the BS chip and the DUT and DUMMY card. The connector is omitted in the figure.

[0078] IO1.1 and IO1.2 of DUT BS chip 1 are connected to one pin of capacitors C1 and C2 respectively, and the other pins of capacitors C1 and C2 are connected to pins a1.1 and a1.2 of connector 1 respectively. Connector 1 is the connector to be tested. Pins a1.1 and a1.2 of connector 1 are connected to pins a2.1 and a2.2 of gold finger 2 of DUMMY card respectively; pins a2.1 and a2.2 of gold finger 2 are connected to the positive input terminals of op amp 1 and op amp 2 respectively, and the negative input terminals of op amp 1 and op amp 2 are connected to one pin of resistors R1 and R7 respectively, and are connected to Connect to one pin of resistors R2 and R8, the other pins of R1 and R7 are connected to GND, the other pins of R2 and R8 are connected to the output of op amp 1 and op amp 2 respectively, the output of op amp 1 and op amp 2 are also connected to the positive input of comparator 1 and comparator 2 respectively, and are also connected to one pin of resistors R6 and R12 respectively, the other pins of R6 and R12 are connected to IO2.2 and IO2.4 of BS chip 2 respectively, IO2.2 and IO2.4 are also connected to one pin of resistors R5 and R11 respectively, and the other pins of R5 and R11 are both connected to GND;

[0079] The negative input terminals of comparator 1 and comparator 2 are connected to one pin of resistors R4 and R10 respectively, and to one pin of resistors R3 and R9 at the same time. The other pins of R4 and R10 are connected to GND, and the other pins of R3 and R9 are connected to a 5V power supply.

[0080] The 5V power supply is also connected to the D pin and SD pin of D flip-flop 1 and the D pin and SD pin of D flip-flop 2.

[0081] Figure 1The reference models of op amp 1 and op amp 2 are AD8066, and the reference models of comparator 1 and comparator 2 are LM393. The op amp is powered by a 5V single-ended power supply and supports 0 to 5V rail-to-rail output. The comparator is also powered by a 5V single power supply, so that the high level of comparator 1 and 2 outputs is 5V. In order to simplify the connection, Figure 1 The power supply of the operational amplifier and comparator is not drawn; the D flip-flops 1 and 2 are referenced by model 74LVC1G74; the output Q pin of the D flip-flop 1 and the output Q pin of the D flip-flop 2 are connected to one pin of the resistors R13 and R15, respectively, and the other pins of R13 and R15 are connected to IO2.1 and IO2.3 of the BS chip 2, respectively, and IO2.1 and IO2.3 are pulled down to GND through resistors R14 and R16, respectively; in the solution of the present invention, the model of the BS chip 1 of the board under test (DUT) is not fixed, such as the BMC chip commonly used in server-type boards, reference model: AST2600, and may also be other types of chips, such as CPU, FPGA, PCH, ARM and other chips that comply with the IEEE 1149 protocol. The present invention is a chip that complies with the protocol, and provides a unified solution when facing the same test problem.

[0082] The resistors R5 and R11 are both 2kΩ in reference. The resistors R5 and R11 are pulled down to GND to prevent the default weak pull-up high level of 3.3V of IO2.2 and IO2.4 of BS chip 2 (reference model 10M25DAF484I7G) from being connected to the positive input terminals of comparator 1 and comparator 2 through resistors R6 and R12 respectively, thereby causing the comparator to be falsely triggered and output a high level 1. This ensures that the positive input terminals of comparator 1 and comparator 2 are both low level 0, while maintaining IO2.2 and IO2.4 at the default low level 0.

[0083] The reference resistance of R3 and R9 is 10kΩ, and the reference resistance of R4 and R10 is 1kΩ. R3, R4, R9, and R10 divide the 5V power supply and provide 0.5V to the negative input of comparator 1 and comparator 2 respectively. This ensures that the 0V level of the positive input of comparator 1 and comparator 2 is slightly lower than the 0.5V level of the negative input, preventing GND noise from causing comparator 1 and comparator 2 to be falsely triggered to a high level 1, ensuring that the default output of comparator 1 and comparator 2 is a stable low level 0;

[0084] The default output of comparator 1 and comparator 2 is a stable low level 0, which is provided to the CP pin of the D flip-flop respectively to prepare for the level flip when the rising edge comes;

[0085] The working principles of D flip-flop 1 and D flip-flop 2 in the system of the present invention are as follows:

[0086] The D pin and SD pin of D flip-flop 1 and D flip-flop 2 are both connected to 5V and fixed at high level 1;

[0087] The RD pins of D flip-flops 1 and 2 are both connected to DO3 of the BS controller. When DO3 of the BS controller outputs a low level 0, the SD and RD pins of D flip-flops 1 and 2 are both high level 1 and low level 0, respectively. According to the data sheet of the 74LVC1G74 D flip-flop, the Q pins of D flip-flops 1 and 2 both output a low level 0. At this time, IO2.1 and IO2.3 of BS chip 2 both receive a low level 0.

[0088] When DO3 of the BS controller outputs a high level 1, the SD and RD of D flip-flops 1 and 2 are both high level 1. Looking up the data sheet of the D flip-flop 74LVC1G74 shows that when the rising edge of the CP pin arrives, the output level of the Q pin of D flip-flops 1 and 2 will be output according to the level of the D pin;

[0089] When IO1.1 and IO1.2 of BS chip 1 output high level 1 respectively, after being amplified by op amp 1 and op amp 2, and then converted to 5V high level by the comparator, the CP of D flip-flop 1 and D flip-flop 2 respectively changes from low level 0 to high level 1, that is, the CP rising edge arrives, and IO2.1 and IO2.3 of BS chip 2 will receive valid high level 1 respectively;

[0090] The reference resistance of R1 and R7 is 1kΩ, and the reference resistance of R2 and R8 is 2kΩ. Their function is to amplify the output of op amp 1 and op amp 2, and amplify the signal of the coupling capacitor to 3 times;

[0091] The purpose of amplifying 3 times is to be compatible with the test of capacitor open and short circuit faults.

[0092] First, an open-circuit test is performed on the path where the capacitor is located. The output signal amplitude of the coupling capacitor of the LVDS signal is only 0.35V, and the capacitor is a sharp pulse signal. The amplitude of the DC-blocked signal of capacitors 1 and 2 is amplified by 3 times through op amp 1 and op amp 2 respectively, and the DC-blocked signal amplitude is amplified to 1.05V. The output of op amp 1 and 2 is respectively passed through comparators 1 and 2 for comparison. The high-level 1.05V is converted to a fixed high-level output of 5V, which is stably provided to the CP pins of D-type flip-flops 1 and 2 for triggering.

[0093] Step 1: Set the DO3 output of the BS controller to low level 0. According to the above conditions and principles of the D flip-flop, the Q outputs of D flip-flops 1 and 2 are both low level 0. IO1.1 and IO1.2 of BS chip 1 of the DUT do not output. IO2.1 and IO2.2 of BS chip 2 of the DUMMY card only input and receive. IO2.1 and IO2.2 of BS chip 2 both receive low level 0, indicating that the open circuit test of the path where the capacitor is located is fault-free. Otherwise, a fault is reported.

[0094] Step 2: Control the JTAG combination chain of the DUT and DUMMY cards to make IO1.1 and IO1.2 of BS chip 1 output high level 1 respectively, so that the rising edge of CP of D flip-flops 1 and 2 comes respectively, and the output level Q of D flip-flops 1 and 2 is flipped from the original level 0 to level 1;

[0095] To supplement step 2, if IO1.1 and IO1.2 are a set of LVDS signals, and IO1.1 needs to output 0 and 1 respectively to achieve the test purpose, IO1.2 will output 1 and 0 respectively, following the opposite output of IO1.1. This will cause the CP of D flip-flops 1 and 2 to have rising edges, achieving the purpose of measuring the DUT connection relationship where capacitors C1 and C2 are located.

[0096] Step 3: Based on step 2, both IO2.1 and IO2.3 of BS chip 2 receive a valid high level 1, indicating that the open circuit test of the capacitor path is normal. Otherwise, a fault is reported.

[0097] Supplement step 3. Resistors R13 and R14, as well as resistors R15 and R16, divide the 5V high voltage level of the output Q of D flip-flop 1 and D flip-flop 2, respectively. If resistors R14 and R16 are 2kΩ, then resistors R13 and R15 are 1kΩ, respectively. This allows IO2.1 and IO2.3 of BS chip 2 on the DUMMY card to receive a high voltage level of 3.3V, avoiding the risk of BS chip 2's IO directly receiving a high voltage level of 5V.

[0098] The high levels of the outputs of comparators 1 and 2 and the input and output of the D flip-flop are all 5V. The high levels of DO3 of the BS controller and IO2.1 and IO2.2 of BS chip 2 of the DUMMY card are all 3.3V. The outputs of IO1.1 and IO1.2 of BS chip 1 are standard LVDS signals.

[0099] The above three steps test the open circuit fault of the capacitor path. If only this type of test is performed, the short circuit fault of the capacitor itself cannot be accurately detected. Therefore, the short circuit fault test of the capacitor itself needs to be considered. The test method is as follows:

[0100] Both op amp 1 and op amp 2 have a 3x amplification function, and the maximum LVDS output is 1.375V. When a short circuit fault occurs on capacitor C1 or C2, there is no coupling capacitor to block the DC component, driving IO1.1 and IO1.2 of DUT BS chip 1 to output high and maintain it. At this time, the output level of op amp 1 or op amp 2 is 4.125V.

[0101] The voltage of 4.125V is too high for the IO of BS chip 2 of the DUMMY card. The voltage is divided by R6 and R5 as well as R12 and R11. It is known that R5 and R11 are referenced to 2kΩ, and R6 and R11 are referenced to 500Ω, so that IO2.2 and IO2.4 of the DUMMY card receive a high level of 3.3V respectively.

[0102] Step 4: Control the JTAG combination chain of the DUT and DUMMY card to drive IO1.1 and IO1.2 of the DUT BS chip 1 to high level 1 and maintain it;

[0103] Step 5: If IO2.2 and IO2.4 of the DUMMY card BS chip receive a high level, it indicates that capacitors C1 and C2 are not short-circuited. If IO2.2 or IO2.4 of the DUMMY card BS chip receive a low level, it indicates that capacitors C1 or C2 are short-circuited.

[0104] To supplement steps 4 and 5, it is very important that the high level output by IO1.1 and IO1.2 of BS chip 1 of DUT can be maintained only when the capacitor is short-circuited, so that it can be effectively received by IO2.2 or IO2.4. When capacitor C1 or C2 is not short-circuited, IO2.2 or IO2.4 cannot receive the high level.

[0105] Supplementary step 4: If IO1.1 and IO1.2 of the DUT are a set of LVDS signals, in order to achieve the test purpose, IO1.1 needs to output 0 and 1 respectively. Then IO1.2 will follow IO1.1 and output 1 and 0 in the opposite direction. This will control IO1.1 and IO1.2 to output high level 1 respectively, and IO2.2 or IO2.4 will effectively receive the corresponding high level 1, so that the short circuit of capacitors C1 and C2 can be measured.

[0106] The above tests are not yet complete. In order to achieve the best test coverage, the short circuit fault problem between the connection between capacitors C1 and C2 in the DUT is tested as follows:

[0107] IO1.1 and IO1.2 usually have sending and receiving functions. They are defined as INOUT type IO in BSDL and can send and receive levels 0 and 1 by themselves.

[0108] In step 6, IO1.1 and IO1.2 are associated for short-circuit fault testing to achieve the purpose of short-circuit fault testing between the connection relationship of capacitors C1 and C2. When there are more capacitors for associated short-circuit fault testing, the method is the same. Refer to the short-circuit fault algorithm provided by patent number: CN119291484A, which will not be elaborated here.

[0109] Op amp 1 and Op amp 2 use op amps with high slew rate and bandwidth to fully restore and amplify the coupling capacitor signal. They are powered by a single 5V power supply to meet the power supply requirements. The maximum output of op amp 1 and op amp 2 is also limited to no more than 5V.

[0110] The IO1.1 and IO1.2 of the BS chip 1 of the DUT of the present invention are connected to one pin of capacitors C1 and C2 respectively, and the other pins of capacitors C1 and C2 are connected to pins a1.1 and a1.2 of connector 1 respectively. The connection relationship test of a set of differential pairs IO1.1 and IO1.2 connected to capacitors C1 and C2 respectively is described in detail. The number of differential pairs and capacitors tested in practice may be large, and the method can be expanded and implemented according to the present invention;

[0111] The method and system for capacitor open-circuit and short-circuit testing of the present invention are also applicable to boundary scan testing of non-standard LVDS signals. The purpose of testing can be achieved by simply changing the resistance parameters, and the same applies to the method.

[0112] To achieve the above object, the present invention also provides a capacitor open-short circuit test method suitable for boundary scan, such as Figure 3 As shown, the method is applied to a capacitor open-short circuit test architecture suitable for boundary scan; the method comprises the following steps:

[0113] The DO3 output of the boundary scan controller unit is set to low level 0. Combined with the conditions and principles of the D flip-flop, the Q outputs of the first D flip-flop and the second D flip-flop are both low level 0. The first point 1 IO terminal and the first point 2 IO terminal of the first BS chip in the test board unit do not output. The second point 1 IO terminal and the second point 2 IO terminal of the second BS chip in the simulation test card unit only input and receive. If the second point 1 IO terminal and the second point 2 IO terminal of the second BS chip both receive low level 0, it indicates that the open circuit test of the path where the capacitor is located is fault-free. Otherwise, a fault is reported.

[0114] Control the JTAG combination chain of the board under test unit and the analog test card unit, so that the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip respectively output a high level 1, thereby causing the rising edge of CP of the first D flip-flop and the second D flip-flop to respectively arrive, and the output level Q of the first D flip-flop and the second D flip-flop is flipped from the original level 0 to the level 1;

[0115] Based on the previous step, the second IO terminal of the second BS chip and the second IO terminal of the second BS chip both receive a valid high level 1, indicating that the open circuit test of the capacitor path is fault-free, otherwise a fault is reported;

[0116] Control the JTAG combination chain of the test board unit and the simulation test card unit, and drive the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip to a high level 1 and maintain them respectively; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a high level, it indicates that there is no short circuit fault in the first capacitor and the second capacitor; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a low level, it indicates that there is a short circuit fault in the first capacitor and the second capacitor.

[0117] In the embodiment of the method of the present invention, the test architecture involved in the capacitor open-short circuit test applicable to boundary scan has been described above in detail and will not be repeated here.

[0118] To achieve the above object, the present invention also provides a capacitor open and short circuit test platform suitable for boundary scanning, such as Figure 4 As shown, it includes a processor, a memory, and a capacitor open-short circuit test platform control program suitable for boundary scan; wherein, the processor executes the capacitor open-short circuit test platform control program suitable for boundary scan, the capacitor open-short circuit test platform control program suitable for boundary scan is stored in the memory, and the capacitor open-short circuit test platform control program suitable for boundary scan implements the capacitor open-short circuit test method steps suitable for boundary scan. For example:

[0119] S01. The DO3 output of the boundary scan controller unit is set to a low level 0. Based on the conditions and principles of the D flip-flop, the Q outputs of the first D flip-flop and the second D flip-flop are both low level 0. The first point 1 IO terminal and the first point 2 IO terminal of the first BS chip in the test board unit do not output. The second point 1 IO terminal and the second point 2 IO terminal of the second BS chip in the simulation test card unit only input and receive. If the second point 1 IO terminal and the second point 2 IO terminal of the second BS chip both receive a low level 0, it indicates that the open circuit test of the capacitor path is normal. Otherwise, a fault is reported.

[0120] S02, controlling the JTAG combination chain of the board under test unit and the analog test card unit, respectively causing the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip to output a high level 1, thereby causing the rising edge of CP of the first D flip-flop and the second D flip-flop to respectively arrive, and the output level Q of the first D flip-flop and the second D flip-flop to flip from the original level 0 to the level 1;

[0121] S03. Based on the previous step S02, the second 1st IO terminal and the second 3rd IO terminal of the second BS chip both receive a valid high level 1, indicating that the open circuit test of the path where the capacitor is located is fault-free, otherwise a fault is reported;

[0122] S04. Control the JTAG combination chain of the board unit to be tested and the simulation test card unit, and respectively drive the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip to a high level 1 and maintain it; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a high level, it indicates that there is no short circuit fault in the first capacitor and the second capacitor; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a low level, it indicates that there is a short circuit fault in the first capacitor and the second capacitor.

[0123] The specific details of the steps have been explained above and will not be repeated here.

[0124] In an embodiment of the present invention, the built-in processor of the capacitor open-short circuit test platform suitable for boundary scanning can be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of integrated circuits with the same or different functions, including a combination of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor uses various interfaces and lines to connect various components, and executes or executes programs or units stored in the memory, as well as calls data stored in the memory, to perform various functions and process data suitable for boundary scanning capacitor open-short circuit testing.

[0125] The memory is used to store program codes and various data. It is installed in a capacitor open and short circuit test platform suitable for boundary scan and can automatically access programs or data at high speed during operation.

[0126] The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electronically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0127] The present invention includes an analog test card unit through an architecture, and a board under test unit and a boundary scan controller unit electrically connected to the analog test card unit respectively; the boundary scan controller unit is used to provide a clock drive signal TCK, a state drive signal TMS, a data drive signal TDI, a data receiving signal TDO and a drive signal DO3; the TCK, TMS and TDI pins of the boundary scan controller unit are respectively connected to the JTAG clock receiving TCK1, state receiving TMS1 and data receiving TDI1 pins of the first BS chip in the board under test unit; wherein the TCK and TMS pins of the boundary scan controller unit are also respectively connected to the JTAG clock receiving TCK2 and state receiving TMS2 of the second BS chip in the analog test card unit; the data output TDO1 pin of the first BS chip in the board under test unit is connected to the data receiving TDI2 pin of the second BS chip in the analog test card unit, and the data output pin TDO2 of the second BS chip in the analog test card unit is connected to the data receiving TDO pin of the boundary scan controller unit; the DO3 end of the boundary scan controller unit is respectively connected to the RD pins of the first D flip-flop and the second D flip-flop of the analog test card unit. The method and platform corresponding to the architecture can achieve the purpose of open-circuit and short-circuit testability of coupling capacitor connection relationships through the IEEE 1149.1 protocol, regardless of whether the IEEE 1149.6 protocol is supported, thereby improving test coverage and reducing test design costs.

[0128] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A capacitor open-short circuit test architecture suitable for boundary scan, characterized in that: The architecture includes: an analog test card unit, and a board under test unit and a boundary scan controller unit electrically connected to the analog test card unit respectively; The boundary scan controller unit is used to provide a clock driving signal TCK, a state driving signal TMS, a data driving signal TDI, a data receiving signal TDO and a driving signal DO3; The TCK, TMS, and TDI pins of the boundary scan controller unit are respectively connected to the JTAG clock receiving TCK1, status receiving TMS1, and data receiving TDI1 pins of the first BS chip in the board under test unit; wherein the TCK and TMS pins of the boundary scan controller unit are also respectively connected to the JTAG clock receiving TCK2 and status receiving TMS2 of the second BS chip in the analog test card unit; The data output TDO1 pin of the first BS chip in the board under test unit is connected to the data receiving TDI2 pin of the second BS chip in the analog test card unit; the data output pin TDO2 of the second BS chip in the analog test card unit is connected to the data receiving TDO pin of the boundary scan controller unit; The DO3 terminal of the boundary scan controller unit is connected to the RD pins of the first D flip-flop and the second D flip-flop of the analog test card unit respectively.

2. A capacitor open-short circuit test architecture suitable for boundary scan according to claim 1, characterized in that: The first point-110 terminal of the first BS chip in the board under test unit is connected to one end of the first capacitor; the other end of the first capacitor is sequentially connected to the first connector and the second gold finger in the analog test card unit; the first point-210 terminal of the first BS chip in the board under test unit is connected to one end of the second capacitor; the other end of the second capacitor is sequentially connected to the first connector and the second gold finger in the analog test card unit; One side of the second golden finger is connected to the positive input terminal of the first operational amplifier and the positive input terminal of the second operational amplifier respectively; the output terminal of the first operational amplifier is connected to the positive input terminal of the first comparator; the output terminal of the second operational amplifier is connected to the positive input terminal of the second comparator; The output end of the first comparator is connected to the CP pin of the first D flip-flop; the Q pin of the first D flip-flop is connected to the second point-1 IO end of the second BS chip; the output end of the second comparator is connected to the CP pin of the second D flip-flop; the Q pin of the second D flip-flop is connected to the second point-3 IO end of the second BS chip.

3. The capacitor open-short circuit test architecture suitable for boundary scan according to claim 2, characterized in that: The negative input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor respectively; the other end of the second resistor is connected to the output terminal of the first operational amplifier, the positive input terminal of the first comparator, and one end of the sixth resistor respectively; the other end of the sixth resistor is connected to one end of the fifth resistor and the second point 2 IO terminal of the second BS chip respectively; The other end of the first resistor and the other end of the fifth resistor are grounded together; The negative input terminal of the second operational amplifier is connected to one end of the seventh resistor and one end of the eighth resistor respectively; the other end of the eighth resistor is connected to the output terminal of the second operational amplifier, the positive input terminal of the second comparator, and one end of the twelfth resistor respectively; the other end of the twelfth resistor is connected to one end of the eleventh resistor and the second point four IO terminal of the second BS chip respectively; The other end of the seventh resistor and the other end of the eleventh resistor are commonly grounded.

4. The capacitor open-short circuit test architecture suitable for boundary scan according to claim 2, characterized in that: The Q pin of the first D flip-flop is connected to one end of a thirteenth resistor; the other end of the thirteenth resistor is connected to the second point-IO terminal of the second BS chip and one end of a fourteenth resistor respectively; The Q pin of the second D flip-flop is connected to one end of the fifteenth resistor; the other end of the fifteenth resistor is connected to the second point-IO terminal of the second BS chip and one end of the sixteenth resistor respectively; The other end of the fourteenth resistor and the other end of the sixteenth resistor are commonly grounded.

5. A capacitor open-short circuit test architecture suitable for boundary scan according to claim 2 or 3, characterized in that: The negative input terminal of the first comparator is connected to one end of the third resistor and one end of the fourth resistor respectively; the other end of the third resistor is connected to the power supply terminal, the first D flip-flop, the second D flip-flop, and one end of the ninth resistor respectively; The negative input terminal of the second comparator is connected to the other end of the ninth resistor and one end of the tenth resistor respectively; the other end of the tenth resistor and the other end of the fourth resistor are grounded in common.

6. A capacitor open-short circuit test architecture suitable for boundary scan according to claim 2 or 3, characterized in that: The models of the first operational amplifier and the second operational amplifier are AD8066.

7. The capacitor open-short circuit test architecture suitable for boundary scan according to claim 5, characterized in that: The first comparator and the second comparator are of LM393 type; Models of the first D flip-flop and the second D flip-flop are 74LVC1G74.

8. A capacitor open-short circuit test architecture suitable for boundary scan according to claim 1, 2, 3 or 4, characterized in that: The model of the second BS chip is 10M25DAF484I7G.

9. A capacitor open-short circuit test method suitable for boundary scan, characterized in that: The method is applied to a capacitor open-short circuit test architecture suitable for boundary scan according to any one of claims 1 to 8; the method comprises the following steps: The DO3 output of the boundary scan controller unit is set to low level 0. Combined with the conditions and principles of the D flip-flop, the Q outputs of the first D flip-flop and the second D flip-flop are both low level 0. The first point 1 IO terminal and the first point 2 IO terminal of the first BS chip in the test board unit do not output. The second point 1 IO terminal and the second point 2 IO terminal of the second BS chip in the simulation test card unit only input and receive. If the second point 1 IO terminal and the second point 2 IO terminal of the second BS chip both receive low level 0, it indicates that the open circuit test of the path where the capacitor is located is fault-free. Otherwise, a fault is reported. Control the JTAG combination chain of the board under test unit and the analog test card unit, so that the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip respectively output a high level 1, thereby causing the rising edge of CP of the first D flip-flop and the second D flip-flop to respectively arrive, and the output level Q of the first D flip-flop and the second D flip-flop is flipped from the original level 0 to the level 1; Based on the previous step, the second IO terminal of the second BS chip and the second IO terminal of the second BS chip both receive a valid high level 1, indicating that the open circuit test of the capacitor path is fault-free, otherwise a fault is reported; Control the JTAG combination chain of the test board unit and the simulation test card unit, and drive the first point 1 IO terminal and the first point 2 IO terminal of the first BS chip to a high level 1 and maintain them respectively; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a high level, it indicates that there is no short circuit fault in the first capacitor and the second capacitor; if the second point 2 IO terminal and the second point 4 IO terminal of the second BS chip of the simulation test card unit respectively receive a low level, it indicates that there is a short circuit fault in the first capacitor and the second capacitor.

10. A capacitance open and short circuit test platform suitable for boundary scanning, characterized in that: The invention comprises a processor, a memory and a capacitor open-short circuit test platform control program suitable for boundary scanning; wherein, the capacitor open-short circuit test platform control program suitable for boundary scanning is executed by the processor, the capacitor open-short circuit test platform control program suitable for boundary scanning is stored in the memory, and the capacitor open-short circuit test platform control program suitable for boundary scanning implements the capacitor open-short circuit test method suitable for boundary scanning as claimed in claim 9.

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