A storage device and a processing method thereof, a centralized storage system, and an electronic device

Abstract

The application discloses a storage device and a processing method thereof, a centralized storage system and electronic equipment, and relates to the technical field of storage, and comprises a fibre channel card, a chip and at least two storage controllers; the chip comprises at least two fibre channel ports and at least two peripheral component interconnect (PCI) ports; the fibre channel card is connected with each fibre channel port respectively; each fibre channel port virtually has at least two virtual fibre channel ports; the virtual fibre channel ports of each fibre channel port correspond to the PCI ports one by one; and each PCI port is connected with the corresponding virtual fibre channel port and the storage controller respectively. In the storage device, the at least two storage controllers can share the fibre channel card, hardware-level virtualization is realized through the chip, and at least the problems of high cost and low resource utilization caused by the fact that the front-end interfaces of the multi-controller storage cannot be shared in the prior art are solved, multi-control resource sharing is realized, and the resource utilization is improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a storage device and its processing method, a centralized storage system, and an electronic device. Background Technology

[0002] In storage systems, multi-controller architectures aim to improve system performance, reliability, and scalability by introducing multiple controllers. However, the inability to share front-end interfaces among multiple controllers is a significant issue. Each controller typically has an independent front-end interface that connects to external devices such as servers and hosts, handling data input and output. For a four-controller storage system, each controller needs a Fibre Channel (FC) card, requiring four FC cards to meet the redundancy requirements of four controllers. This approach is costly, has low resource utilization, and can lead to significant waste of hardware resources.

[0003] Therefore, how to solve the above-mentioned problems caused by the inability to share the storage front-end interfaces of multiple controllers is a technical problem that urgently needs to be solved by those in the field. Summary of the Invention

[0004] This invention provides a storage device and its processing method, a centralized storage system, and an electronic device, which can at least solve the problems of high cost and low resource utilization caused by the inability to share the storage front-end interfaces of multiple controllers in related technologies, realize multi-controller resource sharing, and improve resource utilization.

[0005] This invention provides a storage device, comprising: a Fibre Channel card, a chip, and at least two storage controllers;

[0006] The chip includes at least two Fibre Channel ports and at least two peripheral component interconnect bus ports;

[0007] The fiber channel card is connected to each of the fiber channel ports respectively;

[0008] Each of the aforementioned Fibre Channel ports has at least two virtual Fibre Channel ports; each of the aforementioned virtual Fibre Channel ports corresponds one-to-one with the peripheral component interconnect bus port.

[0009] Each of the peripheral component interconnect bus ports is connected to the corresponding virtual Fibre Channel port and the storage controller.

[0010] The present invention also provides a method for processing a storage device, the storage device comprising a Fibre Channel card, a chip, and at least two storage controllers; the chip comprising at least two Fibre Channel ports and at least two peripheral component interconnect bus ports; the processing method comprising:

[0011] Connect the fiber channel card to each of the fiber channel ports respectively;

[0012] At least two virtual Fibre Channel ports are created on each of the aforementioned Fibre Channel ports; each of the virtual Fibre Channel ports created on each of the aforementioned Fibre Channel ports corresponds one-to-one with the peripheral component interconnect bus port.

[0013] The virtual fiber channel ports are sequentially connected to the corresponding peripheral component interconnect bus ports.

[0014] Connect the interconnect bus ports of each peripheral component to the corresponding storage controller.

[0015] The present invention also provides a centralized storage system, including a server and a storage device as described above; wherein the Fibre Channel card of the storage device is installed on the server.

[0016] The present invention also provides an electronic device, including a computer program stored in the electronic device described above, wherein the computer program, when executed by a processor, implements the centralized storage system described above.

[0017] The storage device provided by this invention connects Fibre Channel cards to each physical Fibre Channel port in the chip. Each physical Fibre Channel port in the chip virtualizes at least two virtual Fibre Channel ports, allowing a single physical port to be shared by multiple storage controllers. Compared to the traditional multi-controller architecture where each controller has its own independent physical port, this significantly reduces the number of Fibre Channel cards and achieves efficient reuse of hardware resources. Furthermore, each virtual Fibre Channel port virtualized by each physical Fibre Channel port corresponds one-to-one with a peripheral component interconnect bus port, and each peripheral component interconnect bus port connects both the virtual Fibre Channel port and the storage controller. This avoids designing dedicated interface circuits for different controllers, further reducing the hardware complexity and cost of the chip and motherboard. When additional controllers or front-end devices are needed, only the number or mapping relationship of virtual ports needs to be adjusted via software, without the need for additional physical port hardware, further reducing expansion costs. Therefore, at least two storage controllers in this storage device can share a Fibre Channel card. By implementing hardware-level virtualization through the chip, this invention can at least solve the problems of high cost and low resource utilization caused by the inability to share storage front-end interfaces among multiple controllers in related technologies. It achieves multi-controller resource sharing, improves resource utilization, and significantly enhances the performance and availability of the storage system.

[0018] In addition, the present invention also provides a corresponding storage device processing method, centralized storage system and electronic device, which have the same or corresponding technical features as the storage devices mentioned above, and have the same effects. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present invention;

[0021] Figure 2 This is one of the specific structural schematic diagrams of the storage device provided in the embodiments of the present invention;

[0022] Figure 3 This is the second schematic diagram of the specific structure of the storage device provided in the embodiment of the present invention;

[0023] Figure 4 A flowchart illustrating the processing method of a storage device provided in an embodiment of the present invention. Detailed Implementation

[0024] Fibre Channel (FC) is a data transmission technology designed specifically for high-performance storage networks. Its core objective is to meet the high reliability requirements of mission-critical applications through high bandwidth, low latency, and lossless transmission. FC is based on a layered protocol architecture (FC-0 to FC-4). The physical layer supports both fiber optic and copper cables, with fiber optics becoming the mainstream choice due to its advantages in interference resistance and long-distance transmission. The logical layer ensures efficient and reliable data transmission through flow control, frame sequence management, and Quality of Service (QoS) mechanisms. The topology has evolved from early point-to-point, shared-bandwidth arbitration rings to switched fabrics, supporting full-duplex communication and multi-device expansion, becoming the cornerstone of Storage Area Networks (SANs). FC can interact with storage devices using either the Small Computer System Interface (SCSI) protocol or the Non-Volatile Memory Express (NVMe) protocol.

[0025] Fibre Channel (FC) can dominate core storage architectures in industries such as finance, healthcare, and telecommunications, supporting highly sensitive businesses such as databases and real-time transaction systems. Its microsecond-level latency and redundancy design ensure zero data loss and high availability for critical data. In recent years, FC has further penetrated cloud computing and hyperconverged environments, adapting to hybrid cloud and cloud-native scenarios by supporting virtual machine hot migration and containerized storage interfaces. However, FC also faces competitive pressure from Ethernet technology: on the one hand, Fibre Channel over Ethernet (FCoE) attempts to reduce deployment costs through converged networks, but has failed to achieve widespread adoption due to performance degradation and management complexity; on the other hand, NVMe protocol and Remote Direct Memory Access (RDMA) technology, which transmit via Transmission Control Protocol / Internet Protocol (TCP / IP), are impacting the low-to-mid-range storage market with their Ethernet ecosystem and cost advantages. Nevertheless, FC has consolidated its position in the high-end market through continuous technological iterations, such as introducing Pulse Amplitude Modulation with 4 levels (PAM4) to improve bandwidth efficiency, hardware-level encrypted Fibre Channel-Signaling Protocol-2 (FC-SP-2) to enhance security, and intelligent management tools to achieve fault self-healing.

[0026] In centralized storage systems, the traditional architecture of connecting server nodes to SAN storage arrays via FC host bus adapter (HBA) cards faces several challenges: low resource utilization: Each node's FC card in a centralized storage system can achieve a peak bandwidth of 256Gbps (64Gbps for 4 ports). Assuming 10 million IOPS for 4 controllers (8K 7:3 model) and 250,000 IOPS per controller (Input / Output Operations Per Second), the actual maximum unidirectional bandwidth is only 250,000 * 8,000 * 8 * 0.7 = 11.2Gbps, resulting in an actual load of only 4.4%, leading to a significant waste of hardware resources. Furthermore, a four-controller storage system requires one FC card per controller (a total of four FC cards) to meet the redundancy requirements of the four controllers, which is costly. Using two shared FC cards can meet the redundancy requirements. To address these technical problems, this invention provides a storage device.

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0028] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0029] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] The specific application environment architecture or specific hardware architecture on which the execution of the storage device depends is described herein.

[0031] Embodiments of the present invention provide a storage device, and the method is described in detail in conjunction with the execution flow of the storage device. Figure 1 This is a schematic diagram of the structure of the storage device provided in an embodiment of the present invention, such as... Figure 1 As shown, the device includes: a Fibre Channel card 10, a chip 20, and at least two storage controllers 30;

[0032] Chip 20 includes at least two Fibre Channel ports (FC Port) and at least two peripheral component interconnect bus ports;

[0033] Fibre Channel card 10 is connected to each Fibre Channel port;

[0034] Each Fibre Channel port has at least two virtual Fibre Channel ports; each virtual Fibre Channel port corresponds one-to-one with a peripheral component interconnect bus port.

[0035] Each peripheral component interconnect bus port is connected to the corresponding virtual Fibre Channel port and storage controller 30.

[0036] In the storage device provided in this embodiment of the invention, the Fibre Channel card is connected to each physical Fibre Channel port in the chip. Each physical Fibre Channel port in the chip virtualizes at least two virtual Fibre Channel ports, allowing a single physical port to be shared by multiple storage controllers. Compared to the traditional multi-controller architecture where each controller exclusively occupies an independent physical port, this significantly reduces the number of Fibre Channel cards and achieves efficient reuse of hardware resources. Furthermore, each virtual Fibre Channel port virtualized by each physical Fibre Channel port corresponds one-to-one with a peripheral component interconnect bus port, and each peripheral component interconnect bus port simultaneously connects to both the virtual Fibre Channel port and the storage controller. This avoids designing dedicated interface circuits for different controllers, further reducing the hardware complexity and cost of the chip and motherboard. When additional controllers or front-end devices are needed, only the number or mapping relationship of virtual ports needs to be adjusted via software, without the need for additional physical port hardware, further reducing expansion costs. Therefore, in this storage device, at least two storage controllers can share the Fibre Channel card. By implementing hardware-level virtualization through the chip, this can at least solve the problems of high cost and low resource utilization caused by the inability to share storage front-end interfaces among multiple controllers in related technologies. This achieves multi-controller resource sharing, improves resource utilization, and significantly enhances the performance and availability of the storage system.

[0037] It should be noted that the storage device provided by this invention is suitable for multi-controller centralized storage. The number of storage controllers can be two, four, or other numbers, and is not limited herein.

[0038] Figure 2 This is one of the schematic diagrams illustrating the specific structure of a storage device provided in an embodiment of the present invention. For example... Figure 2 As shown, when there are four storage controllers, there is one Fibre Channel card. The chip can contain four Fibre Channel ports (P1, P2, P3 and P4) and four peripheral component interconnect bus ports (E1, E2, E3 and E4). The Fibre Channel card can be connected to each Fibre Channel port through a Small Form-factor Pluggable (SFP) optical module. Each Fibre Channel port can virtualize four virtual Fibre Channel ports.

[0039] like Figure 2 As shown, Fibre Channel port P1 can virtualize four virtual Fibre Channel ports (P1V1, P1V2, P1V3, and P1V4). It can be deduced that Fibre Channel port P2 can virtualize four virtual Fibre Channel ports (P2V1, P2V2, P2V3, and P2V4), Fibre Channel port P3 can virtualize four virtual Fibre Channel ports (P3V1, P3V2, P3V3, and P3V4), and Fibre Channel port P4 can virtualize four virtual Fibre Channel ports (P4V1, P4V2, P4V3, and P4V4).

[0040] Figure 3 This is one of the specific structural schematic diagrams of the storage device provided in the embodiments of the present invention. Figure 3 The diagram shows that virtual Fibre Channel ports P1V1, P2V1, P3V1, and P4V1 can all be connected to peripheral component interconnect bus port E1. It can be inferred that virtual Fibre Channel ports P1V2, P2V2, P3V2, and P4V2 are all connected to peripheral component interconnect bus port E2. Virtual Fibre Channel ports P1V3, P2V3, P3V3, and P4V3 are all connected to peripheral component interconnect bus port E3. Virtual Fibre Channel ports P1V4, P2V4, P3V4, and P4V4 are all connected to peripheral component interconnect bus port E4.

[0041] As described above, all Fibre Channel ports can be used to create sixteen virtual Fibre Channel ports. Each virtual Fibre Channel port can be connected to a Peripheral Component Interconnect (PCI) bus port. In other words, for each Fibre Channel port, one virtual Fibre Channel port can be bound to one PCI bus port. Thus, each PCI bus port can connect to a total of four virtual Fibre Channel ports at one end and a control memory at the other end.

[0042] Similarly, when there are two storage controllers, there is one Fibre Channel card. The chip can contain two Fibre Channel ports and two Peripheral Component Interconnect (PCI) ports. The Fibre Channel card connects to each Fibre Channel port. Each Fibre Channel port can virtualize two virtual Fibre Channel ports, meaning all Fibre Channel ports can virtualize four virtual Fibre Channel ports. Each virtual Fibre Channel port can connect to one PCI port. In other words, for each Fibre Channel port, one virtual Fibre Channel port can be bound to one PCI port. Thus, each PCI port can connect to two virtual Fibre Channel ports at one end and to a control memory at the other end.

[0043] Furthermore, the aforementioned chip can be a Field-Programmable Gate Array (FPGA) for customized hardware logic. The Fibre Channel card can be understood as a Fibre Channel host bus adapter card, which can be an interface card connecting the server and the storage network. The aforementioned Peripheral Component Interconnect (PCIe) bus can be a high-speed computer expansion bus standard, and the PCIe port can be a PCIe port. The aforementioned storage controller is the core unit managing storage device input / output (I / O) scheduling, data caching, and Redundant Array of Independent Disks (RAID) functions, working in conjunction with the aforementioned chip (such as an FPGA) to achieve multi-controller resource sharing.

[0044] Furthermore, in a specific implementation, in the storage device provided in the embodiments of the present invention, the interior of the chip may include a peripheral component interconnect architecture (PCIe Fabric) component with a peripheral component interconnect bus port; the peripheral component interconnect architecture component can be used to perform aggregation logic with the internal channels of the chip through a peripheral component interconnect bus switch to build a communication network between each storage controller and the chip; the peripheral component interconnect architecture component supports multi-port parallel transmission and uses dynamic channel bonding to allocate bandwidth on demand.

[0045] In implementation, the peripheral component interconnect architecture can be based on PCIe 4.0 / 5.0 high-speed interconnect technology. Through PCIe switching and FPGA internal channel aggregation logic, a low-latency communication network can be built between multiple controllers (e.g., four controllers) and the FPGA. PCIe 4.0 / 5.0 single-channel bandwidth reaches 16GT / s (approximately 1.969GB / s) and 32GT / s (approximately 3.938GB / s) respectively, supporting higher throughput and lower latency. This invention can utilize PCIe expansion technology based on a switched architecture to achieve point-to-point communication between multiple devices through a PCIe switch, breaking the bandwidth limitations of traditional bus architectures. The module integrates a PCIe switch, supporting full interconnection between multiple controllers (such as server CPUs, storage controllers, etc.) and the FPGA, with each controller able to independently access FPGA resources. The aforementioned aggregation logic is a resource integration and optimization technology implemented through hardware and software design. Its core objective is to merge multiple independent low-speed channels, devices, or data streams into a logically high-speed channel or whole to improve system performance, reliability, or resource utilization.

[0046] It's worth noting that the peripheral component interconnect architecture can support simultaneous data transmission from multiple physical ports, enabling parallel communication. It utilizes dynamic channel binding to combine multiple independent channels into a single logical link, dynamically allocating bandwidth resources based on business needs. This avoids the bottleneck of controllers queuing for transmission, common in traditional single-channel architectures. When a controller needs to handle a sudden surge in traffic (such as data backup or video stream loading), multiple idle channels can be temporarily bound, allocating higher bandwidth (e.g., upgrading from x4 to x8). When traffic decreases, the channels can be released and allocated to other controllers. This on-demand allocation mode avoids resource waste caused by fixed bandwidth allocation, further improving overall bandwidth utilization. Furthermore, when multiple controllers concurrently access the front-end interface, sudden traffic surges (such as multiple controllers writing data simultaneously) can cause congestion on the peripheral component interconnect bus or front-end interface, leading to increased latency or even data loss. The peripheral component interconnect architecture can integrate traffic shaping functionality, using mechanisms such as queue management and rate limiting to regulate data flow. For example, by limiting the maximum transmission rate of a single storage controller, bandwidth resources can be reserved for other storage controllers, preventing congestion caused by sudden traffic surges. Meanwhile, the peripheral component interconnect architecture supports hot-swapping and link redundancy (such as dual PCIe switch cascading), ensuring high availability of multi-controller systems. When a storage controller or PCIe device fails, maintenance personnel can directly remove and replace the faulty component without interrupting storage system services, significantly improving business continuity.

[0047] Furthermore, in a specific implementation, in the above-described storage device provided in the embodiments of the present invention, the chip may include a Fibre Channel component with a Fibre Channel port; the Fibre Channel component can be used to realize the conversion between the Fibre Channel protocol and the peripheral interconnect component bus protocol; the Fibre Channel component supports multiple rate standards and is connected to the peripheral interconnect component architecture component through an on-chip bus.

[0048] In implementation, the Fibre Channel component can achieve high-speed physical layer communication based on the FC-PH protocol, supporting 16G / 32G / 64G FC multi-rate standards (maximum bandwidth 64Gbps). It connects to the aforementioned peripheral components via an on-chip high-speed bus, and hardware-accelerated FC-2 layer protocol processing (such as frame encapsulation, cyclic redundancy check, and buffer-to-buffer credit flow control) ensures microsecond-level latency (<5μs) and lossless transmission (zero packet loss). The Fibre Channel component's dual-protocol stack is compatible with traditional SCSI and NVMe over FC (a technology combining NVMe protocol with FC network): the SCSI protocol adapts to traditional disk arrays, while NVMe over FC uses FC-NVMe command pass-through parsing, reducing protocol conversion overhead and increasing the input / output operations per second (IOPS) of all-flash arrays by 40%. The Fibre Channel component can also integrate rate adaptive circuitry to dynamically adjust the link rate (e.g., downgrading from 64G FC to 32G FC) to maintain connection stability.

[0049] Furthermore, in a specific implementation, in the storage device provided in the embodiments of the present invention, the internal structure of the chip may include a virtualization engine; the virtualization engine can be used to virtualize each Fibre Channel port into at least two independent logical ports as virtual Fibre Channel ports, perform spatial isolation of memory access of each storage controller through a multi-channel memory access mapping table, and achieve mutual exclusion access through hardware semaphores.

[0050] In implementation, the virtualization engine can virtualize each physical Fibre Channel port of the Fibre Channel card into four independent logical ports through FPGA hardware logic, with each port transparently bound to a storage controller. The virtualization engine can integrate multi-channel DMA mapping tables and hardware semaphore mechanisms to ensure data isolation and atomic operations between multiple controllers, avoiding resource contention (such as concurrent write conflicts). For example, when four controllers share the same 64G Fibre Channel card, interface utilization increases from 60% in traditional solutions to 95%, and hardware costs are reduced by 60%.

[0051] Furthermore, in a specific implementation, the storage device provided in the embodiments of the present invention includes a heartbeat detection component and a fault switching component internally within the chip. The heartbeat detection component maintains a heartbeat connection with each storage controller to monitor the health status of each storage controller and receives heartbeat signals from each storage controller within a set period. The heartbeat detection component has a built-in timeout counter and digital filter logic to determine if a storage controller has failed when a set number of heartbeats are lost. When a storage controller fails, a hardware interrupt alarm is triggered, and the fault switching component is notified. The heartbeat detection component supports dynamic configuration of the heartbeat frequency to adapt to different disaster recovery levels. The fault switching component, upon receiving the notification alarm information from the heartbeat detection component, isolates the failed storage controller and migrates unfinished input / output requests to other storage controllers besides the failed one.

[0052] It should be noted that traditional multi-path service redundancy solutions require the server to actively detect path failures and switch over, with switching times typically ranging from tens of seconds to several minutes, which is quite lengthy. In contrast, this application uses a shared Fibre Channel card to achieve storage device failures with sub-second switching, and the server remains unaware of the failure.

[0053] In implementation, the heartbeat detection component can monitor the health status of multiple controllers in real time through FPGA hardware circuitry. Each controller sends a heartbeat signal to the FPGA at a configurable interval (e.g., 10ms). The heartbeat detection component has a built-in timeout counter and digital filtering logic, which can detect three consecutive lost heartbeats (30ms timeout) to determine a controller failure and trigger a hardware interrupt alarm. The hardware-software coordination mechanism of the heartbeat detection component, combined with FPGA status registers and driver-layer health checks, can avoid false judgments (such as transient signal interference). Fault events are notified to the load balancing and failover components via PCIe Message Signaled Interrupts – Extended (MSI-X) interrupts, initiating a sub-second (<50ms) response process. The heartbeat detection component can support dynamic configuration of the heartbeat frequency (1ms-1s) to adapt to different disaster recovery levels (e.g., RTO <1s in financial scenarios). By using redundant signal paths and cyclic redundancy check (CRC), the detection reliability reaches 99.999%, and the fault perception delay is <1ms. This is a hundred times more efficient than traditional software solutions (second-level polling), providing a millisecond-level fault recovery foundation for multi-control systems.

[0054] The failover component enables seamless service migration at the millisecond level in the event of storage controller failure, ensuring storage service continuity. The hardware architecture of the failover component can include: a caching sub-component and a transmission result detection sub-component; the caching sub-component caches transmitted data; the transmission result detection sub-component clears the data in the caching sub-component when successful data transmission is detected, and retains the data in the caching sub-component when transmission failure is detected.

[0055] In implementation, when the sending result detection subcomponent detects successful transmission, it clears the data in the cache subcomponent; when the sending result detection subcomponent detects transmission failure, it retains the data in the cache subcomponent. It also works in conjunction with a heartbeat detection subcomponent for failover. When the heartbeat detection subcomponent triggers a fault alarm, the failover subcomponent can isolate the faulty controller within 50ms, migrate incomplete I / O requests to a backup port, and notify the storage software layer to complete the path switch (total RTO < 100ms).

[0056] Furthermore, in a specific implementation, in the storage device provided in the embodiments of the present invention, the chip may include a load balancing component; the load balancing component may include a monitoring sub-component, a weight and priority arbitrator, and a cache management queue; the monitoring sub-component is used to collect the request rate, queue depth, and latency of each storage controller; the weight and priority arbitrator is used to allocate Fibre Channel bandwidth using a hybrid scheduling strategy based on the data collected by the monitoring sub-component; and the cache management queue is used to allocate buffer pools for each storage controller.

[0057] In implementation, the load balancing component can optimize the utilization of shared Fibre Channel bandwidth by multiple controllers (e.g., four controllers) in real time based on a dynamic arbitration algorithm accelerated by FPGA hardware. The load balancing component monitors the load of each PCIe channel to ensure load balancing. Its core components include: a monitoring sub-component that collects request rates, queue depths, and latency for each controller via hardware counters; a weighted priority arbiter that dynamically allocates physical Fibre Channel bandwidth using a hybrid scheduling strategy (e.g., weighted round-robin + minimum latency priority); and a buffer management queue that allocates an independent buffer pool for each controller to absorb burst traffic. For example, high-priority database transactions can exclusively occupy 40% of the bandwidth, while backup tasks are rate-limited to 10%. The module achieves microsecond-level (<2μs) decision-making through hardware logic, avoiding software scheduling overhead and increasing Fibre Channel port utilization from 60% to 90%, improving system IOPS by 35%. It supports dynamic policy configuration, such as adapting to changes in service load by combining the intelligent platform management interface with the expressive state transition application programming interface (IPMI / REST API), and ensuring critical service performance by combining QoS tags (e.g., NVMe priority flows). This design reduces the load difference among multiple controllers from 70% in traditional solutions to 15%, significantly improving resource fairness.

[0058] Furthermore, in a specific implementation, in the storage device provided in the embodiments of the present invention, the chip includes a memory access engine; the memory access engine is used to detect whether there is data to be transferred in the memory of the Fibre Channel card; if there is, the data to be transferred is retrieved from the memory of the Fibre Channel card and transferred to the memory area on the storage controller.

[0059] In implementation, the memory access engine can be a Direct Memory Access (DMA) engine. The memory access engine can achieve direct data transfer between the storage controller and the Fibre Channel card through a multi-channel zero-copy transfer mechanism, bypassing processor and system memory bottlenecks. Its core components include: at least two independent memory access channels, each bound to a storage controller, supporting concurrent transfer; and a priority scheduler that dynamically adjusts the transfer order according to load balancing strategies (e.g., preemption of high-priority I / O).

[0060] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0061] Embodiments of this application also provide a method for processing a storage device, wherein the storage device includes a Fibre Channel card, a chip, and at least two storage controllers; the chip includes at least two Fibre Channel ports and at least two peripheral component interconnect bus ports. Figure 4 A flowchart of a processing method for a storage device provided in an embodiment of the present invention is shown below. Figure 4 As shown, the processing method includes the following steps:

[0062] S401. Connect the Fibre Channel card to each Fibre Channel port.

[0063] S402. Create at least two virtual Fibre Channel ports on each Fibre Channel port; each virtual Fibre Channel port corresponds one-to-one with the peripheral component interconnect bus port.

[0064] S403. Connect the virtual Fibre Channel ports sequentially to the corresponding peripheral component interconnect bus ports.

[0065] S404. Connect the interconnect bus ports of each peripheral component to the corresponding storage controller.

[0066] In the processing method of the storage device provided in the embodiments of the present invention, steps S401 to S404 can be executed to connect the Fibre Channel card to each physical Fibre Channel port in the chip. Each physical Fibre Channel port in the chip virtualizes at least two virtual Fibre Channel ports, so that a single physical port can be shared by multiple storage controllers. Compared with the mode in the traditional multi-controller architecture where each controller occupies an independent physical port, the number of Fibre Channel cards is significantly reduced, and efficient reuse of hardware resources is achieved. In addition, each virtual Fibre Channel port virtualized by each physical Fibre Channel port corresponds one-to-one with the peripheral component interconnect bus port, and each peripheral component interconnect bus port is connected to the corresponding virtual Fibre Channel port and the storage controller, avoiding the need to design dedicated interface circuits for different controllers, further reducing the hardware complexity and cost of the chip and motherboard. When it is necessary to add controllers or front-end devices, it is only necessary to adjust the number or mapping relationship of virtual ports through software, without adding additional physical port hardware, further reducing expansion costs. Therefore, the above-mentioned storage device processing method enables at least two storage controllers to share a Fibre Channel card, achieving hardware-level virtualization through the chip. This solves at least the problems of high cost and low resource utilization caused by the inability to share storage front-end interfaces among multiple controllers in related technologies, enabling multi-controller resource sharing, improving resource utilization, and significantly enhancing the performance and availability of the storage system.

[0067] Since the embodiments of the processing method portion of the storage device correspond to the embodiments of the storage device portion, the description of the features in the embodiment corresponding to the processing method of the storage device can be found in the relevant description of the embodiment corresponding to the storage device, and will not be repeated here. Furthermore, it has the same beneficial effects as the storage device mentioned above.

[0068] Furthermore, in a specific implementation, the processing method for the storage device provided in the embodiments of the present invention may further include: forming a peripheral component interconnect architecture component with peripheral component interconnect bus ports inside the chip; using the peripheral component interconnect architecture component to perform aggregation logic with the chip's internal channels through a peripheral component interconnect bus switch to construct a communication network between each storage controller and the chip. This peripheral component interconnect architecture component can support multi-port parallel transmission and allocate bandwidth on demand using a dynamic channel bonding method.

[0069] Furthermore, in a specific implementation, the processing method for the storage device provided in the embodiments of the present invention may further include: forming a Fibre Channel component with a Fibre Channel port inside the chip; and using the Fibre Channel component to realize the conversion between the Fibre Channel protocol and the peripheral interconnect component bus protocol. The Fibre Channel component supports multiple rate standards and is connected to the peripheral interconnect architecture component via an on-chip bus.

[0070] Furthermore, in a specific implementation, the processing method of the storage device provided in the embodiments of the present invention may further include: forming a virtualization engine inside the chip.

[0071] Accordingly, step S402 virtualizes at least two virtual Fibre Channel ports on each Fibre Channel port. Specifically, this may include: using a virtualization engine to virtualize each Fibre Channel port into at least two independent logical ports as virtual Fibre Channel ports, using a multi-channel memory access mapping table to achieve spatial isolation of memory access for each storage controller, and using hardware semaphores to achieve mutual exclusion access.

[0072] Furthermore, in a specific implementation, the processing method of the storage device provided in the embodiments of the present invention may further include: forming a heartbeat detection component and a fault switching component inside the chip; using the heartbeat detection component to monitor the health status of each storage controller and receiving heartbeat signals sent by each storage controller within a set period; wherein, the heartbeat detection component has a built-in timeout counter and digital filter logic, used to determine that a storage controller has failed when a set number of heartbeats are lost; triggering a hardware interrupt alarm when a storage controller fails and notifying the fault switching component; the heartbeat detection component supports dynamic configuration of the heartbeat frequency to adapt to different disaster recovery levels. After receiving the notification alarm information sent by the heartbeat detection component, the fault switching component isolates the faulty storage controller and migrates unfinished input / output requests to other storage controllers besides the faulty storage controller.

[0073] Furthermore, in a specific implementation, the processing method of the storage device provided in the embodiments of the present invention may further include: forming a load balancing component inside the chip; and using the load balancing component to control the IO balancing connected to the storage controller. The load balancing component may include a monitoring sub-component, a weight and priority arbitrator, and a cache management queue; the monitoring sub-component is used to collect the request rate, queue depth, and latency of each storage controller; the weight and priority arbitrator is used to allocate Fibre Channel bandwidth using a hybrid scheduling strategy based on the data collected by the monitoring sub-component; and the cache management queue is used to allocate buffer pools for each storage controller.

[0074] Furthermore, in a specific implementation, the processing method of the storage device provided in the embodiments of the present invention may further include: forming a memory access engine inside the chip; using the memory access engine to detect whether there is data to be transferred in the memory of the Fibre Channel card; if so, retrieving the data to be transferred from the memory of the Fibre Channel card and transferring it to the memory area on the storage controller.

[0075] Embodiments of this application also provide a centralized storage system, including a server and any of the storage devices described above; wherein the Fibre Channel card of the storage device is installed on the server.

[0076] Embodiments of the present invention also provide an electronic device comprising the centralized storage system described above.

[0077] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0078] The foregoing has provided a detailed description of a storage device and its processing method, a centralized storage system, and an electronic device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A storage device, characterized in that, include: Fibre Channel card, chip, and at least two memory controllers; The chip includes at least two Fibre Channel ports and at least two peripheral component interconnect bus ports; The fiber channel card is connected to each of the fiber channel ports respectively; Each of the aforementioned fiber channel ports has at least two virtual fiber channel ports; Each of the virtual fiber channel ports corresponds one-to-one with the peripheral component interconnect bus port. Each of the peripheral component interconnect bus ports is connected to the corresponding virtual Fibre Channel port and the storage controller, respectively; The chip includes a virtualization engine; the virtualization engine is used to virtualize each of the fiber channel ports into at least two independent logical ports as the virtual fiber channel ports through hardware logic, to perform spatial isolation of memory access of each of the storage controllers through a multi-channel memory access mapping table, and to achieve mutual exclusion access through hardware semaphores. The chip internally includes a heartbeat detection component and a fault switching component; The heartbeat detection component maintains a heartbeat connection with each of the storage controllers to monitor the health status of each storage controller and receives heartbeat signals from each storage controller within a set period. The heartbeat detection component has a built-in timeout counter and digital filter logic to determine if a storage controller has failed when a set number of heartbeats are lost. When a storage controller fails, a hardware interrupt alarm is triggered, and the fault switching component is notified. The heartbeat detection component supports dynamic configuration of the heartbeat frequency to adapt to different disaster recovery levels. The fault switching component is used to isolate the faulty storage controller after receiving a notification alarm from the heartbeat detection component, and to migrate incomplete input / output requests to other storage controllers besides the faulty storage controller. The fault switching component includes a cache sub-component and a transmission result detection sub-component. The cache sub-component is used to cache transmitted data. The transmission result detection sub-component is used to clear the data in the cache sub-component when successful data transmission is detected, and to retain the data in the cache sub-component when data transmission failure is detected.

2. The storage device according to claim 1, characterized in that, The chip internally includes a peripheral component interconnect architecture component having the peripheral component interconnect bus port; The peripheral component interconnect architecture component is used to aggregate logic with the internal channels of the chip through the peripheral interconnect component bus switch to build a communication network between each memory controller and the chip; The peripheral component interconnection architecture supports multi-port parallel transmission and uses dynamic channel bonding to allocate bandwidth on demand.

3. The storage device according to claim 2, characterized in that, The chip internally includes a fiber channel component having the fiber channel port; The Fibre Channel component is used to convert between the Fibre Channel protocol and the peripheral interconnect component bus protocol; The Fibre Channel component supports multiple rate standards and is connected to the peripheral component interconnect architecture component via an on-chip bus.

4. The storage device according to claim 1, characterized in that, The chip includes a load balancing component. The load balancing component includes a monitoring sub-component, a weight and priority arbitrator, and a cache management queue. The monitoring sub-component is used to collect the request rate, queue depth, and latency of each of the storage controllers; The weighted priority arbitrator is used to allocate fiber channel bandwidth based on the data collected by the monitoring sub-component using a hybrid scheduling strategy. The cache management queue is used to allocate buffer pools to each of the storage controllers.

5. The storage device according to claim 1, characterized in that, The chip includes a memory access engine; The memory access engine is used to detect whether there is data to be transferred in the memory of the Fibre Channel card; If it exists, the data to be transferred is retrieved from the memory of the Fibre Channel card and transferred to the memory area on the storage controller.

6. A method for processing a storage device as described in any one of claims 1 to 5, characterized in that, The storage device includes a Fibre Channel card, a chip, and at least two storage controllers; the chip includes at least two Fibre Channel ports and at least two peripheral component interconnect bus ports; the processing method includes: Connect the fiber channel card to each of the fiber channel ports respectively; At least two virtual Fibre Channel ports are created on each of the aforementioned Fibre Channel ports; each of the virtual Fibre Channel ports created on each of the aforementioned Fibre Channel ports corresponds one-to-one with the peripheral component interconnect bus port. The virtual fiber channel ports are sequentially connected to the corresponding peripheral component interconnect bus ports. Connect the interconnect bus ports of each peripheral component to the corresponding storage controller.

7. A centralized storage system, characterized in that, It includes a server and a storage device as described in any one of claims 1 to 5; wherein the Fibre Channel card of the storage device is installed on the server.

8. An electronic device, characterized in that, Including the centralized storage system as described in claim 7.

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