Method for detecting weaknesses in an integrated circuit power distribution network

Abstract

The application provides a kind of integrated circuit power distribution network weak point detection method, comprising the following steps: obtaining the physical structure data of power distribution network, generating the sparse matrix A representing the relationship between node voltage and current;Through the block processing of nested partitioning and reordering technology to sparse matrix A, construct single-layer BBD matrix, decouple the matrix into K independent sub-matrix;Based on parallel computing architecture, perform LDL decomposition on each sub-matrix, and only calculate the diagonal elements in the inverse matrix to locate the weak nodes or coupling branches that cause abnormal voltage drop;Generate weak point position information distribution map according to the diagonal element results of inverse matrix to guide the optimization design of power distribution network structure.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit power integrity analysis technology, specifically relating to a method for detecting weaknesses in integrated circuit power distribution networks (PDNs). For detecting structural weaknesses in power distribution networks (PDNs), this method rapidly locates weak nodes or coupling branches in the PDN that cause abnormal voltage drops through large-scale sparse matrix block decomposition and parallel element selection and inversion. It is applicable to chip, package, and circuit board level PDN design verification. Background Technology

[0002] In power integrity analysis of integrated circuit design, traditional large-scale sparse matrix inversion techniques suffer from significant computational bottlenecks, particularly in critical scenarios involving the detection of weaknesses in power distribution network (PDN) structures. While iterative methods offer some computational efficiency, their insufficient convergence accuracy often leads to inaccuracies in high-precision analysis at advanced process nodes below 5nm, resulting in inaccurate weakness localization. Direct methods rely on full matrix triangular decomposition (such as LU decomposition and Cholesky decomposition), where O(n 3 The issues of time complexity and the surge in padding elements pose a dual challenge when processing PDN matrices with hundreds of millions of nodes: superlinear growth in computation time and excessive memory consumption, which severely restricts the efficiency of engineering applications.

[0003] In applications where only partial matrix inverses need to be calculated (such as the diagonal elements of the inverse matrix required for PDN voltage drop analysis), the limitations of traditional methods are particularly pronounced. Existing element-selective inversion algorithms (such as the SelInv technique based on LDL decomposition) optimize the complexity to O(n) by focusing on solving the diagonal elements. 2 However, problems such as the surge in filler elements, low parallel computing efficiency, and poor scenario adaptability still exist. These technical bottlenecks make it difficult for existing methods to meet the timeliness requirements of engineering verification when analyzing high-density PDN matrices with over 1 billion nodes on a single chip at advanced process nodes below 5nm. There is an urgent need for efficient parallel solution technology for high-density coupled structures.

[0004] In the field of large-scale sparse matrix processing, traditional direct matrix inversion techniques face significant challenges. These techniques require inverting the entire matrix, leading to an exponential increase in computational complexity and inefficiency when dealing with ultra-large-scale matrices. This is particularly true in power distribution network matrix analysis scenarios with over 1 billion nodes, where practical needs often focus only on calculating the diagonal or sub-diagonal elements of the matrix inversion. The traditional full-matrix inversion approach results in a severe waste of computational resources. Furthermore, existing technologies lack efficient algorithms for element-selective inversion of sparse matrices. Overfilling with non-zero elements not only dramatically increases storage space requirements, making it difficult to meet the storage needs of practical applications, but also suffers from insufficient parallel scalability, failing to fully unleash the parallel computing potential of multi-core processors and further exacerbating the performance bottleneck of large-scale matrix processing. Summary of the Invention

[0005] To address the shortcomings and deficiencies of existing technologies, this invention provides a block matrix element selection and inversion calculation method for vulnerability detection in high-density integrated circuit power distribution networks (PDNs), and implements integrated circuit power distribution network vulnerability detection based on this method. The technological breakthrough is achieved through the following innovative design:

[0006] Single-layer BBD matrix partitioning technology: Based on a nested partitioning and reordering strategy, the ultra-large-scale sparse matrix is ​​decoupled into multiple independent sub-matrix units, suppressing the surge of filling elements and significantly reducing memory consumption;

[0007] Parallel LDL decomposition and directed element selection inversion: Combining a multi-core CPU / GPU parallel architecture, LDL decomposition is performed synchronously on the partitioned submatrices, calculating only the diagonal elements of the inverse matrix, reducing the complexity from the existing O(n)... 2 Optimized to Computational efficiency is improved by 1-2 orders of magnitude;

[0008] Dynamic optimization of dual-layer BBD structure: By constructing a dual-layer nested BBD matrix through iterative loop and inverse transformation, adaptive optimization of the matrix block structure is achieved, supporting real-time analysis of 1 billion-level PDN matrices in advanced process nodes below 5nm;

[0009] This invention overcomes the computational and storage bottlenecks in high-density PDN matrix processing, providing an efficient and accurate engineering solution for integrated circuit power integrity analysis.

[0010] The specific technical solution adopted by this invention to solve its technical problem is as follows:

[0011] A method for detecting weaknesses in integrated circuit power distribution networks includes the following steps:

[0012] Obtain the physical structure data of the power distribution network and generate a sparse matrix A representing the relationship between node voltage and current;

[0013] The sparse matrix A is divided into blocks by nested partitioning and reordering techniques to construct a single-layer BBD matrix, thus decoupling the matrix into K independent sub-matrices.

[0014] Based on a parallel computing architecture, LDL decomposition is performed on each submatrix, and only the diagonal elements in the inverse matrix are computed to locate weak nodes or coupled branches that cause abnormal voltage drops.

[0015] A weakness location information distribution map is generated based on the diagonal elements of the inverse matrix to guide the optimal design of the power distribution network structure.

[0016] Furthermore, the nested segmentation and reordering technique uses a nested partitioning and permutation algorithm to sort the sparse matrix A, and sets the ratio of coupled blocks to diagonal blocks during block processing.

[0017] Furthermore, the single-layer BBD matrix is ​​constructed through the inverse transformation of the two-layer BBD matrix, specifically including:

[0018] The diagonal submatrix of the single-layer BBD matrix is ​​divided into two sub-blocks to form a nested double-layer BBD structure;

[0019] The coupling edges of the two-layer BBD matrix are integrated into the coupling blocks of the initial single-layer BBD matrix, restoring it to a single-layer BBD matrix structure;

[0020] The block processing optimizes the matrix structure through iterative loops until the number of diagonal blocks reaches a preset target value; for diagonal blocks with non-BBD structures, an approximate minimum degree sorting strategy is used.

[0021] Furthermore, the parallel computing architecture is implemented based on a multi-core CPU or GPU cluster, and the LDL decomposition and element selection inversion operations of each submatrix are executed independently and in parallel.

[0022] Furthermore, the element selection and inversion operation is based on the non-zero structure of the sparse vector l, and only calculates the inverse matrix elements related to l, specifically including:

[0023] Decompose the submatrix into a scalar α, a vector a, and a submatrix S;

[0024] Using the formula S=A-aa T / α Update the submatrix;

[0025] Only the elements of the inverse matrix corresponding to the non-zero rows of e are calculated.

[0026] Furthermore, the weakness location information distribution map is integrated into the chip layout and routing stage through EDA tools to dynamically adjust the routing density of the power distribution network or the distribution of decoupling capacitors.

[0027] The weakness location information distribution map marks nodes or coupled branches with excessive voltage drop and generates an optimization suggestion report, including adding decoupling capacitors, adjusting the power grid width, or reducing the coupling path length.

[0028] Furthermore, the sparse matrix A is generated based on the physical structure data of the power distribution network, including the coordinates of the power grid nodes, the impedance parameters of the metal layer, and the current load distribution.

[0029] Furthermore, each submatrix of the single-layer BBD matrix is ​​merged with the bottom-right matrix and its coupling edges to form an independent matrix group:

[0030]

[0031] Among them, A k This is the diagonal submatrix after partitioning. This is the connection matrix between the submatrix and the global coupling block. is the global diagonal coupling matrix, and K is the number of blocks.

[0032] And, an integrated circuit power distribution network weakness detection system, comprising:

[0033] The data input module is used to acquire PDN physical structure data and generate a sparse matrix A;

[0034] The matrix partitioning module is used to construct a single-layer BBD matrix and decouple it into K sub-matrices;

[0035] Parallel computing module, which performs LDL decomposition and element selection inversion based on multi-core CPU or GPU clusters;

[0036] The results output module generates a distribution map of weakness location information and integrates it into the EDA tool.

[0037] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method described above.

[0038] A non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0039] Compared with the prior art, the present invention and its preferred embodiments have at least the following beneficial effects:

[0040] Significantly reduces computational complexity and memory usage: By using a single-layer BBD matrix partitioning technique, large-scale sparse matrices are decoupled into independent submatrices, suppressing the surge in non-zero element filling and reducing memory resource consumption; combined with a parallel element selection inversion method, it focuses only on the calculation of diagonal elements of the inverse matrix, breaking through the efficiency bottleneck of traditional full matrix inversion.

[0041] Enhance the adaptability of high-density coupled structures: Based on the nested segmentation and dual-layer BBD matrix dynamic optimization strategy, it supports PDN matrix processing with a scale of over 1 billion nodes, effectively addressing the real-time analysis needs of complex power networks in advanced process nodes.

[0042] Enhance engineering practicality: By dynamically integrating the weak point location information distribution map with EDA tools, the voltage drop anomaly node location results are directly mapped to the chip physical design stage, guiding the optimization of power grid routing and decoupling capacitor configuration, and shortening the design verification cycle.

[0043] Unleash the potential of parallel computing: Utilize multi-core CPU or GPU cluster architecture to achieve parallel decomposition and inversion operations of block matrices, significantly improving computing throughput and meeting the requirements of high-precision and high-timeliness engineering verification. Attached Figure Description

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0045] Figure 1 This is a schematic diagram of the original matrix structure during the application and implementation of this invention.

[0046] Figure 2 This is a schematic diagram of the partitioning structure of a single-layer BBD matrix when the present invention is applied.

[0047] Figure 3 This is a schematic diagram of the block matrix obtained by merging the diagonal matrix and the coupling edge when the present invention is applied.

[0048] Figure 4 This is a schematic diagram of the operation process when the present invention is applied.

[0049] Figure 5 This is a comparison chart showing the solution time of SelInv and block SelInv when the present invention is applied. Detailed Implementation

[0050] To make the features and advantages of the present invention more apparent and understandable, specific embodiments are described below in detail:

[0051] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0052] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0053] Addressing the pain points of existing technologies, one of the core improvements of this invention in integrated circuit power distribution network (PDN) weakness detection lies in proposing a single-layer bordered-block-diagonal (BBD) matrix block selection and inversion method for PDN structure weakness detection. A hierarchical single-layer bordered-block-diagonal matrix structure is constructed through nested partitioning and reordering techniques, decoupling the large-scale sparse matrix into multiple independent sub-matrix units that can be processed in parallel. Based on this, combined with parallel LDL decomposition technology, targeted element selection and inversion operations are performed on each sub-matrix. This innovative technical approach significantly reduces memory consumption and greatly improves solution efficiency during application, making it particularly suitable for real-time analysis of high-density PDN matrices with over 1 billion nodes on a single chip. The application of this method effectively overcomes the engineering application bottleneck of large-scale matrix processing under advanced process nodes, providing efficient and reliable technical support for power distribution network analysis in high-density integrated circuit design.

[0054] The implementation of the solution includes the following steps:

[0055] Step 1: Matrix preprocessing and block partitioning, receiving a large-scale sparse symmetric positive definite matrix A as input (e.g., Figure 1 As shown, matrix A is sorted using a nested partitioning method (dissect), and then divided into blocks according to the BBD structure principle. The proportions of coupled blocks and diagonal blocks in the matrix are set, with a default value of 5%, to construct a single-layer BBD matrix:

[0056]

[0057] Step 2: Constructing a two-layer BBD matrix. For each submatrix on the diagonal of the single-layer BBD matrix from Step 1, a second processing step is performed using nested partitioning and the principle of diagonal edge-based block division to transform the single-layer BBD matrix into a two-layer BBD matrix.

[0058]

[0059] During this process, the coupling edges of the single-layer BBD matrix need to be sorted synchronously to ensure that the sorting of the submatrix and the coupling edges matches one by one.

[0060] Step 3: Reverse transformation of the matrix structure. For the two-layer BBD matrix obtained in Step 2, the coupling edges corresponding to each diagonal submatrix are integrated into the coupling edges of the initial single-layer BBD matrix, thereby achieving the reverse transformation of the matrix structure and restoring the single-layer BBD matrix.

[0061]

[0062] in

[0063] Step four: Iterate through steps two and three, continuously optimizing the matrix structure until the number of diagonal blocks reaches a preset target value (default value is 30). At this point, output the permutation vector and the position information of each block. During the process, for diagonal blocks that do not conform to the BBD structure, an approximate minimum degree sorting strategy is used to improve the efficiency of subsequent calculations.

[0064] Step 5: Construct the merged block matrix, for multi-diagonal block single-layer BBD matrix (e.g.) Figure 2 As shown), each submatrix on the diagonal is merged with the matrix at the bottom right corner and its corresponding coupling edge to form multiple independent matrix groups:

[0065]

[0066] Step 6, Block LDL Decomposition: For the K block matrices obtained in Step 5, perform LDL decomposition operations synchronously using a parallel strategy (e.g., Figure 3 (As shown). The specific steps are as follows:

[0067] For each submatrix on the diagonal, perform LDL decomposition in parallel to obtain the corresponding lower triangular matrix L and diagonal matrix D.

[0068]

[0069] A is a non-singular symmetric positive definite matrix. The first step of LDL decomposition is to decompose matrix A, which can be expressed as:

[0070]

[0071] Step 7: Matrix Inversion. Based on the multiple lower triangular matrices L and their corresponding diagonal matrices D obtained in Step 6, the inverses of the matrices are solved in parallel. Specifically, the matrix inversion method is adopted, as shown in the following equation. When matrix A is a sparse symmetric positive definite matrix, and only the diagonal components of its inverse matrix need to be calculated, computation time can be significantly reduced. The specific operation is as follows:

[0072] If vector e is sparse, when calculating S -1 When e, there is no need to calculate S in advance. -1 All elements of A are obtained by using only the elements in the rows and columns corresponding to the non-zero rows of e. Therefore, in order to calculate A... -1 For all diagonal elements, only the subsequent calculation of A needs to be solved. -1 The elements required for calculation are determined entirely by the non-zero structure of the lower triangular factor l.

[0073]

[0074] This expression indicates that once matrix A and the lower triangular matrix L are determined, A is calculated. -1 The task can be simplified to calculating S -1 The task.

[0075] Step 8: Merge all diagonal element values. Based on the diagonal components of the inverse matrices of each diagonal block obtained in Step 7, extract and merge their diagonal element values ​​to obtain the final A. -1 All diagonal elements.

[0076] In the field of integrated circuit power integrity analysis, traditional direct matrix inversion techniques face severe challenges for high-density power distribution network (PDN) matrices with over 1 billion nodes per chip. Methods based on full matrix decomposition (such as LU / Cholesky decomposition) are limited by O(n) 3 The time complexity bottleneck is a significant issue. When processing PDN matrices for advanced process nodes below 5nm, the surge in fill elements leads to a superlinear increase in memory usage. Iterative methods are affected by the matrix condition number, making it difficult to guarantee convergence accuracy and meet the high-precision real-time analysis requirements for nodes with abnormal voltage drops in engineering verification. Even existing element selection and inversion techniques (such as SelInv) still suffer from insufficient parallel scalability and high non-zero element fill rate when dealing with the high-density coupled structure of PDN matrices.

[0077] Compared to existing technologies, the single-layer BBD matrix block selection and inversion method developed in this invention for PDN structural weakness detection scenarios has significant technical advantages. By employing a nested partitioning-based reordering technique, the original sparse matrix is ​​transformed into a multi-diagonal block single-layer BBD matrix structure, decoupling the large-scale matrix into 20 to 50 independent sub-matrix units that can be processed in parallel, thereby significantly reducing computational complexity. Utilizing parallel computing technology, each sub-matrix undergoes independent decomposition and inversion operations, fully unleashing the parallel computing potential of multi-core processors and significantly improving computational efficiency. Simultaneously, through a sparse matrix optimization sorting strategy, the filling growth of non-zero elements is significantly suppressed, further reducing memory consumption. The specific implementation process is as follows: Figure 4 As shown, the implementation path of the present invention is clearly illustrated.

[0078] This scheme is based on the calculation of the diagonal components of the inverse of a sparse matrix, giving it a unique advantage in applications requiring only a subset of the matrix's inverse elements. Theoretically, this invention breaks through the traditional framework of element selection for inversion, providing a new methodology for efficient sparse matrix solving. Practical application data demonstrates (e.g.) Figure 5 As shown in the figure, this technology maintains high-precision calculation while improving the computational efficiency by one to two orders of magnitude compared to the closest existing solution. It effectively meets the engineering requirements of power integrity analysis under advanced process nodes and promotes the practical development of matrix inversion calculation technology in high-density integrated circuit design.

[0079] Based on the same inventive concept, this invention also provides a computer device, comprising: one or more processors, and a memory for storing one or more computer programs; the programs include program instructions, and the processor executes the program instructions stored in the memory. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, used to implement one or more instructions, specifically for loading and executing one or more instructions stored in a computer storage medium to implement the above-described method.

[0080] It should be further explained that, based on the same inventive concept, the present invention also provides a computer storage medium storing a computer program, which, when executed by a processor, performs the above-described method. This storage medium can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0081] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

[0083] This invention is not limited to the preferred embodiment described above. Anyone inspired by this invention can derive other various forms of integrated circuit power distribution network weakness detection methods. All equivalent variations and modifications made within the scope of the claims of this invention should be included in the scope of this invention.

Claims

1. A method for detecting weaknesses in integrated circuit power distribution networks, characterized in that, Includes the following steps: Obtain the physical structure data of the power distribution network and generate a sparse matrix A representing the relationship between node voltage and current; The sparse matrix A is divided into blocks by nested partitioning and reordering techniques to construct a single-layer BBD matrix, thus decoupling the matrix into K independent sub-matrices. Based on a parallel computing architecture, LDL decomposition is performed on each submatrix, and only the diagonal elements in the inverse matrix are computed to locate weak nodes or coupled branches that cause abnormal voltage drops. A distribution map of weak point locations is generated based on the diagonal elements of the inverse matrix to guide the optimal design of the power distribution network structure. The single-layer BBD matrix is ​​constructed through the inverse transformation of the double-layer BBD matrix, specifically including: The diagonal submatrix of the single-layer BBD matrix is ​​divided into two sub-blocks to form a nested double-layer BBD structure; The coupling edges of the two-layer BBD matrix are integrated into the coupling blocks of the initial single-layer BBD matrix, restoring it to a single-layer BBD matrix structure; The block processing optimizes the matrix structure through iterative loops until the number of diagonal blocks reaches a preset target value; for diagonal blocks with non-BBD structures, an approximate minimum degree sorting strategy is used.

2. The method for detecting weaknesses in integrated circuit power distribution networks according to claim 1, characterized in that: The nested partitioning and reordering technique uses a nested partitioning and permutation algorithm to sort the sparse matrix A, and sets the ratio of coupled blocks to diagonal blocks during block processing.

3. The method for detecting weaknesses in integrated circuit power distribution networks according to claim 1, characterized in that: The parallel computing architecture is implemented based on a multi-core CPU or GPU cluster, and the LDL decomposition and element selection inversion operations of each submatrix are executed independently and in parallel.

4. The method for detecting weaknesses in integrated circuit power distribution networks according to claim 3, characterized in that: The element selection and inversion operation is based on sparse vectors. The non-zero structure is calculated only with respect to... The relevant inverse matrix elements specifically include: Decompose the submatrix into a scalar α, a vector a, and a submatrix S; Through the formula S= Update the submatrix; Only calculate with The inverse matrix elements corresponding to non-zero rows.

5. The method for detecting weaknesses in integrated circuit power distribution networks according to claim 1, characterized in that: The weakness location information distribution map is integrated into the chip layout and routing stage through EDA tools to dynamically adjust the routing density of the power distribution network or the distribution of decoupling capacitors. The weakness location information distribution map marks nodes or coupled branches with excessive voltage drop and generates an optimization suggestion report, including adding decoupling capacitors, adjusting the power grid width, or reducing the coupling path length.

6. The method for detecting weaknesses in integrated circuit power distribution networks according to claim 1, characterized in that: The sparse matrix A is generated based on the physical structure data of the power distribution network, including the coordinates of the power grid nodes, the impedance parameters of the metal layer, and the current load distribution.

7. The method for detecting weaknesses in integrated circuit power distribution networks according to claim 1, characterized in that: Each submatrix of the single-layer BBD matrix is ​​merged with the matrix at the bottom right corner and its coupling edge to form an independent matrix group: in, This is the diagonal submatrix after partitioning. This is the connection matrix between the submatrix and the global coupling block. is the global diagonal coupling matrix, and K is the number of blocks.

8. A vulnerability detection system for integrated circuit power distribution networks, used to implement the method as described in claim 1, characterized in that, include: The data input module is used to acquire PDN physical structure data and generate a sparse matrix A; The matrix partitioning module is used to construct a single-layer BBD matrix and decouple it into K sub-matrices; Parallel computing module, which performs LDL decomposition and element selection inversion based on multi-core CPU or GPU clusters; The results output module generates a distribution map of weakness location information and integrates it into the EDA tool.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-7.

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