Display panel, driving method thereof, and display device

Abstract

The application provides a display panel, a driving method thereof and a display device, which are used for realizing frequency differentiation design of different positions in a display area. The display panel comprises a plurality of data lines and a plurality of sub-pixels. The sub-pixel comprises a first transistor and a second transistor which are electrically connected in series between the data line and a storage capacitor. The gate of the first transistor and the gate of the second transistor respectively receive a first gate driving signal and a second gate driving signal. In a first mode, the working period of the display panel comprises at least a first period. In the first period, when the second gate driving signal received by the first sub-pixel is a second enable level, the first gate driving signal received by the first sub-pixel is a first non-enable level; and when the second gate driving signal received by the second sub-pixel is the second enable level, the first gate driving signal received by the second sub-pixel is a first enable level.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel and its driving method, and a display device. Background Technology

[0002] With the continuous development of science and technology, more and more display devices are being widely used in people's daily lives and work, becoming indispensable tools for people today. Moreover, with the continuous development of display technology, consumers' requirements for monitors are constantly increasing. How to achieve frequency differentiation design in different positions of the display area has become a research focus for relevant technical personnel. Summary of the Invention

[0003] In view of this, the present invention provides a display panel and its driving method and display device for realizing frequency differentiation design at different positions in the display area.

[0004] In a first aspect, the present invention provides a display panel including multiple data lines and multiple sub-pixel rows arranged along a first direction, each sub-pixel row including multiple sub-pixels arranged along a second direction, the first direction and the second direction intersecting; each sub-pixel includes a first transistor, a second transistor and a storage capacitor; wherein the first transistor and the second transistor are connected in series between the data lines and the storage capacitor. The gate of the first transistor receives the first gate drive signal. The gate of the second transistor receives the second gate drive signal. The display panel operates in several modes, including a first mode in which it includes at least a first sub-pixel and a second sub-pixel, and its operating cycle includes at least a first time period in which... When the second gate drive signal received by the first sub-pixel is at the second enable level, the first gate drive signal received by the first sub-pixel is at the first disable level; When the second gate drive signal received by the second sub-pixel is at the second enable level, the first gate drive signal received by the second sub-pixel is at the first enable level; Here, the first enable level refers to the level that controls the first transistor to turn on, the first disable level refers to the level that controls the first transistor to turn off, and the second enable level refers to the level that controls the second transistor to turn on.

[0005] Secondly, the present invention provides a driving method for a display panel. The display panel includes multiple data lines and multiple rows of sub-pixels arranged along a first direction. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and the first and second directions intersect. Each sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The first transistor and the second transistor are connected in series between the data lines and the storage capacitor. The gate of the first transistor receives a first gate driving signal, and the gate of the second transistor receives a second gate driving signal. The display panel operates in a first mode, wherein the display panel includes at least a first sub-pixel and a second sub-pixel, and the display panel's operating cycle includes at least a first time period, wherein the driving method during the first time period includes: When the second gate drive signal received by the first sub-pixel is at the second enable level, the first gate drive signal received by the first sub-pixel is controlled to be at the first disable level. When the second gate drive signal received by the second sub-pixel is at the second enable level, the first gate drive signal received by the second sub-pixel is controlled to be at the first enable level. Here, the first enable level refers to the level that controls the first transistor to turn on, the first disable level refers to the level that controls the first transistor to turn off, and the second enable level refers to the level that controls the second transistor to turn on.

[0006] Thirdly, the present invention provides a display device, including the display panel of the present invention.

[0007] Compared with the prior art, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects: The display panel provided by this invention includes multiple data lines and multiple sub-pixel rows arranged along a first direction. Each sub-pixel row includes multiple sub-pixels arranged along a second direction, and the first and second directions intersect. Each sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The first transistor and the second transistor are connected in series between the data lines and the storage capacitor. The gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal. The operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. The operating cycle of the display panel includes at least a first time period. In the first time period, when the second gate drive signal received by the first sub-pixel is at a second enable level, the first gate drive signal received by the first sub-pixel is at a first disable level. When the second gate drive signal received by the second sub-pixel is at a second enable level, the first gate drive signal received by the second sub-pixel is at a first enable level. The first enable level refers to the level that controls the first transistor to be turned on, the first disable level refers to the level that controls the first transistor to be turned off, and the second enable level refers to the level that controls the second transistor to be turned on. The sub-pixel provided by this invention includes a first transistor, a second transistor, and a storage capacitor. The first and second transistors are connected in series between a data line and the storage capacitor, allowing the charging of the sub-pixel to be jointly determined by a second gate driving signal and a first gate driving signal. The display panel of this invention has a first operating mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel, and the operating cycle of the display panel includes at least a first time period. During the first time period, under the control of the first gate driving signal, the data voltage writing path of the first sub-pixel is turned off, and under the control of the first gate driving signal, the data voltage writing path of the second sub-pixel is turned on. This allows the data refresh rate of the first sub-pixel to be lower than that of the second sub-pixel in the first mode, achieving a differentiated design of the data refresh rates of the first and second sub-pixels. The data refresh rate of a sub-pixel refers to the number of times data voltage is written to the sub-pixel per unit time. Based on the method provided by this invention, the data refresh rate of the first sub-pixel can be lower than the frequency of the second gate driving signal. That is, without changing the frequency of the second gate driving signal, at least the frequency reduction of the first sub-pixel can be achieved by designing the timing of the first gate driving signal received by the first sub-pixel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 An equivalent circuit diagram of a sub-pixel is provided for an embodiment of the present invention; Figure 3 A driving timing diagram of a first sub-pixel and a second sub-pixel in a first mode is provided for an embodiment of the present invention; Figure 4 Another timing diagram of the operation of the first sub-pixel and the second sub-pixel in the first mode provided in an embodiment of the present invention; Figure 5 A schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 7 This is a timing diagram of a mode control line provided in an embodiment of the present invention; Figure 8 A timing diagram for an embodiment of the present invention, showing a second gate line connecting a first sub-pixel, a second gate line connecting a second sub-pixel, and a gate driving bus; Figure 9 A timing diagram for another embodiment of the present invention, showing a second gate line connecting a first sub-pixel, a second gate line connecting a second sub-pixel, and a gate driving bus; Figure 10 A schematic diagram of another display panel provided in an embodiment of the present invention; Figure 11 A timing diagram of a display panel operating in a first mode, provided as an embodiment of the present invention; Figure 12 Timing diagrams of another display panel provided in the embodiments of the present invention in the first mode; Figure 13 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 14 A timing diagram for providing a second gate drive signal to a first sub-pixel and a second sub-pixel, a gate drive bus connected to the first sub-pixel, and a gate drive bus connected to the second sub-pixel, provided for an embodiment of the present invention; Figure 15A timing diagram for providing a second gate driving signal to a first sub-pixel and a second sub-pixel, a gate driving bus connected to the first sub-pixel, and a gate driving bus connected to the second sub-pixel, as provided in an embodiment of the present invention; Figure 16 for Figure 13 The diagram shown illustrates a timing diagram of the display panel in the first mode. Figure 17 for Figure 13 The diagram shown illustrates another operating timing of the display panel in the first mode; Figure 18 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 19 for Figure 18 The diagram shown illustrates a timing diagram of the display panel in the first mode. Figure 20 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 21 for Figure 20 The diagram shown illustrates a timing diagram of the display panel in the first mode. Figure 22 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 23 for Figure 22 The diagram shown illustrates a timing diagram of the display panel in the first mode. Figure 24 A schematic diagram of a first gate control circuit provided in an embodiment of the present invention; Figure 25 A driving timing diagram for yet another display panel provided in an embodiment of the present invention; Figure 26 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 27 A wiring diagram of a display panel provided in an embodiment of the present invention; Figure 28 A schematic diagram of an equivalent circuit for another sub-pixel provided in an embodiment of the present invention; Figure 29 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 30 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 31 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0011] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0012] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0013] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0014] This invention provides a display panel, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes multiple data lines Data, a first gate line 21, a second gate line 22, and multiple sub-pixel rows 1 arranged along a first direction h1. Each sub-pixel row 1 includes multiple sub-pixels 10 arranged along a second direction h2. The first direction h1 and the second direction h2 intersect. Figure 1 The first direction h1 and the second direction h2 are perpendicular as an illustration.

[0015] For example, such as Figure 2 As shown, Figure 2 An equivalent circuit diagram of a sub-pixel is provided in an embodiment of the present invention. The sub-pixel 10 includes a first transistor M1, a second transistor M2, and a storage capacitor Cst. The first transistor M1 and the second transistor M2 are connected in series between a data line Data and the storage capacitor Cst. When both the first transistor M1 and the second transistor M2 are turned on, the signal on the data line Data is written to the storage capacitor Cst through the turned-on first transistor M1 and the second transistor M2 to charge the storage capacitor Cst. When either of them is turned off, the signal on the data line Data stops writing to the storage capacitor Cst.

[0016] like Figure 2As shown, the first gate line 21 is electrically connected to the gate of the first transistor M1, and the second gate line 22 is electrically connected to the gate of the second transistor M2. The gate of the first transistor M1 receives the first gate drive signal GateV through the first gate line 21, and the gate of the second transistor M2 receives the second gate drive signal GateH through the second gate line 22.

[0017] For example, such as Figure 1 As shown, the second gate line 22 is electrically connected to the corresponding sub-pixel row 1. When the display panel is working, multiple second gate lines 22 sequentially provide the second enable level according to the scanning sequence of the display panel.

[0018] In this embodiment of the invention, the operating mode of the display panel includes a first mode. For example, the first mode may be a mode in which at least two sub-pixels in the display panel are driven by different data refresh frequencies.

[0019] In the first mode, such as Figure 1 As shown, the display panel includes at least one first sub-pixel 101 and at least one second sub-pixel 102. Figure 3 As shown, Figure 3 The present invention provides a driving timing diagram of a first sub-pixel and a second sub-pixel in a first mode, wherein the working period T of the display panel includes at least a first time period P1.

[0020] During the first time period P1, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is at the first disable level; that is, the data voltage write path of the first sub-pixel 101 can be deactivated. For example, during the first time period P1, the voltage on the storage capacitor Cst of the first sub-pixel 101 can maintain the data voltage written before the first time period P1. That is, this time period can be a data voltage maintenance period for the first sub-pixel 101.

[0021] During the first time period P1, when the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is at the first enable level; that is, the data voltage write path of the second sub-pixel 102 can be turned on, and the data voltage on the data line Data can be written to the storage capacitor Cst through the turned-on first transistor M1 and second transistor M2; that is, this time period can be the data voltage write period of the second sub-pixel 102.

[0022] Based on this configuration, the data refresh frequency of the first sub-pixel 101 can be lower than the frequency of the second gate driving signal GateH. Taking the frequency of the second gate driving signal GateH as f0, the data refresh frequency of the first sub-pixel 101 as f1, and the data refresh frequency of the second sub-pixel 102 as f2 as an example, based on the configuration provided in this embodiment of the invention, it is possible to achieve: f1 < f2 ≤ f0.

[0023] The display panel provided in this embodiment of the invention includes a first transistor M1 and a second transistor M2 in the sub-pixel 10, so that whether the sub-pixel 10 is charged or not can be jointly determined by the second gate driving signal GateH and the first gate driving signal GateV.

[0024] This invention allows the display panel to operate in a first mode. In this first mode, the display panel includes at least a first sub-pixel 101 and a second sub-pixel 102. The display panel's operating cycle T includes at least a first time period P1. During this first time period P1, under the control of the first gate driving signal GateV_101, the data voltage write path of the first sub-pixel 101 is turned off, and under the control of the first gate driving signal GateV_102, the data voltage write path of the second sub-pixel 102 is turned on. This allows the data refresh rate of the first sub-pixel 101 to be lower than that of the second sub-pixel 102 in the first mode, achieving a differentiated design between the data refresh rates of the first and second sub-pixels 101. The data refresh rate of sub-pixel 101 refers to the number of times data voltage is written to sub-pixel 101 per unit time.

[0025] Based on the method provided by the embodiments of the present invention, there is no need to adjust the frequency of the second gate driving signal GateH, and correspondingly, there is no need to adjust the circuit that provides the second gate driving signal. The data refresh frequency of the first sub-pixel 101 can be lower than the frequency of the second gate driving signal GateH. That is, without changing the frequency of the second gate driving signal GateH, at least the frequency reduction driving of the first sub-pixel 101 can be achieved by designing the timing of the first gate driving signal GateV_1 received by the first sub-pixel 101.

[0026] For example, such as Figure 3As shown, in the first mode, the working cycle T of the display panel includes at least a second time period P2, which is located before the first time period P1. In the second time period P2, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is at the first enable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is at the first enable level.

[0027] During the second time period P2, the data voltage write path of the first sub-pixel 101 and the data voltage write path of the second sub-pixel 102 are both turned on. Therefore, during the second time period P2, both the first sub-pixel 101 and the second sub-pixel 102 can perform data voltage write operations.

[0028] The voltage on the storage capacitor Cst of the first sub-pixel 101 can maintain the data voltage written in the second time period P2 during the first time period P1.

[0029] from Figure 3 It can be seen that one working cycle T of the display panel includes a second time period P2 and a first time period P1. Within one working cycle T of the display panel, the first sub-pixel 101 performs one data voltage write in the second time period P2, and the second sub-pixel 102 performs one data voltage write in both the second time period P2 and the first time period P1, that is, it performs two data voltage writes in total. In other words, within one working cycle T of the display panel, the first sub-pixel 101 can be charged once, and the second sub-pixel 102 can be charged twice, that is, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 can satisfy f0:f1:f2=2:1:2. Taking the frequency f0 of the second gate driving signal GateH as 60Hz as an example, based on this setting, the data refresh frequency f1 of the first sub-pixel 101 can be 30Hz, and the data refresh frequency f2 of the second sub-pixel 102 can be 60Hz.

[0030] For example, such as Figure 4 As shown, Figure 4 Another timing diagram of the first sub-pixel and the second sub-pixel in the first mode is provided for an embodiment of the present invention. In the first mode, in addition to the first time period P1 and the second time period P2 mentioned above, the working period T of the display panel also includes at least the third time period P3 and the fourth time period P4.

[0031] During the third time period P3, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is at the first disable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is at the first disable level.

[0032] That is, in the third time period P3, the second transistor M2 in the data voltage writing path of the first sub-pixel 101 and the second sub-pixel 102 are both turned off, and the first sub-pixel 101 and the second sub-pixel 102 stop writing data voltage in the third time period P3. The voltage on the storage capacitor Cst is maintained at the data voltage written in the second time period P2.

[0033] In the fourth time period P4, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is at the first enable level; when the second gate drive signal GateH_102 received by the second sub-pixel is at the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is at the first disable level.

[0034] That is, in the fourth time period P4, the data voltage write path in the first sub-pixel 101 is turned on, and the data voltage write path in the second sub-pixel 102 is turned off.

[0035] Based on making the data voltage refresh frequency of the first sub-pixel 101 lower than the data voltage refresh frequency of the second sub-pixel 102, the settings of the third time period P3 and the fourth time period P4 can also make the data refresh frequency of the second sub-pixel 102 lower than the frequency of the second gate drive signal GateH, thereby increasing the selectable range of the data refresh frequency of the second sub-pixel 102.

[0036] from Figure 4 It can be seen that one working cycle T of the display panel includes a second time period P2, two third time periods P3, two first time periods P1, and a fourth time period P4.

[0037] Within one working cycle T of the display panel, the first sub-pixel 101 performs a data voltage write once each in the second time period P2 and the fourth time period P4, that is, it performs a total of two data voltage writes. The second sub-pixel 102 performs a data voltage write once each in the second time period P2 and the two first time periods P1, that is, it performs a total of three data voltage writes.

[0038] In other words, within one working cycle T of the display panel, the first sub-pixel 101 can be charged twice, and the second sub-pixel 102 can be charged three times. This means that the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 satisfy f0:f1:f2 = 6:2:3. Taking a frequency f0 = 60Hz for the second gate driving signal GateH as an example, based on this setting, the data refresh frequency f1 of the first sub-pixel 101 can be set to 20Hz, and the data refresh frequency f2 of the second sub-pixel 102 to 30Hz.

[0039] Optionally, in the display panel, the area containing the second sub-pixel 102, which has a higher data refresh rate, can be used to display dynamic images such as animations or videos to ensure smoothness. The area containing the first sub-pixel 101, which has a lower data refresh rate, can be used to display static images such as text or pictures to reduce power consumption.

[0040] Optionally, the display panel can also operate in a second mode, in which the data refresh rate of each sub-pixel in the display panel can be equal.

[0041] For example, the second mode includes either the first sub-mode or the second sub-mode. In the first sub-mode, the data refresh frequency of each sub-pixel in the display panel can be consistent with the frequency of the second gate drive signal GateH. In this case, the first gate drive signal GateV provided to each sub-pixel can always be maintained at the first enable level.

[0042] In the second sub-mode, the data refresh rate of each sub-pixel in the display panel can be lower than the frequency of the second gate drive signal GateH. In this case, the first gate drive signal GateV provided to each sub-pixel can be the same, and all can be set according to the first gate drive signal GateV received by the first sub-pixel 101.

[0043] It should be noted that, Figure 2 The structure of sub-pixel 10 shown is only an illustration. The structure of sub-pixel 10 can be adjusted according to different design requirements in the embodiments of the present invention. For example, sub-pixel 10 can be set to include more transistors.

[0044] as well as, Figure 2The design of the first transistor M1 and the second transistor M2 as N-type transistors is merely illustrative. In this embodiment, each transistor in the sub-pixel 10 can be either an N-type or a P-type transistor. For N-type transistors, the enable level is high, and the disable level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are turned off. For P-type transistors, the enable level is low, and the disable level is high. That is, when the gate of a P-type transistor is low, its first and second terminals are connected; when the gate of a P-type transistor is high, its first and second terminals are turned off.

[0045] In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the enable level and non-enable level in the embodiments of the present invention are general terms. The enable level refers to any level that can turn on the transistor, and the non-enable level refers to any level that can turn off / turn off the transistor.

[0046] For example, the display panel includes a liquid crystal display panel. The liquid crystal display panel includes a liquid crystal layer, pixel electrodes, and a common electrode. The pixel electrodes can be electrically connected to a data line Data via the first transistor M1 and the second transistor M2. When the first transistor M1 and the second transistor M2 are turned on, the pixel electrodes can receive the data voltage provided by the data line Data. The common electrode can receive a common voltage. For example, the pixel electrodes can be electrically connected to the first plate of the storage capacitor Cst, and the common electrode is electrically connected to the second plate of the storage capacitor Cst. Liquid crystal molecules can be deflected by the voltage difference between the pixel electrodes and the common electrode.

[0047] For example, such as Figure 5 As shown, Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel includes a display area AA and a non-display area NA. The display area AA includes a first gate line 21, a second gate line 22 and the aforementioned sub-pixel 10.

[0048] The display panel includes a first gate control circuit 31, which includes a gate drive bus 310. In a first mode, the gate drive bus 310 is electrically connected to a first gate line 21, and the gate drive bus 310 is used to transmit the aforementioned first gate drive signal GateV. For example,... Figure 5 As shown, at least a portion of the first gate control circuit 31 may be located in the non-display area NA.

[0049] For example, such as Figure 5 As shown, in this embodiment of the invention, the gate drive bus 310 can be directly electrically connected to the first gate line 21.

[0050] Or, such as Figure 6 As shown, Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The first gate control circuit 31 further includes a mode control line 311 and a control transistor M3. The gate drive bus 310 is electrically connected to the first gate line 21 through the control transistor M3.

[0051] like Figure 6 As shown, the gate electrical connection mode control line 311 of the control transistor M3 is electrically connected to the gate drive bus 310, and the second gate is electrically connected to the first gate line 21.

[0052] Combination Figure 7 As shown, Figure 7 This is a timing diagram of a mode control line provided in an embodiment of the present invention. The operating mode of the display panel also includes a low-power mode MD0.

[0053] The mode control line 311 provides an enable level at least in the first mode MD1, so that the control transistor M3 is turned on at least in the first mode MD1, thereby providing the first gate drive signal transmitted by the gate drive bus 310 to the first gate line 21.

[0054] In low-power mode MD0, mode control line 311 provides an enable level to turn off control transistor M3, thereby stopping the transmission of signals from gate drive bus 310 to first gate line 21.

[0055] As can be seen, in low-power mode MD0, the connection between the gate drive bus 310 and the first gate line 21 is disconnected, and the signal on the gate drive bus 310 will not affect the signal on the first gate line 21. Therefore, in low-power mode MD0, no signal needs to be provided to the gate drive bus 310, that is, the gate drive bus 310 can be in a floating state without signal transmission, thereby reducing the power consumption of the display panel.

[0056] In low-power mode MD0, the first gate line 21 can retain the signal provided by the mode control line 311 before it switches to the disabled level.

[0057] For example, if the gate drive bus 310 transmits a first enable level before the mode control line 311 switches to an enable level, then the first gate line 21 maintains the first enable level when the mode control line 311 switches to an enable level. Conversely, if the gate drive bus 310 transmits a first disable level before the mode control line 311 switches to an enable level, then the first gate line 21 maintains the first disable level when the mode control line 311 switches to an enable level.

[0058] Figure 6 and Figure 7 This embodiment illustrates the use of an N-type transistor as the control transistor M3, with the enable level transmitted by the mode control line 311 being high and the disable level being low. Alternatively, in this embodiment, the control transistor M3 can be a P-type transistor, and correspondingly, the enable level transmitted by the mode control line 311 can be set to low and the disable level to high.

[0059] For example, the display panel also includes a driver chip (not shown), with a gate drive bus 310 and a mode control line 311 electrically connected to the driver chip to receive the first gate drive signal and the response signal of the control transistor M3 from the driver chip, respectively.

[0060] For example, such as Figure 5 As shown, in this embodiment of the invention, the first sub-pixel 101 and the second sub-pixel 102 can be connected to the same gate drive bus 310, and the two can be located in different sub-pixel rows 1, that is, the two can be connected to different second gate lines 22.

[0061] In this case, it is equivalent to making Figure 3 and Figure 4 The first gate drive signal GateV_101 and the first gate drive signal GateV_102 shown are provided by the same gate drive bus 310.

[0062] like Figure 8 and Figure 9 As shown, Figure 8 and Figure 9 These are timing diagrams for two different types of second gate lines connecting the first sub-pixel, second gate lines connecting the second sub-pixel, and gate driving buses provided in embodiments of the present invention. Figure 8 With the above Figure 3 Corresponding to, Figure 9 With the above Figure 4 Corresponding to, that is, based on Figure 8 The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 to satisfy f0:f1:f2=2:1:2. Based on Figure 9 The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 to satisfy f0:f1:f2=6:2:3.

[0063] Figure 8 and Figure 9 The second sub-pixel 102 is scanned after the first sub-pixel 101, that is, the second enable level of the second gate drive signal GateH_102 is located after the second enable level of the second gate drive signal GateH_101 as an illustration.

[0064] like Figure 8 and Figure 9 As shown, the first gate drive signal GateV provided by the gate drive bus 310 satisfies: During the first time period P1, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the gate drive bus 310 provides the first disable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the gate drive bus 310 provides the first enable level.

[0065] During the second time period P2, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the gate drive bus 310 provides the first enable level. When the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the gate drive bus 310 provides the first enable level, so that the first sub-pixel 101 writes data voltage during the second time period P2, and the second sub-pixel 102 writes data voltage during the second time period P2.

[0066] like Figure 9 As shown, during the third time period P3, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the gate drive bus 310 provides the first disable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the gate drive bus 310 provides the first disable level.

[0067] In the fourth time period P4, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the gate drive bus 310 provides the first enable level; when the second gate drive signal GateH_102 received by the second sub-pixel is at the second enable level, the gate drive bus 310 provides the first disable level.

[0068] Based on this configuration, by adjusting the signals transmitted by the gate drive bus 310 at different times, the data refresh frequencies of the first sub-pixel 101 and the second sub-pixel 102, which are electrically connected to the gate drive bus 310, can be differentiated.

[0069] For example, such as Figure 6 As shown, the display panel may include multiple subpixel columns 4, each subpixel column 4 including multiple subpixels 10 arranged along a first direction h1. Multiple subpixels 10 located in the same subpixel column 4 may be electrically connected to the same data line Data.

[0070] Optionally, in this embodiment of the invention, the first sub-pixel 101 and the second sub-pixel 102 may be located in the same sub-pixel column 4, or they may be located in different sub-pixel columns 4. Figure 5 and Figure 6 The diagram illustrates two possible positions for the second sub-pixel 102, representing two possible positional relationships between the first sub-pixel 101 and the second sub-pixel 102. In one case, the first sub-pixel 101 and the second sub-pixel 102 (shown by a solid line) are located in the same sub-pixel column 4 and are connected to the same data line (Data). In another case, the first sub-pixel 101 and the second sub-pixel 102 (shown by a dashed line) are located in different sub-pixel columns 4 and are connected to different data lines (Data).

[0071] For example, such as Figure 5 and Figure 6 As shown, the display area AA may include multiple first gate lines 21, and each first gate line 21 is electrically connected to at least one of the multiple sub-pixels 10 in a sub-pixel column 4. The first gate control circuit 31 includes a gate drive bus 310, which is electrically connected to multiple first gate drive lines 21. That is, in the first mode, different first gate lines 21 can receive the same signal.

[0072] It should be noted that, Figure 6 The arrangement of a control transistor M3 for each first gate line 21 is merely illustrative; however, a control transistor M3 may also be connected to at least two first gate lines 21.

[0073] For example, such as Figure 10 As shown, Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display area AA includes a first display area AA1 and a second display area AA2, which are arranged along a first direction h1. The first display area AA1 includes a plurality of first sub-pixels 101, and the data refresh rates of the plurality of first sub-pixels 101 are equal. The second display area AA2 includes a plurality of second sub-pixels 102, and the data refresh rates of the plurality of second sub-pixels 102 are equal.

[0074] like Figure 10As shown, the display area AA includes multiple first gate lines 21, which pass through the second display area AA2 and the first display area AA1.

[0075] Optional, such as Figure 10 As shown, display area AA includes n sub-pixel rows 1, which are labeled 1_1, 1_2, ..., 1_m, 1_m+1, ..., 1_n in top-down order. m and n are both positive integers, and m < n. The second display area AA2 includes the first sub-pixel row 1_1 to the m-th sub-pixel row 1_m, and the first display area AA1 includes the (m+1)-th sub-pixel row 1_m+1 to the n-th sub-pixel row 1_n.

[0076] like Figure 10 As shown, the first gate control circuit 31 includes a gate drive bus 310. In the first mode, the gate drive bus 310 is electrically connected to the first gate line 21 passing through the first display area AA1 and the second display area AA2.

[0077] When the display panel is working, in the first mode, such as Figure 11 and Figure 12 As shown, Figure 11 and Figure 12 The following are timing diagrams of the operation of the two display panels provided in the embodiments of the present invention in the first mode. Figure 11 With the above Figure 3 Corresponding to, Figure 12 With the above Figure 4 Corresponding to, that is, based on Figure 11 The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first display area AA1, and the data refresh frequency f2 of the second display area AA2 to satisfy f0:f1:f2=2:1:2. Based on Figure 12 The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first display area AA1, and the data refresh frequency f2 of the second display area AA2 to satisfy f0:f1:f2=6:2:3.

[0078] like Figure 11 and Figure 12 As shown, during the second time period P2, during the scanning of the entire display area AA, that is, from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the nth sub-pixel row 1_n providing the second enable level, the gate drive bus 310 provides the first enable level. During this process, each sub-pixel row 1 in the second display area AA2 and the first display area AA1 is written with data voltage sequentially according to the scanning order of the second gate line 22.

[0079] like Figure 11 and Figure 12 As shown, the first time period P1 includes a first sub-time period P11 and a second sub-time period P12. The first sub-time period P11 is the scanning period of the second display area AA2. That is, in the first sub-time period P11, the first sub-pixel row 1_1 to the m-th sub-pixel row 1_m are scanned sequentially. The second gate line 22_1 electrically connected to the first sub-pixel row 1_1 to the second gate line 22_m electrically connected to the m-th sub-pixel row 1_m are sequentially provided with a second enable level. The gate drive bus 310 provides a first enable level in the first sub-time period P11. In other words, in the first sub-time period P11, each sub-pixel row 1 in the second display area AA2 is written with data voltage sequentially according to the scanning order of the second gate line 22.

[0080] The second sub-segment P12 is the scanning period of the first display area AA1. Specifically, during the second sub-segment P12, the (m+1)th sub-pixel row 1_m+1 to the nth sub-pixel row 1_n are scanned sequentially. That is, the second gate line 22 electrically connected to the (m+1)th sub-pixel row 1_m+1 to the second gate line 22 electrically connected to the nth sub-pixel row 1_n sequentially provides a second enable level, and the gate drive bus 310 provides a first enable level during the second sub-segment P12. In other words, during the second sub-segment P12, each sub-pixel row 1 in the first display area AA1 stops writing data voltage, maintaining the data voltage written during the second sub-segment P2.

[0081] like Figure 12 As shown, during the third time period P3, during the scanning of the entire display area AA, that is, from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the nth sub-pixel row 1_n providing the second enable level, the gate drive bus 310 provides the first disable level. In other words, during this process, each sub-pixel row 1 in the second display area AA2 and the first display area AA1 stops writing data voltage.

[0082] like Figure 12 As shown, the fourth time period P4 includes the third sub-time period P41 and the fourth sub-time period P42. The third sub-time period P41 is the scanning period of the second display area AA2. That is, in the third sub-time period P41, the first sub-pixel row 1_1 to the m-th sub-pixel row 1_m are scanned sequentially. Specifically, the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 to the second gate line 22_m electrically connected to the m-th sub-pixel row 1_m are sequentially provided with a second enable level, and the gate drive bus 310 provides a first disable level in the third sub-time period P41. In other words, in the third sub-time period P41, the writing of data voltage in each sub-pixel row 1 of the second display area AA2 is stopped, and the data voltage written in the second time period P2 is maintained.

[0083] The fourth sub-segment P42 is the scanning period for the first display area AA1. Specifically, during the fourth sub-segment P42, sub-pixel rows 1_m+1 to 1_n are scanned sequentially. This means that the second gate line 22_m+1 electrically connected to the (m+1)th sub-pixel row 1_m+1 to the second gate line 22_n electrically connected to the 1_nth sub-pixel row 1_n sequentially provides a second enable level, and the gate drive bus 310 provides a first enable level during the fourth sub-segment P42. In other words, during the fourth sub-segment P42, each sub-pixel row 1 in the first display area AA1 is written with data voltage according to the scanning order of the second gate line 22.

[0084] For example, when driving the display panel, the first display area AA1, which has a lower data refresh rate, can be used to display text or static images to reduce the power consumption of the first display area AA1. The second display area AA2, which has a higher data refresh rate, can be used to display dynamic images such as animations or videos to improve the smoothness of the images displayed in the second display area AA2.

[0085] In this embodiment of the invention, the period TH of the signal on the gate drive bus 310 determines the operating period T of the display panel in the first mode. That is, in this embodiment of the invention, the operating period T of the display panel in the first mode can be adjusted by adjusting the period TH of the signal on the gate drive bus 310.

[0086] For example, the period TH of the signal on the gate drive bus 310 and the period T0 of the second gate drive signal GateH satisfy: TH=N×T0, where N is an integer and N≥2. Figure 11 Using N=2 as an example, Figure 12 Using N=6 as an example.

[0087] It should be noted that, Figure 3 and Figure 4 The second enable level of the second gate drive signal GateH_101 and the second enable level of the second gate drive signal GateH_102 shown are provided in a time-division manner as an illustration. In another optional embodiment, the second enable level of the second gate drive signal GateH_101 and the second enable level of the second gate drive signal GateH_102 may also be provided simultaneously, that is, the first sub-pixel 101 and the second sub-pixel 102 may be electrically connected to the same second gate line 22.

[0088] Optional, such as Figure 13 As shown, Figure 13 This is a schematic diagram of another display panel provided in an embodiment of the present invention, wherein the first sub-pixel 101 and the second sub-pixel 102 have different... Figure 10 Positional relationships, such as Figure 13 As shown, the same sub-pixel row 1 includes the first sub-pixel 101 and the second sub-pixel 102 with different frequencies; that is, the first sub-pixel 101 and the second sub-pixel 102 are electrically connected to the same second gate line 22 to receive the same second gate drive signal GateH.

[0089] In this embodiment of the invention, the first gate control circuit 31 includes at least two gate drive buses 310. Figure 13 The first gate control circuit 31 includes two gate drive buses, which are labeled 310_1 and 310_2 respectively. In the first mode, one gate drive bus 310_1 is electrically connected to the first sub-pixel 101, and the other gate drive bus 310_2 is electrically connected to the second sub-pixel 102.

[0090] In this embodiment of the invention, by electrically connecting the first sub-pixel 101 and the second sub-pixel 102 located in the same sub-pixel row 1 to different gate drive buses 310 and by differentiating the signals on the different gate drive buses 310, the data refresh frequency of the first sub-pixel 101 and the second sub-pixel 102 located in the same sub-pixel row 1 can be differentiated.

[0091] For example, when the display panel is working, in the first mode, such as Figure 14 and Figure 15 As shown, Figure 14 and Figure 15 The following is a timing diagram illustrating two methods for providing second gate drive signals to a first sub-pixel and a second sub-pixel, a gate drive bus connecting the first sub-pixel, and a gate drive bus connecting the second sub-pixel, as provided in embodiments of the present invention. Figure 14 and Figure 15 GateH_101 and GateH_102 in the text represent Figure 13 The second gate drive signal received by the first sub-pixel 101 and the second sub-pixel 102 located in one of the sub-pixel rows 1. Figure 14 With the above Figure 3 Corresponding to, Figure 15 With the above Figure 4 Corresponding to, that is, based on Figure 14 The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 to satisfy f0:f1:f2=2:1:2. Based on Figure 15The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 to satisfy f0:f1:f2=6:2:3.

[0092] like Figure 14 and Figure 15 As shown, the first gate drive signal provided by the gate drive bus 310 satisfies: During the first time period P1, when the second gate drive signal GateH_101 received by the first sub-pixel 101 and the second gate drive signal GateH_102 received by the second sub-pixel 102 are at the second enable level, the gate drive bus 310_1 provides a first disable level so that the gate drive bus 310_1 controls the first sub-pixel 101 to stop writing data voltage during the first time period P1. The gate drive bus 310_2 provides a first enable level so that the gate drive bus 310_2 controls the second sub-pixel 102 to write data voltage during the second time period P2.

[0093] During the second time period P2, when the second gate drive signal GateH_101 received by the first sub-pixel 101 and the second gate drive signal GateH_102 received by the second sub-pixel 102 are at the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide the first enable level, so that the gate drive bus 310_1 controls the first sub-pixel 101 to write data voltage during the second time period P2, and the gate drive bus 310_2 controls the second sub-pixel 102 to write data voltage during the second time period P2.

[0094] For example, such as Figure 15 As shown, the working cycle T of the display panel includes at least the aforementioned third time period P3 and fourth time period P4. During the third time period P3, when the second gate drive signal GateH_101 received by the first sub-pixel 101 and the second gate drive signal GateH_102 received by the second sub-pixel 102 are at the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide a first disable level. This causes the gate drive bus 310 to control the first sub-pixel 101 to stop writing data voltage during the third time period P3, and the gate drive bus 310_2 to control the second sub-pixel 102 to stop writing data voltage during the third time period P3.

[0095] During the fourth time period P4, when the second gate drive signal GateH_101 received by the first sub-pixel 101 and the second gate drive signal GateH_102 received by the second sub-pixel 102 are at the second enable level, the gate drive bus 310_1 provides a first enable level to control the first sub-pixel 101 to write data voltage during the fourth time period P4. The gate drive bus 310_2 provides a first disable level to control the second sub-pixel 102 to stop writing data voltage during the fourth time period P4.

[0096] In this embodiment of the invention, the period TH1 of the signal on the gate driving bus 310_1, which is electrically connected to the first sub-pixel 101, determines the operating period of the first sub-pixel 101 in the first mode. That is, in this embodiment of the invention, the operating period of the first sub-pixel 101 in the first mode can be adjusted by adjusting the period TH1 of the signal on the gate driving bus 310_1.

[0097] For example, in this embodiment of the invention, TH1 ≥ N1 × T0. Wherein, T0 is the period of the second gate drive signal GateH; N1 is an integer.

[0098] Optionally, in this embodiment of the invention, TH1 can be set to N1 × T0, that is, the time interval between two adjacent identical pulses in the first gate driving signal GateV received by the first sub-pixel 101 is N1 × T0. Based on this setting, the data refresh frequencies of the multiple first sub-pixels 101 connected to the gate driving bus 310_1 can be made equal. For example, the data refresh frequencies f1 of the multiple first sub-pixels 101 and the frequency f0 of the second gate driving signal GateH can be made to satisfy f0:f1 = N1:1. Figure 14 Using TH1=2T0 as an example, Figure 15 Using TH1=3T0 as an example.

[0099] Alternatively, in this embodiment of the invention, TH1 > N1 × T0 can be set so that the data refresh frequencies of at least two first sub-pixels 101 connected to the gate drive bus 310_1 are not equal.

[0100] like Figure 14 As shown, the first gate drive signal GateV provided by the second gate drive bus 310_2 can be kept constant at the first enable level. Based on this setting, the data refresh frequency f2 of the second sub-pixel can be made to match the frequency f0 of the second gate drive signal GateH. For example, when the frequency f0 of the second gate drive signal GateH is 60Hz, based on this setting, the data refresh frequency f2 of the second sub-pixel 102 can be made to be 60Hz.

[0101] Or, such as Figure 15As shown, in this embodiment of the invention, the signal transmitted by the gate drive bus 310_2 can also be a periodic pulse signal that can switch between a first enable level and a first disable level. Based on this setting, while making the data refresh frequency of the first sub-pixel 101 less than the data refresh frequency of the second sub-pixel 102, the data refresh frequency of the second sub-pixel 102 can also be made less than the frequency of the second gate drive signal GateH.

[0102] When the gate drive bus 310_2 transmits a pulse signal, the period TH2 of the signal on the gate drive bus 310_2, which is electrically connected to the second sub-pixel 102, determines the operating period of the second sub-pixel 102 in the first mode. That is, in this embodiment of the invention, the operating period of the second sub-pixel 102 in the first mode can be adjusted by adjusting the period TH2 of the signal on the gate drive bus 310_2.

[0103] For example, in an embodiment of the present invention, TH2≥N2×T0; N2 is an integer, and N2<N1.

[0104] Optionally, in this embodiment of the invention, TH2 can be set to N2 × T0, that is, the time interval between two adjacent identical pulses in the first gate driving signal GateV received by the second sub-pixel 102 is N2 × T0. Based on this setting, the data refresh frequencies of the multiple second sub-pixels 102 connected to the gate driving bus 310_2 can be made equal. For example, the data refresh frequencies f2 of the multiple second sub-pixels 102 and the frequency f0 of the second gate driving signal GateH can be made to satisfy f0:f2 = N2:1. Figure 15 The example uses TH1=3T0 and TH2=2T0.

[0105] Alternatively, in this embodiment of the invention, TH2 > N2 × T0 can be set so that the data refresh frequencies of at least two second sub-pixels 102 connected to the gate drive bus 310_2 are not equal.

[0106] In another alternative implementation, such as Figure 13 As shown, the display area AA includes a first display area AA1 and a second display area AA2, which are arranged along the second direction h2. The first display area AA1 includes a plurality of first sub-pixels 101, and the data refresh rates of the plurality of first sub-pixels 101 are equal. The second display area AA2 includes a plurality of second sub-pixels 102, and the data refresh rates of the plurality of second sub-pixels 102 are equal.

[0107] like Figure 13As shown, the display area AA includes multiple first gate lines 21. Some of the first gate lines 21 are located in the first display area AA1 and are electrically connected to multiple first sub-pixels 101 in the first display area AA1. Another portion of the first gate lines 21 are located in the second display area AA2 and are electrically connected to multiple second sub-pixels 102 in the second display area AA2.

[0108] Optional, such as Figure 13 As shown, display area AA includes r subpixel columns 4, and subpixel columns 4 include multiple subpixels 10 arranged along the first direction h1. From left to right, the r subpixel columns 4 are sequentially labeled 4_1, 4_2, ..., 4_s, 4_s+1, ..., 4_r. First display area AA1 includes the first subpixel column 4_1 to the s-th subpixel row 4_s, and second display area AA2 includes the (s+1)-th subpixel column 4_s+1 to the r-th subpixel column 4_r.

[0109] The first gate control circuit 31 includes a gate drive bus 310_1 and a gate drive bus 310_2. In a first mode, the gate drive bus 310_1 is electrically connected to multiple first gate lines 21 in the first display area AA1. The gate drive bus 310_2 is electrically connected to multiple first gate lines 21 in the second display area AA2.

[0110] When the display panel is working, in the first mode, such as Figure 16 and Figure 17 As shown, Figure 15 and Figure 16 for Figure 13 The display panel shown is illustrated with two timing diagrams for operation in the first mode. Figure 16 With the above Figure 3 Corresponding to, in Figure 16 In the above, N1=2, and the first gate drive signal GateV provided by the gate drive bus 310_2 is set to a constant signal. Figure 17 With the above Figure 4 Corresponding to, in Figure 17 In this case, N1=3, the first gate drive signal GateV provided by the gate drive bus 310_2 is a pulse signal, and its period TH2 and the period T0 of the second gate drive signal GateH satisfy: TH2=2T0. That is, N2=2.

[0111] based on Figure 16 The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first display area AA1, and the data refresh frequency f2 of the second display area AA2 to satisfy f0:f1:f2=2:1:2.

[0112] based on Figure 17The method shown allows the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first display area AA1, and the data refresh frequency f2 of the second display area AA2 to satisfy f0:f1:f2=6:2:3.

[0113] like Figure 16 and Figure 17 As shown, during the second time period P2, during the scanning of the entire display area AA, that is, from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the nth sub-pixel row 1_n providing the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide the first enable level. During this process, each sub-pixel row 1 in the second display area AA2 and the first display area AA1 is written with data voltage sequentially according to the scanning order of the second gate line 22.

[0114] During the first time period P1, while scanning the entire display area AA, that is, from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the nth sub-pixel row 1_n providing the second enable level, the gate drive bus 310_1 provides the first disable level, and the gate drive bus 310_2 provides the first enable level. In other words, during the first time period P1, each sub-pixel row 1 in the first display area AA1 stops writing data voltage, and each sub-pixel row 1 in the second display area AA2 sequentially writes data voltage according to the scanning order of the second gate line 22.

[0115] like Figure 17 As shown, the working cycle T of the display panel includes at least the aforementioned third time period P3 and fourth time period P4.

[0116] During the third time period P3, while scanning from the first sub-pixel row 1_1 to the last sub-pixel row, i.e., the nth sub-pixel row 1_n, that is, while the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 provides the second enable level to the second gate line 22_n electrically connected to the nth sub-pixel row 1_n provides the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide the first disable level. During this process, each sub-pixel row 1 in the first display area AA1 and the second display area AA2 stops writing data voltage.

[0117] During the fourth time period P4, during the scanning of the first sub-pixel row 1_1 to the last sub-pixel row, i.e., the nth sub-pixel row 1_n, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the process from the second gate line 22_n electrically connected to the nth sub-pixel row 1_n providing the second enable level, the gate drive bus 310_1 provides the first enable level, and the gate drive bus 310_2 provides the first disable level. During this process, each sub-pixel row 1 in the first display area AA1 performs data voltage writing. Data voltage writing stops in each sub-pixel row 1 in the second display area AA2.

[0118] For example, when driving the display panel, the first display area AA1, which has a lower data refresh rate, can be used to display text or static images to reduce the power consumption of the first display area AA1. The second display area AA2, which has a higher data refresh rate, can be used to display dynamic images such as animations or videos to improve the smoothness of the images displayed in the second display area AA2.

[0119] In yet another alternative implementation, such as Figure 18 As shown, Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display area AA includes a first display area AA1 and a second display area AA2, with the first display area AA1 surrounding the second display area AA2.

[0120] For example, such as Figure 18 As shown, the first display area AA1 includes a first sub-display area AA11, a second sub-display area AA12, a third sub-display area AA13, and a fourth sub-display area AA14. Specifically, along the first direction h1, the second sub-display area AA12 and the third sub-display area AA13 are located on either side of the second display area AA2. Along the second direction h2, the first sub-display area AA11 and the fourth sub-display area AA14 are located on either side of the second display area AA2.

[0121] like Figure 18 As shown, the display area AA includes multiple first gate lines 21. Some of the first gate lines 21 are located in the first display area AA1 and are electrically connected to multiple first sub-pixels 101 in the first display area AA1. Some of the first gate lines 21 extend through the first display area AA1 and the second display area AA2.

[0122] Optionally, the subpixels in the display area AA are arranged in n rows and r columns, that is, the display area AA includes n subpixel rows and r subpixel columns. For the sake of simplicity in the illustration, Figure 18 Sub-pixels are not shown.

[0123] From left to right, the first sub-display area AA11 includes the first sub-pixel column to the xth sub-pixel column; the second sub-display areas AA12, AA2, and AA13 each include the (x+1)th to the yth sub-pixel column; and the fourth sub-display area AA14 includes the (y+1)th to the rth sub-pixel column.

[0124] The first sub-pixel column, the x-th sub-pixel column, the (x+1)-th sub-pixel column, the y-th sub-pixel column, the (y+1)-th sub-pixel column, and the r-th sub-pixel column are respectively connected to... Figure 18 The first gate line 21_1, the xth gate line 21_x, the (x+1)th gate line 21_x+1, the first gate line 21_y, the (y+1)th gate line 21_y+1, and the rth gate line 21_r shown are electrically connected.

[0125] In top-down order, the second sub-display area AA12 includes the portion from the first sub-pixel row to the u-th sub-pixel row, the second display area AA2 includes the portion from the (u+1)-th sub-pixel row to the v-th sub-pixel row, and the third sub-display area AA13 includes the portion from the (v+1)-th sub-pixel row to the n-th sub-pixel row.

[0126] The first sub-pixel row, the u-th sub-pixel row, the (u+1)-th sub-pixel row, the v-th sub-pixel row, the (v+1)-th sub-pixel row, and the n-th sub-pixel row are respectively connected to... Figure 18 The first second gate line 22_1, the uth second gate line 22_u, the u+1th second gate line 22_u+1, the vth second gate line 22_v, the v+1th second gate line 22_v+1, and the nth second gate line 22_n are electrically connected accordingly.

[0127] The first gate control circuit 31 includes at least two gate drive buses. Figure 18 Taking the first gate control circuit 31, which includes gate drive bus 310_1 and gate drive bus 310_2, as an example, in the first mode, gate drive bus 310_1 is electrically connected to multiple first gate lines 21 in the first sub-display area AA11 and the fourth sub-display area AA14. Gate drive bus 310_2 is electrically connected to the first gate lines 21 passing through the second sub-display area AA12, the second display area AA2, and the third sub-display area AA13.

[0128] When the display panel is working, in the first mode, such as Figure 19 As shown, Figure 19 for Figure 18 The diagram shown is a timing diagram of the display panel in one of the first modes. During the second time period P2, during the scanning process from the first sub-pixel row to the nth sub-pixel row, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row providing the second enable level to the second gate line 22_n electrically connected to the nth sub-pixel row providing the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide the first enable level. During this process, each sub-pixel row in the second display area AA2 and the first display area AA1 is sequentially written with data voltage according to the scanning order of the second gate line 22.

[0129] like Figure 19 As shown, the first time period P1 includes a first sub-time period P11, a second sub-time period P12, and a third sub-time period P13. The first sub-time period P11 is the scanning period for the first sub-pixel row to the u-th sub-pixel row of the first sub-display area AA11 and the fourth sub-display area AA14, and the second sub-display area AA12. That is, in the first sub-time period P11, the first sub-pixel row to the u-th sub-pixel row are scanned sequentially. Specifically, the second gate line 22_1 electrically connected to the first sub-pixel row to the second gate line 22_u electrically connected to the u-th sub-pixel row are sequentially provided with a second enable level, and the gate drive bus 310_2 provides a first disable level in the first sub-time period P11. In other words, in the first sub-time period P11, the writing of data voltage to each sub-pixel row in the second sub-display area AA12 is stopped.

[0130] The second sub-period P12 is the scanning period for the (u+1)th to the vth sub-pixel rows of the first sub-display area AA11 and the fourth sub-display area AA14, and the second display area AA2. Specifically, during the second sub-period P12, the (u+1)th to the vth sub-pixel rows are scanned sequentially. This means that the second gate line 22_u+1, electrically connected to the (u+1)th sub-pixel row, to the second gate line 22_v, electrically connected to the vth sub-pixel row, sequentially provides a second enable level, and the gate drive bus 310_2 provides a first enable level during the second sub-period P12. In other words, during the second sub-period P12, each sub-pixel row in the second display area AA2 is written with data voltage according to the scanning order of the second gate line 22.

[0131] The third sub-period P13 is the scanning period for the (v+1)th to the nth sub-pixel rows of the first sub-display area AA11 and the fourth sub-display area AA14, as well as the third sub-display area AA13. Specifically, during the third sub-period P13, the (v+1)th to the nth sub-pixel rows are scanned sequentially. This means that the second gate line 22_v+1 electrically connected to the (v+1)th sub-pixel row, to the second gate line 22_n electrically connected to the nth sub-pixel row, sequentially provides a second enable level, and the gate drive bus 310_2 provides a first disable level during the third sub-period P13. In other words, during the third sub-period P13, the writing of data voltage to each sub-pixel row in the third sub-display area AA13 is stopped.

[0132] During the first sub-period P11, the second sub-period P12, and the third sub-period P13, the gate drive bus 310_1 provides a first disabled level. That is, during the first sub-period P11, the second sub-period P12, and the third sub-period P13, the writing of data voltages to each sub-pixel row in the first sub-display area AA11 and the fourth sub-display area AA14 is stopped.

[0133] The work described above for the second time period P2 and the first time period P1 can then be repeated. Based on this setting, the data refresh rate of the first display area AA1 can be lower than the data refresh rate of the second display area AA2.

[0134] For example, such as Figure 18 As shown, in this embodiment of the invention, the sub-pixels in the first sub-display area AA11 and the fourth sub-display area AA14 are all connected to the gate drive signal line 310_1. The sub-pixels in the second sub-display area AA12, the second display area AA2, and the fourth sub-display area AA14 are all connected to the gate drive signal line 310_2.

[0135] Or, such as Figure 20 As shown, Figure 20 This is a schematic diagram of another display panel provided by an embodiment of the present invention. In this embodiment of the present invention, the gate driving bus 310_1 and the gate driving bus 310_2 can also be split into two signal lines. For example, the gate driving bus 310_1 can be split into the gate driving bus 310_11 and the gate driving bus 310_12, and the gate driving bus 310_2 can be split into the gate driving bus 310_21 and the gate driving bus 310_22.

[0136] Combination Figure 20 and Figure 21 As shown, Figure 21 for Figure 20The diagram shown is a timing diagram of the display panel in one mode. The timing of gate drive buses 310_11 and 310_12 is the same, and the timing of gate drive buses 310_21 and 310_22 is also the same. like Figure 20 As shown, gate drive bus 310_11 is electrically connected to the first gate line 21 in the first sub-display area AA11, and gate drive bus 310_12 is electrically connected to the first gate line 21 in the fourth sub-display area AA14. Gate drive bus 310_21 is electrically connected to a portion of the first gate line 21 passing through the second sub-display area AA12, the second sub-display area AA2, and the fourth sub-display area AA14, and gate drive bus 310_22 is electrically connected to another portion of the first gate line 21 passing through the second sub-display area AA12, the second sub-display area AA2, and the fourth sub-display area AA14.

[0137] Based on this configuration, the number of sub-pixels connected to a gate drive bus 310 can be reduced, which helps to reduce the load on a gate drive bus 310.

[0138] In another alternative embodiment, the number of gate drive buses 310 may be the same as the number of sub-pixel columns in the display area AA. For example... Figure 22 As shown, Figure 22 This is a schematic diagram of another display panel provided by an embodiment of the present invention. In this embodiment, the first gate control circuit may include r first gate driving buses, and the r first gate driving buses 310 are electrically connected to r sub-pixel columns in a one-to-one correspondence. For the sake of simplicity in the illustration, Figure 22 The sub-pixel column is not shown; instead, a first gate line 21 electrically connected to the sub-pixel column is shown.

[0139] Based on this configuration, the first gate drive signals provided to different sub-pixel columns can be made independent of each other, enabling differentiated frequency settings for each sub-pixel column. In other words, a sub-pixel column can be treated as a minimum frequency unit, facilitating fine-tuning of the frequency division areas in the display panel.

[0140] For example, combining Figure 22 and Figure 23 As shown, Figure 23 for Figure 22 The diagram shown illustrates a timing diagram of the display panel in a first mode, where the timings of gate drive buses 310_1 and 310_2 are different, while the timings of gate drive buses 310_2 to 310_r are the same. Based on this configuration, the data refresh rate of the sub-pixels in rows u+1 to v of the sub-pixel column electrically connected to gate drive bus 310_1 can be twice that of the other sub-pixels.

[0141] For example, such as Figure 24 As shown, Figure 24 This is a schematic diagram of another first gate control circuit provided in an embodiment of the present invention. The control transistor M3 includes a first control transistor M31 and a second control transistor M32, and the mode control signal line 311 includes a first signal line 3111 and a second signal line 3112.

[0142] In this configuration, the gate of the first control transistor M31 is electrically connected to the first signal line 3111, and the gate of the second control transistor M32 is electrically connected to the second signal line 3112. The first terminals of both the first and second control transistors are electrically connected to the gate drive bus 310 to receive the first gate drive signal GateV. The second terminals of both the first and second control transistors are electrically connected to the first gate line 21.

[0143] In an embodiment of the invention, in a first mode, the first signal line 3111 and the second signal line 3112 provide signals that turn on the first control transistor M31 and the second control transistor M32 in a time-division manner.

[0144] like Figure 25 As shown, Figure 25 The following is a driving timing diagram of a display panel in a first mode provided by an embodiment of the present invention. In the first mode, the signals provided by the first signal line 3111 and the second signal line 3112 are signals that alternate between enable level and non-enable level.

[0145] In the first mode, during the second time period P2, the first signal line 3111 provides a signal to turn on the first control transistor M31. When the first control transistor M31 is turned on, the signal on the gate drive bus 310 is written to the first gate line 21 through the first control transistor M31. The second signal line 3112 provides a signal to turn off the second control transistor M32. During the first time period P1, the second signal line 3112 provides a signal to turn on the second control transistor M32. When the second control transistor M32 is turned on, the signal on the gate drive bus 310 is written to the first gate line 21 through the second control transistor M32. The first signal line 3111 provides a signal to turn off the first control transistor M31.

[0146] It can be seen that at any given time in the first mode, at most one of the first control transistor M31 and the second control transistor M32 is turned on. Based on this setting, in the first mode, the first control transistor M31 and the second control transistor M32 can be controlled to conduct in a time-sharing manner, which can avoid the first control transistor M31 or the second control transistor M32 being turned on for a long time, thus improving the operational reliability of the first control transistor M31 or the second control transistor M32.

[0147] Figure 24 Therefore, the first control transistor M31 and the second control transistor M32 are set as N-type transistors for illustration. Accordingly, Figure 25 The diagram illustrates the use of a high level transmitted via the first signal line 3111 and the second signal line 3112 as the enable level and a low level as the disable level. Alternatively, the first control transistor M31 or the second control transistor M32 can be configured as a P-type transistor, which is not illustrated in the accompanying diagram.

[0148] Furthermore, it is understandable that Figure 24 The illustration shows multiple first gate lines 21 connected to the same gate drive bus 310. Alternatively, at least two first gate lines 21 can be connected to different gate drive buses 310. This illustration will not be shown in the attached diagram.

[0149] Optional, such as Figure 26 As shown, Figure 26 This is a schematic diagram of another display panel provided in an embodiment of the present invention. A first gate line 21 is electrically connected to at least two sub-pixels 10 in the same sub-pixel row 1. Based on this arrangement, a first gate drive signal GateV can be shared by at least two sub-pixels 10 in the same sub-pixel row 1.

[0150] When the display panel is operating, at least two sub-pixels 10 sharing the same first gate drive signal GateV have the same data refresh frequency, that is, they can serve as a minimum refresh unit in the display panel. For example, Figure 26 As illustrated, three adjacent sub-pixels 10 are connected to the same first gate line 21. In this case, three adjacent sub-pixels 10 in the same sub-pixel row 1 can serve as a minimum refresh unit in the display panel. Figure 26 As shown, these three sub-pixels 10 are connected to different data lines Data.

[0151] For example, such as Figure 26 and Figure 27 As shown, Figure 27 This is a wiring diagram of a display panel provided in an embodiment of the present invention. At least a portion of the first gate line 21 extends along a first direction h1; at least a portion of the second gate line 22 extends along a second direction h2.

[0152] The display panel also includes a gate connection line 5, which electrically connects the first gate line 21 and at least two sub-pixels 10 in the same sub-pixel row 1; specifically, it connects the gate of the first transistor M1 to at least two sub-pixels 10 in the same sub-pixel row 1.

[0153] Optional, such as Figure 26 and Figure 27 As shown, at least a portion of the gate connection line 5 extends along the second direction h2. At least a portion of the second gate line 22 extends along the second direction h2.

[0154] The setting of gate connection line 5 can reduce the number of first gate lines 21 while enabling at least two sub-pixels 10 to have the same data refresh frequency drive, which is beneficial to reduce the distance between two adjacent sub-pixels 10 in the second direction h2.

[0155] For example, such as Figure 27 As shown, the plurality of sub-pixels 10 includes at least a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B arranged along the second direction h2; at least a portion of the orthographic projection of the first gate line 21 onto the plane of the display panel is located on the side of the orthographic projection of the blue sub-pixel B onto the plane of the display panel that is away from the orthographic projection of the green sub-pixel G onto the plane of the display panel. When the display panel is configured as a liquid crystal display panel, the liquid crystal display panel also includes a plurality of color resists with different colors. For example, the color resists include a red color resist corresponding to the red sub-pixel R, a green color resist corresponding to the green sub-pixel G, and a blue color resist corresponding to the blue sub-pixel B. Compared with the red and green color resists, the blue color resist has a higher transmittance. Therefore, in order to balance the transmittance of the sub-pixels of different colors, it is usually necessary to set the aperture ratio of the red and green sub-pixels to be larger. In this embodiment of the invention, by setting at least a portion of the orthogonal projection of the first gate line 21 onto the plane where the display panel is located to be on the side where the orthogonal projection of the blue sub-pixel B onto the plane where the display panel is located is far from the orthogonal projection of the green sub-pixel G onto the plane where the display panel is located, the setting of the first gate line 21 can avoid affecting the aperture ratio of the red sub-pixel R and the green sub-pixel B.

[0156] For example, such as Figure 27 As shown, the display panel also includes a black matrix 6, the orthographic projection of which at least partially covers the first gate line 21, the second gate line 22, the gate connection line 5, and the data line Data on the plane of the display panel.

[0157] When setting subpixel 10, for example, such as Figure 2As shown, in this embodiment of the invention, the first electrode of the second transistor M2 can be electrically connected to the data line Data, and the second electrode of the second transistor M2 can be electrically connected to the first electrode of the first transistor M1; the second electrode of the first transistor M1 can be electrically connected to the first plate of the storage capacitor Cst.

[0158] When the display panel is in use, the second transistor M2 of sub-pixel 10 can be turned on according to the frequency of the second gate drive signal GateH. In this embodiment of the invention, by electrically connecting the first transistor M1 to the data line Data through the second transistor M2, that is, by writing the data voltage provided by the data line Data to the storage capacitor Cst in the order of first passing through the second transistor M2 and then through the first transistor M1, the data voltage provided by the data line Data can be written to the second electrode of the second transistor M2 at a relatively high frequency. Since the second electrode of the second transistor M2 is connected to the first transistor M1, it avoids situations where there is no data voltage written for a long time at the connection node of the first transistor M1 and the second transistor M2. Therefore, during the period when the first transistor M1 is off, the potential of the first electrode of the first transistor M1 can still be refreshed at a certain frequency, thereby improving the potential stability of the first plate of the storage capacitor Cst electrically connected to the first transistor M1 and improving the brightness stability of sub-pixels with lower data refresh rates.

[0159] Or, such as Figure 28 As shown, Figure 28 This is an equivalent circuit diagram of another sub-pixel provided in an embodiment of the present invention. In this embodiment of the present invention, the first electrode of the first transistor M1 can be electrically connected to the data line Data, the second electrode of the first transistor M1 can be electrically connected to the first electrode of the second transistor M2, and the second electrode of the second transistor M2 can be electrically connected to the first plate of the storage capacitor Cst.

[0160] For example, such as Figure 29 As shown, Figure 29 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The non-display area NA includes a first non-display area NA1 and a second non-display area NA2. The first non-display area NA1 and the display area AA are arranged along a first direction h1, and the second non-display area NA2 and the display area AA are arranged along a second direction h2. like Figure 29 As shown, the second non-display area NA2 includes a second gate control circuit 32, which includes multiple cascaded gate control units 320. The gate control units 320 are electrically connected to the second gate line 22 and are used to provide the second gate drive signal GateH to the second gate line 22.

[0161] For example, such as Figure 29As shown, the first non-display area NA1 includes at least a portion of the first gate control circuit 31; for example, the first non-display area NA1 includes Figure 24 The first control transistor M31, the second control transistor M32, the first signal line 3111, the second signal line 3112, and the gate drive bus 310 shown are one or more of these. Based on this arrangement, the first gate control circuit 31 and the second gate control circuit 32 can be distributed, which can avoid the display panel having an excessively wide single-sided bezel.

[0162] Or, such as Figure 30 As shown, Figure 30 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The second non-display area NA2 includes at least a portion of the first gate control circuit 31. For example, the second non-display area NA2 includes... Figure 24 The first control transistor M31, the second control transistor M32, the first signal line 3111, the second signal line 3112, and the gate drive bus 310 shown are one or more of these.

[0163] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel, such as... Figure 1 As shown, the display panel includes multiple data lines Data and multiple sub-pixel rows 1 arranged along a first direction h1. Each sub-pixel row 1 includes multiple sub-pixels 10 arranged along a second direction h2. The first direction h1 and the second direction h2 intersect.

[0164] like Figure 2 As shown, sub-pixel 10 includes a first transistor M1, a second transistor M2, and a storage capacitor Cst; wherein, the first transistor M1 and the second transistor M2 are connected in series between the data line Data and the storage capacitor Cst, the gate of the first transistor M1 receives a first gate drive signal GateV, and the gate of the second transistor M2 receives a second gate drive signal GateH.

[0165] In this embodiment of the invention, the operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel 101 and a second sub-pixel 102, and the operating cycle of the display panel includes at least a first time period. Figure 3 and Figure 4 As shown, in the first mode, the driving method for the display panel includes: During the first time period P1, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is controlled to be at the first disable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is controlled to be at the first enable level.

[0166] The first enable level refers to the level that controls the first transistor M1 to turn on, the first disable level refers to the level that controls the first transistor M1 to turn off, and the second enable level refers to the level that controls the second transistor M2 to turn on.

[0167] The display panel driving method provided in this embodiment of the invention includes a first transistor M1 and a second transistor M2 in the sub-pixel 10, so that whether the data voltage Vdata provided by the data line Data is written to the storage capacitor Cst, that is, whether the sub-pixel 10 is charged or not can be jointly determined by the second gate driving signal GateH and the first gate driving signal GateV.

[0168] Based on this, embodiments of the present invention can make the working mode of the display panel include a first mode. In the first mode, the display panel includes at least a first sub-pixel 101 and a second sub-pixel 102. The working cycle T1 of the display panel includes at least a first time period P1. In the first time period P1, under the control of the first gate driving signal GateV_101, the data voltage write path of the first sub-pixel 101 is turned off, and under the control of the first gate driving signal GateV_102, the data voltage write path of the second sub-pixel 102 is turned on. This allows the data refresh frequency of the first sub-pixel 101 to be lower than the frequency of the second gate driving signal GateH in the first mode. That is, the data refresh frequency of the first sub-pixel 101 can be lower than the data refresh frequency of the second sub-pixel 102, realizing a differentiated design of the data refresh frequency of the first sub-pixel 101 and the data refresh frequency of the second sub-pixel 102.

[0169] Moreover, based on the method provided by the embodiments of the present invention, the data refresh frequency of the first sub-pixel 101 can be lower than the frequency of the second gate driving signal GateH. That is, without changing the frequency of the second gate driving signal GateH, at least the frequency reduction driving of the first sub-pixel 101 can be achieved by designing the timing of the first gate driving signal GateV_1 received by the first sub-pixel 101.

[0170] like Figure 1 and Figure 2As shown, the display panel also includes a first gate line 21 and a second gate line 22. The first gate line 21 provides the first gate drive signal GateV, and the second gate line 22 provides the second gate drive signal GateH.

[0171] In one alternative implementation, such as Figure 5 As shown, the first gate control circuit 31 includes a gate drive bus 310, which connects the first sub-pixel 101 and the second sub-pixel 102.

[0172] like Figure 5 As shown, the first sub-pixel 101 and the second sub-pixel 102 are connected to different second gate lines 22.

[0173] Combination Figure 8 and Figure 9 As shown, the method for controlling the first gate drive signal GateV_101 received by the first sub-pixel 101 to be at a first disabled level; and controlling the first gate drive signal GateV_102 received by the second sub-pixel 102 to be at a first enabled level includes: When the second gate drive signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the control gate drive bus 310 provides the first enable level; When the second gate drive signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the control gate drive bus 310 provides the first disable level; Based on this configuration, by adjusting the signals transmitted by the gate drive bus 310 at different times, the data refresh frequencies of the first sub-pixel 101 and the second sub-pixel 102, which are electrically connected to the gate drive bus 310, can be differentiated.

[0174] Optional, such as Figure 13 As shown, the same sub-pixel row 1 includes a first sub-pixel 101 and a second sub-pixel 102; that is, the first sub-pixel 101 and the second sub-pixel 102 are electrically connected to the same second gate line 22 to receive the same second gate drive signal GateH.

[0175] The first gate control circuit 31 includes at least two gate drive buses 310. In the first mode, one gate drive bus 310_1 is electrically connected to the first sub-pixel 101, and the other gate drive bus 310_2 is electrically connected to the second sub-pixel 102.

[0176] Optional, combined Figure 14 and Figure 15As shown, the method for controlling the first gate drive signal GateV_101 received by the first sub-pixel 101 to be at a first disabled level; and controlling the first gate drive signal GateV_102 received by the second sub-pixel 102 to be at a first enabled level includes: When the second gate drive signal GateH received by the first sub-pixel 101 and the second sub-pixel 102 is at the second enable level, the gate drive bus 310_1 is controlled to provide a first disable level so that the first gate drive signal GateV_101 received by the first sub-pixel 101 is at the first disable level, stopping the writing of data voltage to the first sub-pixel 101. Conversely, the gate drive bus 310_2 is controlled to provide a first enable level so that the first gate drive signal GateV_102 received by the second sub-pixel 102 is at the first enable level, enabling the writing of data voltage to the second sub-pixel 102.

[0177] For example, such as Figure 14 As shown, the gate drive bus 310_2 can provide a constant first enable level. Alternatively, as... Figure 15 As shown, both gate drive bus 310_1 and gate drive bus 310_2 can provide periodic pulse signals. The period TH1 of the signal on gate drive bus 310_1 satisfies TH1=N1×T0, and the period TH2 of the signal on gate drive bus 310_2 satisfies TH2=N2×T0. N1 and N2 are integers, and 1<N2<N1.

[0178] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 31 As shown, Figure 31 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 31 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, in-vehicle display screen or television.

[0179] As can be seen from the above embodiments, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects: The display panel provided by this invention includes multiple data lines and multiple sub-pixel rows arranged along a first direction. Each sub-pixel row includes multiple sub-pixels arranged along a second direction, and the first and second directions intersect. Each sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The first transistor and the second transistor are connected in series between the data lines and the storage capacitor. The gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal. The operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. The operating cycle of the display panel includes at least a first time period. In the first time period, when the second gate drive signal received by the first sub-pixel is at a second enable level, the first gate drive signal received by the first sub-pixel is at a first disable level. When the second gate drive signal received by the second sub-pixel is at a second enable level, the first gate drive signal received by the second sub-pixel is at a first enable level. The first enable level refers to the level that controls the first transistor to be turned on, the first disable level refers to the level that controls the first transistor to be turned off, and the second enable level refers to the level that controls the second transistor to be turned on. The sub-pixel provided by this invention includes a first transistor, a second transistor, and a storage capacitor. The first and second transistors are connected in series between a data line and the storage capacitor, allowing the charging of the sub-pixel to be jointly determined by a second gate driving signal and a first gate driving signal. The display panel of this invention has a first operating mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel, and the operating cycle of the display panel includes at least a first time period. During the first time period, under the control of the first gate driving signal, the data voltage writing path of the first sub-pixel is turned off, and under the control of the first gate driving signal, the data voltage writing path of the second sub-pixel is turned on. This allows the data refresh rate of the first sub-pixel to be lower than that of the second sub-pixel in the first mode, achieving a differentiated design of the data refresh rates of the first and second sub-pixels. The data refresh rate of a sub-pixel refers to the number of times data voltage is written to the sub-pixel per unit time. Based on the method provided by this invention, the data refresh rate of the first sub-pixel can be lower than the frequency of the second gate driving signal. That is, without changing the frequency of the second gate driving signal, at least the frequency reduction of the first sub-pixel can be achieved by designing the timing of the first gate driving signal received by the first sub-pixel.

[0180] It should be understood that, without conflict, the above embodiments and features described in the embodiments of the present invention can be combined with each other.

[0181] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, It includes multiple data lines and multiple sub-pixel rows arranged along a first direction, each sub-pixel row including multiple sub-pixels arranged along a second direction, the first direction and the second direction intersecting; each sub-pixel includes a first transistor, a second transistor and a storage capacitor; wherein the first transistor and the second transistor are connected in series between the data lines and the storage capacitor; The gate of the first transistor receives a first gate drive signal. The gate of the second transistor receives the second gate drive signal. The display panel operates in a first mode, wherein in the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. The working cycle of the display panel includes at least a first time period. During the first time period, when the second gate drive signal received by the first sub-pixel is at the second enable level, the first gate drive signal received by the first sub-pixel is at the first disable level. When the second gate drive signal received by the second sub-pixel is at the second enable level, the first gate drive signal received by the second sub-pixel is at the first enable level. Wherein, the first enable level refers to the level that controls the first transistor to be turned on, the first disable level refers to the level that controls the first transistor to be turned off, and the second enable level refers to the level that controls the second transistor to be turned on.

2. The display panel according to claim 1, characterized in that, It also includes a first gate control circuit and multiple first gate lines, the first gate lines being electrically connected to the gate of the first transistor; The first gate control circuit includes a gate drive bus. In the first mode, the gate drive bus is electrically connected to the first gate line, and the gate drive bus is used to transmit the first gate drive signal.

3. The display panel according to claim 2, characterized in that, The first sub-pixel and the second sub-pixel are located in different sub-pixel rows; the first sub-pixel and the second sub-pixel are connected to the same gate drive bus; and... When the second gate drive signal received by the first sub-pixel is at the second enable level, the gate drive bus provides the first enable level; When the second gate drive signal received by the second sub-pixel is at the second enable level, the gate drive bus provides a first disable level.

4. The display panel according to claim 2, characterized in that, The same sub-pixel row includes the first sub-pixel and the second sub-pixel; The first gate control circuit includes at least two gate driving buses, one of which is electrically connected to the first sub-pixel and the other is electrically connected to the second sub-pixel. When the second gate drive signal received by the first sub-pixel and the second sub-pixel is at the second enable level, the gate drive bus electrically connected to the first sub-pixel provides a first disable level, and the gate drive bus electrically connected to the second sub-pixel provides a first disable level.

5. The display panel according to claim 4, characterized in that, The period of the signal of the gate driving bus electrically connected to the first sub-pixel is TH1, TH1≥N1×T0, where T0 is the period of the second gate driving signal; N1 is an integer, N1≥2; The signal of the gate drive bus electrically connected to the second sub-pixel is constantly at a first enable level, or the period of the signal of the gate drive bus electrically connected to the second sub-pixel is TH2, TH2≥N2×T0, N2 is an integer, 2≤N2<N1.

6. The display panel according to claim 2, characterized in that, The first gate control circuit includes: The first control transistor has its gate electrically connected to the first signal line. The second control transistor has its gate electrically connected to the second signal line. The first terminal of both the first control transistor and the first terminal of the second control transistor are electrically connected to the gate drive bus. The second terminals of the first control transistor and the second control transistor are both electrically connected to the first gate line; In the first mode, the first signal line and the second signal line provide conduction signals in a time-division manner.

7. The display panel according to claim 2, characterized in that, A first gate line is electrically connected to at least two of the sub-pixels in the same row of sub-pixels.

8. The display panel according to claim 7, characterized in that, At least a portion of the first gate line extends along the first direction; The display panel further includes a gate connection line, which electrically connects the first gate line and at least two sub-pixels in the same sub-pixel row; At least a portion of the gate connection line extends along the second direction.

9. The display panel according to claim 8, characterized in that, The plurality of said sub-pixels includes at least red sub-pixels, green sub-pixels, and blue sub-pixels arranged along the second direction; At least a portion of the orthographic projection of the first gate line onto the plane of the display panel is located on the side of the orthographic projection of the blue sub-pixel onto the plane of the display panel that is away from the orthographic projection of the green sub-pixel onto the plane of the display panel.

10. The display panel according to claim 1, characterized in that, The first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the first terminal of the first transistor; the second terminal of the first transistor is electrically connected to the first plate of the storage capacitor.

11. The display panel according to claim 2, characterized in that, The display panel includes a first non-display area and a second non-display area, the first non-display area and the display area are arranged along the first direction, and the second non-display area and the display area are arranged along the second direction; The second non-display area includes a second gate control circuit, which includes multiple cascaded gate control units. The gate control units are electrically connected to the second transistor and are used to provide the second gate drive signal to the second transistor.

12. The display panel according to claim 11, characterized in that, The first non-display area includes at least a portion of the first gate control circuit; Alternatively, the second non-display area may include at least a portion of the first gate control circuit.

13. A driving method for a display panel, characterized in that, The display panel includes multiple data lines and multiple rows of sub-pixels arranged along a first direction. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, where the first and second directions intersect. Each sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The first transistor and the second transistor are connected in series between the data lines and the storage capacitor. The gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal. The display panel's operating mode includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel, and the display panel's operating cycle includes at least a first time period. In the first mode, the driving method includes: During the first time period, when the second gate drive signal received by the first sub-pixel is at the second enable level, the first gate drive signal received by the first sub-pixel is controlled to be at the first disable level. When the second gate drive signal received by the second sub-pixel is at the second enable level, the first gate drive signal received by the second sub-pixel is controlled to be at the first enable level. Wherein, the first enable level refers to the level that controls the first transistor to be turned on, the first disable level refers to the level that controls the first transistor to be turned off, and the second enable level refers to the level that controls the second transistor to be turned on.

14. The driving method according to claim 13, characterized in that, The display panel includes a display area and a non-display area; The display area includes multiple first gate lines, which are electrically connected to the gate of the first transistor. The non-display area includes a first gate control circuit, which includes a gate drive bus. In the first mode, the gate drive bus is electrically connected to the first gate line and is used to transmit the first gate drive signal.

15. The driving method according to claim 14, characterized in that, The first sub-pixel and the second sub-pixel are located in different rows of sub-pixels; The first sub-pixel and the second sub-pixel are connected to the same gate drive bus; The method for controlling the first gate drive signal received by the first sub-pixel to be at a first disabled level and the first gate drive signal received by the second sub-pixel to be at a first enabled level includes: When the second gate drive signal received by the first sub-pixel is at a second enable level, the gate drive bus is controlled to provide a first enable level. When the second gate drive signal received by the second sub-pixel is at the second enable level, the gate drive bus is controlled to provide a first disable level.

16. The driving method according to claim 14, characterized in that, The same sub-pixel row includes the first sub-pixel and the second sub-pixel; The first gate control circuit includes at least two gate driving buses, one of which is electrically connected to the first sub-pixel and the other is electrically connected to the second sub-pixel. The first gate drive signal received by the first sub-pixel is controlled to be at a first disabled level. The method for controlling the first gate drive signal received by the second sub-pixel to be at a first enable level includes: When the second gate drive signal received by the first sub-pixel and the second sub-pixel is at a second enable level, the gate drive bus electrically connected to the first sub-pixel is controlled to provide a first disable level, and the gate drive bus electrically connected to the second sub-pixel is controlled to provide a first enable level.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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