Transmission circuit structure

Abstract

This invention discloses a transmission circuit structure, comprising: a first level shift circuit with inputs connected to a first state signal, a high-voltage signal, and a negative-voltage signal; a first output connected to a first MOS transistor; and a second output connected to an eighth MOS transistor. The first and second MOS transistors are connected in series, with the first MOS transistor connected to a negative voltage source, the second MOS transistor connected to a first electrical node, and the second MOS transistor connected to a power supply voltage. A second level shift circuit with inputs connected to a second state signal and a high-voltage signal; a first output connected to a seventh MOS transistor; and a second output connected to a sixth MOS transistor. The sixth MOS transistor is connected to a high-voltage source, the seventh MOS transistor is connected to a specified voltage source, and the sixth and seventh MOS transistors are connected to a second electrical node. The eighth MOS transistor is connected to the second electrical node, and the eighth and ninth MOS transistors are connected in series, with the ninth MOS transistor connected to the first electrical node and grounded. The third and fifth MOS transistors are connected to the first electrical node. The third MOS transistor is grounded, as are the fourth and fifth MOS transistors. The fourth MOS transistor is connected to a negative voltage signal and a third state signal, and the fifth MOS transistor is connected to a negative voltage output. A resistor is connected in parallel with the fifth MOS transistor. This invention can reduce the off-state leakage current of the transmission circuit structure, thereby reducing power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a transmission circuit structure for embedded flash memory. Background Technology

[0002] Embedded flash memory is a crucial component of MCUs, and with the rapid development of new energy vehicles, the demand for automotive-grade electronics has exploded. Unlike consumer electronics, automotive-grade electronics have much stricter requirements for the operating environment of chips. For example, in terms of operating temperature, consumer electronics only need to meet the requirements of 0℃-85℃, while automotive-grade electronics need to meet the requirements of -40℃-150℃.

[0003] As chip operating temperature increases, channel leakage current in internal components becomes more severe. In embedded flash memory, high voltage is generated by the charge pump. The increase in off-state leakage current indirectly increases the load on the charge pump. When the charge pump's load capacity is weak, the generated high voltage may not reach the target voltage value. Compared to the positive high-voltage charge pump, the negative high-voltage charge pump is relatively weaker, therefore the off-state leakage current has a greater impact on the negative high-voltage charge pump.

[0004] Figure 1 The diagram illustrates a simulation of leakage current generation. In embedded flash memory, NMOS transistors are typically used to control the transfer of negative voltage. To transfer -8V, -8V is applied to VNEG_D and 0V to VNEG_G, allowing for efficient transfer of the negative voltage to the source. Conversely, -8V is applied to VNEG_G to shut down the conductive channel. When -8V is applied to the gate and drain, and 0V to the source, a large electric field is generated between the source and drain terminals, pointing from the source to the drain. This field intensifies the reverse bias current, increasing the off-state leakage current. During a full-chip erase of a large-capacity embedded flash memory, thousands or even more MOS transistors are in this state, connected in parallel between the negative voltage and ground, resulting in a significant off-state leakage current. This affects the output of the negative charge pump, causing unnecessary power consumption. The technical problem of increased off-state leakage current at high temperatures leading to increased load current of the negative charge pump remains to be solved. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is to provide a transmission circuit structure that can reduce off-state leakage current.

[0007] To solve the above-mentioned technical problems, the present invention provides a transmission circuit structure for embedded flash memory, comprising:

[0008] The first level shift circuit has its inputs connected to the first state signal ERASED, the high voltage signal HVIN, and the negative voltage signal VNEG, respectively. Its first output A is connected to the third terminal of the first MOS NM0, and its second output B is connected to the third terminal of the eighth MOS PM2.

[0009] The first terminal of the first MOS NM0 and the second terminal of the second MOS NM1 are connected in series. The second terminal of the first MOS NM0 is connected to the negative voltage signal VNEG. The first terminal of the second MOS NM1 is connected to the first electrical node SET. The third terminal of the second MOS NM1 is connected to the power supply voltage VDD.

[0010] The second level shift circuit, Level Shift 1, has its inputs connected to the second state signal ERASE_GLO and the high voltage signal HVIN, respectively. Its first output C is connected to the third terminal of the seventh MOS PM1, and its second output D is connected to the third terminal of the sixth MOS PM0.

[0011] The first terminal of the sixth MOS PM0 is connected to the high-voltage signal HVIN, the first terminal of the seventh MOS PM1 is connected to the specified voltage V1P5, and the second terminals of the sixth MOS PM0 and the seventh MOS PM1 are connected to the second electrical node E.

[0012] The first terminal of the eighth MOS PM2 is connected to the second electrical node E. The second terminal of the eighth MOS PM2 is connected in series with the first terminal of the ninth MOS PM3. The second terminal of the ninth MOS PM3 is connected to the first electrical node SET. The third terminal of the ninth MOS PM3 is grounded.

[0013] The third terminal of the third MOS NM2 and the third terminal of the fifth MOS NM4 are connected to the first electrical node SET;

[0014] The third MOS NM2 has its second terminal grounded, and its first terminal is connected to the second terminal of the fourth MOS NM3 and the second terminal of the fifth MOS NM4.

[0015] The fourth MOS NM3 has its first terminal connected to the negative voltage signal VNEG and its third terminal connected to the third state signal EN.

[0016] The fifth MOS NM4 has its first terminal connected to the negative voltage output VNEG_OUT;

[0017] Resistor R0 is connected in parallel between the first and second terminals of the fifth MOS NM4.

[0018] Among them, the first to fifth MOS are NMOS, and the sixth to ninth MOS are PMOS; the first terminal is the source, the second terminal is the drain, and the third terminal is the gate.

[0019] Furthermore, when the transmission circuit structure of the present invention is working, when the second state signal ERASE_GLO is 1 and the first state signal ERASED is 1, the negative voltage signal VNEG is the specified negative voltage, the first level shift circuit Level Shift sets its first output A to the power supply voltage VDD, its second output B to the positive high voltage, the first MOS NM0 is turned on, the eighth MOS PM2 is turned off, and the first electrical node SET is set to the specified negative voltage;

[0020] The second level shift circuit, Level Shift 1, sets its first output C to GND, its second output D to a positive high voltage, the sixth MOS PM0 to turn off, the seventh MOS PM1 to turn on, the second electrical node E to the specified voltage V1P5, the first electrical node SET to the specified negative voltage, the third MOS NM2 and the fifth MOS NM4 to turn off, the third status signal EN to 0, and the negative voltage signal VNEG is transmitted to the negative voltage output VNEG_OUT through the fourth MOS NM3 and resistor R0. The negative voltage output VNEG_OUT is connected to... Figure 1 VNEG_D in the diagram, the negative pressure signal VNEG is connected. Figure 1 In VNEG_G, as the leakage current increases, the voltage drop across resistor R0 increases, causing the absolute value of the negative voltage output VNEG_OUT to decrease. At this time:

[0021] V gs =VNEG_G-VNEG_D<0

[0022] Therefore, it can effectively suppress off-state leakage current, reduce the current flowing through resistor R0, decrease the voltage drop across resistor R0, and eventually reach a stable state. For example... Figure 3 In the equations VNEG and VNEG_OUT, the final stable voltage difference between the negative voltage output VNEG_OUT and the negative voltage signal VNEG is approximately 0.1V. The negative voltage output VNEG_OUT is the final voltage applied to the flash memory cell, and the voltage loss is within an acceptable range. i(r2) represents the load current required by the negative voltage charge pump. The blue line represents the result using the proposed transmission structure, and the red line represents the result without using the transmission structure. It can be seen that this negative voltage transmission structure can effectively reduce leakage current and ensure the normal operation of the negative voltage charge pump.

[0023] Furthermore, when the transmission circuit structure of the present invention is working, when the second state signal ERASE_GLO is 1 and the first state signal ERASED is 0, the first level shift circuit Level Shift sets the first output A to GND, its second output B to GND, the negative voltage signal VNEG is 0, the first MOS NM0 is turned off, and the eighth MOS PM2 is turned on.

[0024] The second level shift circuit, Level Shift 1, sets its first output C to GND, its second output D to a positive high voltage, the sixth MOS PM0 to turn off, the seventh MOS PM1 to turn on, the second electrical node E to the specified voltage V1P5, the third MOS NM2 and the fifth MOS NM4 to turn on, and the negative voltage output VNEG_OUT to 0. This state corresponds to the unselected bank during flash memory erasure.

[0025] Furthermore, when the transmission circuit structure of the present invention is working, when the second state signal ERASE_GLO is 0 and the first state signal ERASED is 0, the first level shift circuit Level Shift sets the first output A to GND and its second output B to GND.

[0026] The second level shift circuit, Level Shift 1, sets its first output C to positive high voltage and its second output D to GND.

[0027] The second level shift circuit, Level Shift 1, sets its first output C to positive high voltage and its second output D to GND. The high voltage signal HVIN is transmitted to the first electrical node SET, enhancing the driving capability of the third MOS NM2 and the fifth MOS NM4, causing the negative voltage output VNEG_OUT to be pulled down to a stable 0. This state corresponds to the non-erasing operating mode.

[0028] When transmitting negative voltage, the transmission circuit structure of the present invention connects a resistor in series between the charge pump output and the device. The voltage drop across the resistor increases with the increase of leakage current, so that the voltage Vgs applied to the gate and drain terminals of the MOS transistor is less than 0, thereby reducing the off-state leakage current and thus reducing power consumption. Attached Figure Description

[0029] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0030] Figure 1 This is a schematic diagram simulating the generation of leakage current.

[0031] Figure 2 This is a schematic diagram of the structure of the present invention.

[0032] Figure 3 This is a simulation diagram of voltage and current in this invention. Detailed Implementation

[0033] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0034] Example

[0035] refer to Figure 2 As shown, the present invention provides a transmission circuit structure for embedded flash memory, comprising:

[0036] The first level shift circuit has its inputs connected to the first state signal ERASED, the high voltage signal HVIN, and the negative voltage signal VNEG, respectively. Its first output A is connected to the gate of the first MOS NM0, and its second output B is connected to the gate of the eighth MOS PM2.

[0037] The source of the first MOS NM0 and the drain of the second MOS NM1 are connected in series. The drain of the first MOS NM0 is connected to the negative voltage signal VNEG, and the source of the second MOS NM1 is connected to the first electrical node SET. The gate of the second MOS NM1 is connected to the power supply voltage VDD.

[0038] The second level shift circuit, Level Shift 1, has its inputs connected to the second state signal ERASE_GLO and the high voltage signal HVIN, respectively. Its first output C is connected to the gate of the seventh MOS PM1, and its second output D is connected to the gate of the sixth MOS PM0.

[0039] The source of the sixth MOS PM0 is connected to the high-voltage signal HVIN, the source of the seventh MOS PM1 is connected to the specified voltage V1P5, and the drains of the sixth MOS PM0 and the seventh MOS PM1 are connected to the second electrical node E.

[0040] The source of the eighth MOS PM2 is connected to the second electrical node E, the drain of the eighth MOS PM2 is connected in series with the source of the ninth MOS PM3, the drain of the ninth MOS PM3 is connected to the first electrical node SET, and the gate of the ninth MOS PM3 is grounded.

[0041] The gates of the third MOS NM2 and the fifth MOS NM4 are connected to the first electrical node SET;

[0042] The third MOS NM2 has its drain grounded, and its source is connected to the drain of the fourth MOS NM3 and the drain of the fifth MOS NM4;

[0043] The fourth MOS NM3 has its source connected to the negative voltage signal VNEG and its gate connected to the third state signal EN.

[0044] The fifth MOS NM4 has its source connected to the negative voltage output VNEG_OUT;

[0045] Resistor R0 is connected in parallel between the source and drain of the fifth MOS NM4;

[0046] Among them, the first to fifth MOS are NMOS, and the sixth to ninth MOS are PMOS;

[0047] When the second state signal ERASE_GLO is 1 and the first state signal ERASED is 1, the negative voltage signal VNEG is the specified negative voltage, the first level shift circuit Level Shift sets its first output A to the power supply voltage VDD, its second output B to the positive high voltage, the first MOS NM0 is turned on, the eighth MOS PM2 is turned off, and the first electrical node SET is set to the specified negative voltage.

[0048] The second level shift circuit, Level Shift 1, sets its first output C to GND, its second output D to a positive high voltage, the sixth MOS PM0 to turn off, the seventh MOS PM1 to turn on, the second electrical node E to the specified voltage V1P5, the first electrical node SET to the specified negative voltage, the third MOS NM2 and the fifth MOS NM4 to turn off, the third status signal EN to 0, and the negative voltage signal VNEG to the negative voltage output VNEG_OUT through the fourth MOS NM3 and resistor R0.

[0049] When the second state signal ERASE_GLO is 1 and the first state signal ERASED is 0, the first level shift circuit sets the first output A to GND, its second output B to GND, the negative voltage signal VNEG is 0, the first MOS NM0 is turned off, and the eighth MOS PM2 is turned on.

[0050] The second level shift circuit, Level Shift 1, sets its first output C to GND, its second output D to a positive high voltage, the sixth MOS PM0 to turn off, the seventh MOS PM1 to turn on, the second electrical node E to the specified voltage V1P5, the third MOS NM2 and the fifth MOS NM4 to turn on, and the negative voltage output VNEG_OUT to 0. This state corresponds to the unselected bank during flash memory erasure.

[0051] When the second state signal ERASE_GLO is 0 and the first state signal ERASED is 0, the first level shift circuit sets its first output A to GND and its second output B to GND.

[0052] The second level shift circuit, Level Shift 1, sets its first output C to positive high voltage and its second output D to GND.

[0053] The second level shift circuit, Level Shift 1, sets its first output C to positive high voltage and its second output D to GND. The high voltage signal HVIN is transmitted to the first electrical node SET, enhancing the driving capability of the third MOS NM2 and the fifth MOS NM4, causing the negative voltage output VNEG_OUT to be pulled down to a stable 0. This state corresponds to the non-erasing operating mode.

[0054] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0056] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A transmission circuit structure for embedded flash memory, characterized by, include: The first level shift circuit has its inputs connected to the first state signal (ERASED), the high voltage signal (HVIN), and the negative voltage signal (VNEG), respectively. Its first output (A) is connected to the third terminal of the first MOS (NM0), and its second output (B) is connected to the third terminal of the eighth MOS (PM2). The first terminal of the first MOS (NM0) and the second terminal of the second MOS (NM1) are connected in series. The second terminal of the first MOS (NM0) is connected to the negative voltage signal (VNEG). The first terminal of the second MOS (NM1) is connected to the first electrical node (SET). The third terminal of the second MOS (NM1) is connected to the power supply voltage (VDD). The second level shift circuit (Level Shift 1) has its inputs connected to the second state signal (ERASE_GLO) and the high voltage signal (HVIN), respectively. Its first output (C) is connected to the third terminal of the seventh MOS (PM1), and its second output (D) is connected to the third terminal of the sixth MOS (PM0). The first terminal of the sixth MOS (PM0) is connected to the high voltage signal (HVIN), the first terminal of the seventh MOS (PM1) is connected to the specified voltage (V1P5), and the second terminals of the sixth MOS (PM0) and the seventh MOS (PM1) are connected to the second electrical node (E). The first terminal of the eighth MOS (PM2) is connected to the second electrical node (E), the second terminal of the eighth MOS (PM2) and the first terminal of the ninth MOS (PM3) are connected in series, the second terminal of the ninth MOS (PM3) is connected to the first electrical node (SET), and the third terminal of the ninth MOS (PM3) is grounded; The third terminal of the third MOS (NM2) and the third terminal of the fifth MOS (NM4) are connected to the first electrical node (SET); The third MOS (NM2) has its second terminal grounded, and its first terminal connected to the second terminal of the fourth MOS (NM3) and the second terminal of the fifth MOS (NM4); The fourth MOS (NM3) has its first terminal connected to the negative voltage signal (VNEG) and its third terminal connected to the third state signal (EN). The fifth MOS (NM4) has its first terminal connected to the negative voltage output (VNEG_OUT); A resistor (R0) is connected in parallel between the first and second terminals of the fifth MOS (NM4).

2. The transmission circuit structure of claim 1, wherein: The first to fifth MOS are NMOS, and the sixth to ninth MOS are PMOS; The first terminal is the source, the second terminal is the drain, and the third terminal is the gate.

3. The transmission circuit structure as described in claim 1, characterized in that: When the second state signal (ERASE_GLO) is 1 and the first state signal (ERASED) is 1, the negative voltage signal (VNEG) is the specified negative voltage, the first level shift circuit (LevelShift) sets its first output (A) to the power supply voltage (VDD), its second output (B) to the positive high voltage, the first MOS (NM0) is turned on, the eighth MOS (PM2) is turned off, and the first electrical node (SET) is set to the specified negative voltage; The second level shift circuit (Level Shift 1) sets its first output (C) to GND, its second output (D) to positive high voltage, the sixth MOS (PM0) to turn off, the seventh MOS (PM1) to turn on, the second electrical node (E) to the specified voltage (V1P5), the first electrical node (SET) to the specified negative voltage, the third MOS (NM2) and the fifth MOS (NM4) to turn off, the third state signal (EN) to be 0, and the negative voltage signal (VNEG) to be transmitted to the negative voltage output (VNEG_OUT) through the fourth MOS (NM3) and the resistor (R0).

4. The transmission circuit structure as described in claim 1, characterized in that: When the second state signal (ERASE_GLO) is 1 and the first state signal (ERASED) is 0, the first level shift circuit (LevelShift) sets the first output (A) to GND, its second output (B) to GND, the negative voltage signal (VNEG) is 0, the first MOS (NM0) is turned off, and the eighth MOS (PM2) is turned on. The second level shift circuit (Level Shift 1) sets its first output (C) to GND, its second output (D) to positive high voltage, the sixth MOS (PM0) to turn off, the seventh MOS (PM1) to turn on, the second electrical node (E) to the specified voltage (V1P5), the third MOS (NM2) and the fifth MOS (NM4) to turn on, and the negative voltage output (VNEG_OUT) to 0. This state corresponds to the unselected bank during flash memory erasure.

5. The transmission circuit structure as described in claim 1, characterized in that: When the second state signal (ERASE_GLO) is 0 and the first state signal (ERASED) is 0, the first level shift circuit sets the first output (A) to GND and its second output (B) to GND; The second level shift circuit (Level Shift 1) sets its first output (C) to positive high voltage and its second output (D) to GND. The second level shift circuit (Level Shift 1) sets its first output (C) to positive high voltage and its second output (D) to GND. The high voltage signal (HVIN) is transmitted to the first electrical node (SET), which enhances the driving capability of the third MOS (NM2) and the fifth MOS (NM4), causing the negative voltage output (VNEG_OUT) to be pulled down to a stable 0. This state corresponds to the non-erasing operating mode.

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