A silicon-based vapor chamber and a method for packaging a chip thereof

Abstract

The application belongs to the field of heat dissipation devices and relates to a silicon-based heat spreading plate and a method for packaging a chip. The silicon-based heat spreading plate comprises an upper shell plate and a lower shell plate, the upper shell plate and the lower shell plate form a closed cavity, the upper shell plate and the lower shell plate are both made of silicon, and the upper shell plate has a boiling enhancement structure on the surface. The silicon-based heat spreading plate is matched with the chip in terms of the coefficient of thermal expansion, warping caused by thermal stress at high temperature is avoided, the thermal resistance can be effectively reduced, and the performance and reliability of the immersion cooling device are improved. The boiling enhancement structure is manufactured on the surface of the silicon-based heat spreading plate, surface modification is realized, and the boiling heat dissipation performance of the heat spreading plate in the immersion cooling process is further enhanced.

Description

Technical Field

[0001] This invention belongs to the field of heat dissipation devices, and in particular to a silicon-based heat sink and a method for packaging chips thereon. Background Technology

[0002] With the advent of the digital age, data centers, as key hubs for information storage, processing, exchange, and transmission, are experiencing a year-on-year increase in data processing volume. This places higher demands on the heat dissipation of high-power computing chips used in data center applications. Efficient heat dissipation is crucial for maintaining the long-term high-performance operation of chips. Related research shows that when a chip exceeds its normal operating temperature range, its failure rate increases by 10% for every 2°C increase in temperature. Compared to traditional air cooling and direct liquid cooling solutions, two-phase immersion cooling has been widely used in the field of data center cooling due to its advantages such as low power consumption, small size, and high heat dissipation efficiency.

[0003] Most existing chip packaging methods use metal materials as integrated heatspreaders (IHS). However, there is a mismatch in the coefficient of thermal expansion between the metal and the silicon chip. Only thermally conductive interfacial membranes (TIMs) with poor thermal conductivity can be used between them to alleviate interface cracking caused by stress mismatch, thus affecting the long-term reliability of the chip. Using silicon as the heatspreader material can eliminate the interface unreliability caused by thermal mismatch. Furthermore, since there is no coefficient of thermal expansion mismatch, metal TIMs with higher thermal conductivity can be used, further reducing thermal resistance. While silicon itself has a lower thermal conductivity than metal materials (approximately 140 W / (m·K)), its equivalent thermal conductivity can be significantly improved by making silicon into a vapor chamber.

[0004] A vapor chamber is a commonly used phase change heat transfer device. It can efficiently dissipate heat from the heat source through the evaporation-condensation process of the internal working fluid. Applying it to immersion cooling can significantly increase the heat dissipation area of ​​high-power chips and improve the efficiency of immersion cooling. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a silicon-based heat spreader and its packaged chip method for enhancing the efficiency of immersion cooling. This invention achieves matching of thermal expansion coefficients, avoids warping problems caused by thermal stress at high temperatures, effectively reduces thermal resistance, and improves the performance and reliability of immersion cooling devices.

[0006] The technical solution adopted by this invention to solve the technical problem is:

[0007] A first aspect of the present invention is to provide a silicon-based heat spreader, comprising: an upper shell plate and a lower shell plate, the upper shell plate and the lower shell plate forming a closed cavity, the upper shell plate and the lower shell plate being made of silicon, and the surface of the upper shell plate having a boiling enhancement structure.

[0008] Furthermore, multiple support columns of different heights were integrally constructed within the enclosed cavity.

[0009] Furthermore, a nanoporous layer is formed on the inner wall of the enclosed cavity and the surface of the support column.

[0010] Furthermore, the upper and lower shell plates are made of monocrystalline silicon or polycrystalline silicon, and the surface of the lower shell plate is polished to achieve a surface roughness Ra of less than 0.1 μm, so as to achieve low contact thermal resistance with the chip.

[0011] Furthermore, the boiling enhancement structure on the surface of the upper shell plate is a microchannel array, the width of the microchannel is 2-200μm, the depth is 10-500μm, the spacing between adjacent microchannels is 10-500μm, and the structure is formed by deep reactive ion etching or metal-assisted chemical etching.

[0012] Alternatively, the boiling enhancement structure may be a silicon micropillar array, wherein the silicon micropillars have a height of 10-500 μm and a diameter of 5-50 μm, and are arranged in a periodic or non-periodic manner.

[0013] Alternatively, the boiling-enhanced structure may be a silicon nanowire with a length of 0.5-5 μm and a diameter of 10-500 nm, formed by a metal-assisted chemical etching method.

[0014] Alternatively, the boiling-enhanced structure may be a silicon nanopore with a depth of 0.5-5 μm and a pore size of 10-1000 nm, formed by electrochemical etching.

[0015] Alternatively, the boiling-enhanced structure may be a silicon microstructure array with surface-modified nanopores or nanowires. The structure can be summarized as a hierarchical micro-nano composite structure, with the dimensions of the corresponding layers being the same as above.

[0016] Furthermore, the upper shell plate and the lower shell plate are connected by a wafer bonding method, which includes one of anodic bonding, direct bonding or interposer bonding.

[0017] Furthermore, the nanoporous layer is made of silicon, with a thickness of 0.5-5 μm, a porosity of 30-70%, and a pore size of 10-1000 nm.

[0018] A second aspect of the present invention is to provide a method for packaging a chip with the aforementioned silicon-based heat spreader, wherein the silicon-based heat spreader and the chip are mechanically connected and thermally conducted by welding a thermally conductive metal interface material (TIM), wherein the thermal conductivity of the TIM is greater than 80 W / (m·K).

[0019] Furthermore, the electronic chip and the substrate are electrically connected via microbumps. The silicon-based heat sink is bonded to the substrate using an underfill adhesive.

[0020] Furthermore, it also includes a silicon interposer containing TSV vias. There are multiple chips, and the silicon interposer is located between the chip and the substrate, and is connected to the chip and the substrate through microbumps.

[0021] The advantages and positive effects of this invention are:

[0022] 1. The present invention achieves matching of thermal expansion coefficients between the silicon-based heat spreader and the chip, avoiding warping problems caused by thermal stress at high temperatures, effectively reducing thermal resistance, and improving the performance and reliability of immersion cooling devices.

[0023] 2. The present invention creates a boiling enhancement structure on the surface of a silicon-based heat spreader, which can achieve surface modification and further enhance the boiling heat dissipation performance of the heat spreader surface during immersion cooling. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the silicon-based heat sink structure of the present invention;

[0025] Figure 2 This is a flowchart of the manufacturing process of the silicon-based heat sink of the present invention;

[0026] Figure 3 This is a structural diagram of a single chip packaged in the silicon-based heat sink of the present invention;

[0027] Figure 4 This is a diagram showing the packaged structure of multiple chips in the silicon-based heat sink of the present invention.

[0028] Figure 5 This is a comparison diagram of the heat dissipation effect of the silicon-based heat sink structure of this invention with other packaging structures. Detailed Implementation

[0029] The present invention will be further described in detail below through specific embodiments. The following embodiments are merely descriptive and not limiting, and should not be used to limit the scope of protection of the present invention.

[0030] like Figure 1 The silicon-based heat exchanger shown includes an upper shell plate 1 and a lower shell plate 2, which form a closed chamber. Both the upper shell plate 1 and the lower shell plate 2 are made of silicon. The surface of the upper shell plate 1 has a boiling enhancement structure 5, which forms a heat exchange surface that is conducive to boiling enhancement and improves the heat dissipation efficiency of immersion cooling.

[0031] The upper shell 1 and the lower shell 2 are made of silicon material, which achieves the matching of the thermal expansion coefficient between the materials with the chip, reduces the thermal resistance, and can effectively improve the heat dissipation efficiency of the chip and the stability of the heat dissipation system.

[0032] Multiple support columns 3 of different heights are integrally formed in the closed chamber to provide mechanical support, prevent deformation of the heat spreader, and promote condensation backflow.

[0033] A nanoporous layer 4 is formed on the inner wall of the enclosed cavity and the surface of the support column 3 to promote the evaporation, condensation and reflux of the working fluid and enhance the heat transfer effect of the heat exchange plate.

[0034] The upper shell 1 and the lower shell 2 are made of monocrystalline silicon or polycrystalline silicon. The surface of the lower shell 2 is polished, with a surface roughness Ra of less than 0.1 μm, to achieve low contact thermal resistance with the chip. In a preferred embodiment, the upper shell 1 and the lower shell 2 are connected by a wafer bonding method, which includes one of anodic bonding, direct bonding, or interposer bonding.

[0035] In a preferred embodiment, the boiling enhancement structure 5 on the surface of the upper shell plate 1 is a microchannel array. The width of the microchannel is 2-200 μm, the depth is 10-500 μm, and the spacing between adjacent microchannels is 10-500 μm. The structure is formed by deep reactive ion etching or metal-assisted chemical etching.

[0036] In a preferred embodiment, the silicon micropillars have a height of 10-500 μm and a diameter of 5-50 μm, and are arranged in a periodic or non-periodic pattern.

[0037] In a preferred embodiment, the silicon nanowires have a length of 0.5-5 μm and a diameter of 10-500 nm, and are formed by metal-assisted chemical etching.

[0038] In a preferred embodiment, the boiling enhancement structure is a silicon nanopore with a depth of 0.5-5 μm and a pore size of 10-1000 nm, and is formed by electrochemical etching.

[0039] In a preferred embodiment, the boiling enhancement structure is a silicon microstructure array with nanopores or nanowires modified on its surface. The structure can be summarized as a hierarchical micro-nano composite structure, with the dimensions of the corresponding layers being the same as above.

[0040] In a preferred embodiment, the nanoporous layer 4 is made of silicon, with a thickness of 0.5-5 μm, a porosity of 30-70%, and a pore size of 10-1000 nm.

[0041] Figure 2This is a flowchart of the manufacturing process of the silicon-based heat sink of the present invention. Figure (a) and Figure (d) show the raw materials for the lower and upper shell plates of the silicon-based heat sink, respectively. Figure (d) shows the boiling enhancement structure fabricated on the surface of the upper shell plate through an electrochemical etching process, resulting in Figure (e). Figures (a) and (e) are both etched using a composite mask to create the gas chamber support structure and the condensation backflow structure within the heat sink, resulting in Figures (b) and (f), respectively. Figures (b) and (e) are both fabricated on the inner surface of the heat sink through an electrochemical etching process, resulting in Figures (c) and (g), respectively. Figures (c) and (g) are connected by wafer bonding to obtain the complete silicon-based heat sink structure (h).

[0042] Figure 3 This is a structural diagram of a single chip packaged in a silicon-based heat spreader according to the present invention. The silicon-based heat spreader 6 and the chip 8 are mechanically connected and thermally conducted through a metal thermal interface material (TIM7) welded together. The thermal conductivity of the TIM7 is greater than 80 W / (m·K). The electronic chip 8 and the substrate 10 are electrically connected through microbumps 9. The silicon-based heat spreader 6 and the substrate 10 are bonded together using an underfill adhesive 11.

[0043] Indium foil can be used as the thermal interface material TIM7, which has excellent heat transfer properties and can significantly reduce the contact thermal resistance of TIM. Other metal materials with excellent thermal conductivity can also be used.

[0044] Figure 4 This is a structural diagram of a silicon-based heat sink for packaging multiple chips according to the present invention. Multiple chips are supported by a silicon interposer 12 and are arranged at intervals. The silicon interposer 12 includes TSV vias 13. There are multiple chips 8. The silicon interposer 12 is located between the chip 8 and the substrate 10 and is connected to the chip 8 and the substrate 10 through microbumps 9.

[0045] This application tested the chip's heat dissipation performance under six different conditions, such as... Figure 5 As shown, the six structures are: 1) bare chip; 2) chip + MP (with a boiling-enhanced silicon micropillar array fabricated on the chip surface); 3) Si structure (using a solid Si thermal expansion block connected to the chip via indium foil); 4) SiMP structure (using a solid Si thermal expansion block with a boiling-enhanced silicon micropillar array fabricated on its surface, connected to the chip via indium foil); 5) VC structure (using a flat Si-based heat spreader as the thermal expansion block, connected to the chip via indium foil); and 6) VCMP structure (using a Si-based heat spreader as the thermal expansion block with a boiling-enhanced silicon micropillar array fabricated on its surface, connected to the chip via indium foil). In the experiment, TDP was defined as the power consumed when the chip reached 95°C; a higher TDP value indicates better heat dissipation.

[0046] The test results show that the silicon-based heat sink in this application has the best heat dissipation performance.

[0047] Test type TDP(W) bare chip 70.2 Chip + MP 144 Si structure 134.2 SiMP structure 180.5 VC architecture 336.7 VCMP structure 373.7

[0048] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the inventive concept, and these all fall within the protection scope of the present invention.

Claims

1. A silicon-based vapor chamber for enhancing the efficiency of immersion cooling, characterized by, include: The upper shell plate (1) and the lower shell plate (2) form a closed chamber. The upper shell plate (1) and the lower shell plate (2) are both made of silicon. The surface of the upper shell plate (1) has a boiling enhancement structure (5) to enhance the boiling heat dissipation performance of the heat spreader surface during the immersion cooling process. Multiple support columns (3) of different heights are integrally formed in the closed chamber. A nanoporous layer (4) is formed on the inner wall of the closed chamber and the surface of the support columns (3). The nanoporous layer (4) is made of silicon, with a thickness of 0.5-5 μm, a porosity of 30-70%, and a pore size of 10-1000 nm. The boiling enhancement structure (5) on the surface of the upper shell plate (1) is a silicon micropillar array. The height of the silicon micropillars is 10-500 μm and the diameter is 5-50 μm. They are arranged in a periodic or non-periodic manner. Alternatively, the boiling enhancement structure (5) may be a silicon nanowire with a length of 0.5-5 μm and a diameter of 10-500 nm, and may be formed by metal-assisted chemical etching. Alternatively, the boiling enhancement structure (5) may be a silicon nanopore with a depth of 0.5-5 μm and a pore size of 10-1000 nm, and may be formed by electrochemical etching. Alternatively, the boiling enhancement structure (5) is a silicon microstructure array with nanopores or nanowires on its surface. The structure is described as a hierarchical micro-nano composite structure, with the corresponding dimensions of each level being the same as above. The upper shell plate (1), lower shell plate (2), support column (3) and nanoporous layer (4) are all made of silicon material.

2. The silicon-based heat plate according to claim 1, wherein The upper shell plate (1) and the lower shell plate (2) are made of monocrystalline silicon or polycrystalline silicon. The surface of the lower shell plate (2) is polished and the surface roughness Ra is less than 0.1 μm to achieve low contact thermal resistance with the chip.

3. The silicon-based heat spreader according to claim 1, characterized in that, The upper shell plate (1) and the lower shell plate (2) are connected by a wafer bonding method, which includes one of anodic bonding, direct bonding or interposer bonding.

4. The method for packaging a chip using a silicon-based heat spreader according to any one of claims 1 to 3, characterized in that, The silicon-based heat spreader (6) and the chip (8) are mechanically connected and heat-conducted by welding a metal thermal interface material (TIM) (7), and the thermal conductivity of the metal thermal interface material (TIM) (7) is greater than 80 W / (m·K).

5. The method for packaging a chip using a silicon-based heat spreader according to claim 4, characterized in that, The electronic chip (8) and the substrate (10) are electrically connected through microbumps (9), and the silicon-based heat spreader (6) and the substrate (10) are bonded together through bottom filler adhesive (11).

6. The method for packaging a chip using a silicon-based heat spreader according to claim 5, characterized in that, It also includes a silicon interposer (12) containing TSV vias (13). There are multiple chips (8). The silicon interposer (12) is located between the chip (8) and the substrate (10) and is connected to the chip (8) and the substrate (10) through microbumps (9).

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