A SiC MOSFET device with overcurrent resistant dual flexible buffer layer package

Abstract

This invention belongs to the field of power semiconductor device packaging technology, and particularly relates to a SiC MOSFET device packaged with an overcurrent-resistant dual flexible buffer layer. In this invention, an upper buffer layer and a lower buffer layer are respectively disposed on the upper and lower sides of the SiC MOSFET chip. An upper DBC substrate and a lower DBC substrate are respectively disposed on the side of the upper and lower buffer layers that are far apart from each other. The upper and lower buffer layers, the upper DBC substrate, and the lower DBC substrate provide good thermal conductivity and electrical performance, while ensuring thermomechanical reliability. This better dissipates the heat generated by the SiC MOSFET chip, reduces the temperature of the SiC MOSFET chip, and improves the reliability of the power module. Simultaneously, the double-sided heat dissipation structure eliminates wire bonding and uses the upper and lower buffer layers to bear the current flow, significantly reducing the parasitic inductance and size of the module.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device packaging technology, and particularly relates to a SiC MOSFET device with overcurrent resistant dual flexible buffer layer packaging. Background Technology

[0002] Compared with traditional silicon (Si)-based power devices, silicon carbide metal oxide semiconductor field-effect transistors (SiCMOSFETs) have stronger high temperature resistance, higher voltage rating, higher switching frequency, higher power density, lower power transmission loss, and better stability, and are widely used in application scenarios where silicon-based power devices are difficult to adapt to.

[0003] Existing structures typically employ planar layouts and wire bonding, resulting in larger module sizes, longer current conduction paths, increased parasitic inductance and resistance, and electromagnetic interference that affects module performance. Furthermore, SiC MOSFETs are susceptible to overcurrent during application. Under conditions such as circuit faults (e.g., short circuits) or sudden load changes, the current flowing through the device exceeds its rated current value, causing the device to experience significant current stress and generate excessive heat. The strongest local hot spots are generated when the overcurrent flows through the conductive channel, and the thermo-mechanical stress near the conductive channel increases sharply. High temperatures can melt the metal, leading to a short circuit between the gate and source. If the overcurrent conduction path and the excessively high thermo-mechanical stress are not controlled, the device will be damaged.

[0004] To address this, a SiC MOSFET device with an overcurrent-resistant dual flexible buffer layer is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide an overcurrent-resistant SiC MOSFET device with a dual flexible buffer layer package to solve the above-mentioned problems.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] An overcurrent resistant dual flexible buffer layer packaged SiC MOSFET device includes a SiC MOSFET chip, an upper buffer layer is disposed above the SiC MOSFET chip, and an upper DBC substrate is disposed above the upper buffer layer.

[0008] A lower buffer layer is disposed below the SiC MOSFET chip, and a lower DBC substrate is disposed below the lower buffer layer.

[0009] Preferably, the upper buffer layer includes a third region and a fourth region. The third region is disposed vertically and vertically corresponding to the gate panel of the SiC MOSFET chip, and the fourth region is disposed vertically and vertically corresponding to the source panel of the SiC MOSFET chip. The third region and the fourth region are separated by an isolation structure, which is an upper buffer layer diamond block.

[0010] Preferably, the fourth region includes multiple upper buffer layer molybdenum pillars, which are arranged in an array and are tangentially positioned between adjacent upper buffer layer molybdenum pillars. An upper buffer layer graphene pillar is inserted into the gap formed by the multiple upper buffer layer molybdenum pillars, and the upper buffer layer graphene pillar is tangentially positioned to the upper buffer layer molybdenum pillar. The third region has the same structure as the fourth region, and the axes of the upper buffer layer molybdenum pillars and the upper buffer layer graphene pillars are arranged parallel to each other. The gaps formed between the upper buffer layer diamond block, the upper buffer layer molybdenum pillar, and the upper buffer layer graphene pillar are filled with a high-temperature resistant material.

[0011] Preferably, the upper DBC substrate includes an upper Si3N4 substrate, the top surface of the upper Si3N4 substrate is covered with an upper copper cladding layer of the upper DBC substrate, the bottom surface of the upper Si3N4 substrate is covered with a lower copper cladding layer of the upper DBC substrate, and a source terminal and a gate terminal are connected to one side of the lower copper cladding layer of the upper DBC substrate, and there is no contact between the source terminal and the gate terminal.

[0012] Preferably, the SiC MOSFET chip is connected to the upper buffer layer via an upper chip solder layer, and the upper buffer layer is connected to the upper DBC substrate via an upper DBC substrate solder layer. The upper chip solder layer includes a first region and a second region. The first region is adapted to the gate panel of the SiC MOSFET chip and is arranged vertically and correspondingly. The second region is adapted to the source panel of the SiC MOSFET chip and is arranged vertically and correspondingly. A high-temperature resistant isolation layer is provided between the first region and the second region.

[0013] The upper DBC substrate solder layer has the same structure as the upper chip solder layer.

[0014] Preferably, the lower buffer layer includes a plurality of lower buffer layer molybdenum pillars, which are arranged in an array. Adjacent lower buffer layer molybdenum pillars are tangentially arranged, and lower buffer layer graphene pillars are inserted into the gaps formed between the plurality of lower buffer layer molybdenum pillars. The lower buffer layer graphene pillars are tangentially arranged with the lower buffer layer molybdenum pillars, and the gaps formed between the lower buffer layer molybdenum pillars and the lower buffer layer graphene pillars are filled with a high-temperature resistant material.

[0015] Preferably, the lower DBC substrate includes a lower Si3N4 substrate, the bottom surface of the lower Si3N4 substrate is covered with a lower copper cladding layer of the lower DBC substrate, the top surface of the lower Si3N4 substrate is covered with an upper copper cladding layer of the lower DBC substrate, and a drain terminal is connected to one side of the upper copper cladding layer of the lower DBC substrate.

[0016] Preferably, the SiC MOSFET chip is connected to the lower buffer layer via a lower chip solder layer, and the lower buffer layer is connected to the lower DBC substrate via a lower DBC substrate solder layer. The shape of the lower chip solder layer is adapted to the shape of the lower buffer layer, and the shape of the lower DBC substrate solder layer is adapted to the shape of the lower buffer layer.

[0017] Preferably, the source cylinder of the SiC MOSFET chip is adapted to and corresponds one-to-one with the upper buffer layer molybdenum pillar and the lower buffer layer molybdenum pillar, and the gate cylinder of the SiC MOSFET chip is adapted to and corresponds one-to-one with the upper buffer layer graphene pillar and the lower buffer layer graphene pillar.

[0018] Compared with the prior art, the present invention has the following advantages and technical effects:

[0019] In this invention, an upper buffer layer and a lower buffer layer are respectively disposed on the top and bottom sides of the SiC MOSFET chip. An upper DBC substrate and a lower DBC substrate are disposed on the sides of the upper and lower buffer layers that are far apart from each other. These components provide excellent thermal conductivity and electrical performance while ensuring thermomechanical reliability. This better dissipates the heat generated by the SiC MOSFET chip, reducing its temperature and improving the reliability of the power module. Furthermore, the double-sided heat dissipation structure eliminates wire bonding and uses the upper and lower buffer layers to handle current flow, significantly reducing the module's parasitic inductance and size. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is an overall schematic diagram from a first perspective of the present invention;

[0022] Figure 2 This is an overall schematic diagram from a second perspective of the present invention;

[0023] Figure 3This is a schematic diagram of the structure of the upper DBC substrate in this invention;

[0024] Figure 4 This is a schematic diagram of the lower DBC substrate structure in this invention;

[0025] Figure 5 This is a schematic diagram of the upper chip solder layer in this invention;

[0026] Figure 6 This is a schematic diagram of the upper buffer layer in this invention;

[0027] Figure 7 This is a schematic diagram of the lower buffer layer in this invention;

[0028] Figure 8 This is an overall schematic diagram of the SiC MOSFET chip in this invention;

[0029] Figure 9 This is a schematic diagram of the SiC MOSFET chip structure in this invention;

[0030] Figure 10 This is a schematic diagram of the gate cylinder structure in this invention;

[0031] Figure 11 This is a schematic diagram of the source electrode cylinder in this invention;

[0032] Figure 12 This is a schematic diagram of the gate-source interlayer structure in this invention;

[0033] Figure 13 This is a schematic diagram of the terminal block in this invention;

[0034] The components include: 1. Copper layer on the upper DBC substrate; 2. Upper Si3N4 substrate; 3. Copper layer below the upper DBC substrate; 4. Solder layer on the upper DBC substrate; 5. Upper buffer layer; 6. Upper chip solder layer; 7. SiC MOSFET chip; 8. Lower chip solder layer; 9. Lower buffer layer; 10. Lower DBC substrate solder layer; 11. Upper copper layer on the lower DBC substrate; 12. Lower Si3N4 substrate; 13. Lower copper layer on the lower DBC substrate; 14. Source terminal; 15. Gate terminal; 16. Drain terminal; 17. High-temperature isolation layer; 18. Upper buffer layer molybdenum pillar; 19. Upper buffer layer graphene pillar; 20. Upper buffer layer diamond block; 21. Lower buffer layer molybdenum pillar; 22. Lower buffer layer graphene pillar; 23. Gate panel; 24. Source panel; 25. Gate connection layer; 26. Source connection layer; 27. Source metal; 28. Gate metal; 29. ​​Junction termination; 30. SiC epitaxial layer; 31. SiC substrate layer; 32. Drain metal; 33. Polyimide layer; 34. SiO2 layer; 35. N +Region; 36, P-body region; 37, panel isolation layer; 38, source cylinder; 39, gate cylinder; 40, gate-source interlayer. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Some related terminology explanations: In SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) chips, N... + The region is a semiconductor region with high n-type doping (electrons are the majority carriers). The semiconductor material is SiC, and n-type doping is common knowledge in the semiconductor field.

[0038] The p-body region is the main region of p-type doping. The material is SiC. P-type doping is common knowledge in the semiconductor field.

[0039] Silicon nitride is an inorganic compound with the chemical formula Si3N4.

[0040] DBC (Direct Copper Clad) is a composite substrate made by directly sintering copper foil onto the surface of Si3N4 ceramic at high temperature using a hot-melt bonding method.

[0041] Figure 10 SiC epitaxial layer 30, Figure 11 SiC epitaxial layer 30, Figure 12 SiC epitaxial layer 30, Figure 13 The SiC epitaxial layer 30 in the middle belongs to the application of the same material and / or structure of the component in different locations;

[0042] Figure 10 SiC substrate layer 31 Figure 11 SiC substrate layer 31 Figure 12 SiC substrate layer 31 Figure 13 The SiC substrate layer 31 in the middle belongs to the application of components of the same material and / or structure in different locations;

[0043] Figure 10 Drain metal 32 in Figure 11 Drain metal 32 in Figure 12 The drain metal 32 in the middle belongs to the application of components of the same material and / or structure in different locations;

[0044] Figure 11 N in + Area 35 Figure 12 N in + Area 35 refers to the application of components of the same material and / or structure in different locations;

[0045] Figure 11 P-body region 36 Figure 12 The P-body area in the text refers to the application of components of the same material and / or structure in different locations;

[0046] Reference Figures 1 to 13 The present invention discloses an overcurrent resistant dual flexible buffer layer packaged SiC MOSFET device, including a SiC MOSFET chip 7, an upper buffer layer 5 disposed above the SiC MOSFET chip 7, and an upper DBC substrate disposed above the upper buffer layer 5.

[0047] A lower buffer layer 9 is disposed below the SiC MOSFET chip 7, and a lower DBC substrate is disposed below the lower buffer layer 9.

[0048] The upper and lower DBC substrates serve to dissipate heat, provide mechanical support and mechanical isolation, and also provide electrical connection and electrical isolation.

[0049] In one feasible solution, the upper buffer layer 5 includes a third region and a fourth region. The third region is vertically and vertically aligned with the gate panel 23 of the SiC MOSFET chip 7, and the fourth region is vertically and vertically aligned with the source panel 24 of the SiC MOSFET chip 7. The third region and the fourth region are separated by an isolation structure, which is the upper buffer layer diamond block 20.

[0050] In one feasible scheme, the fourth region includes multiple upper buffer layer molybdenum pillars 18, which are arranged in an array and are tangential to each other. Upper buffer layer graphene pillars 19 are inserted into the gaps formed by the multiple upper buffer layer molybdenum pillars 18, and are tangential to the upper buffer layer molybdenum pillars 18. The third region has the same structure as the fourth region, with the axes of the upper buffer layer molybdenum pillars 18 and the upper buffer layer graphene pillars 19 arranged parallel to each other. The gaps formed between the upper buffer layer diamond block 20, the upper buffer layer molybdenum pillars 18, and the upper buffer layer graphene pillars 19 are filled with high-temperature resistant material.

[0051] In one feasible solution, the upper DBC substrate includes an upper Si3N4 substrate 2, the top surface of the upper Si3N4 substrate 2 is covered with an upper copper cladding layer 1, the bottom surface of the upper Si3N4 substrate 2 is covered with a lower copper cladding layer 3, and a source terminal 14 and a gate terminal 15 are connected to one side of the lower copper cladding layer 3, with no contact between the source terminal 14 and the gate terminal 15.

[0052] The upper substrate copper layer 3 and the upper DBC substrate copper layer 1 are respectively covered on the upper and lower surfaces of the upper Si3N4 substrate 2. The substrate is heated to a set temperature, generally between 850°C and 1050°C. Under high temperature conditions, the copper and ceramic substrates form a metal-ceramic bond through diffusion bonding.

[0053] In one feasible solution, the SiC MOSFET chip 7 is connected to the upper buffer layer 5 through the upper chip solder layer 6, and the upper buffer layer 5 is connected to the upper DBC substrate through the upper DBC substrate solder layer 4. The upper chip solder layer 6 includes a first region and a second region. The first region is adapted to the gate panel 23 of the SiC MOSFET chip 7 and is arranged vertically and vertically. The second region is adapted to the source panel 24 of the SiC MOSFET chip 7 and is arranged vertically and vertically. A high-temperature resistant isolation layer 17 is provided between the first region and the second region.

[0054] The high-temperature resistant isolation layer 17 is made of high-temperature resistant epoxy resin material; the function of the high-temperature resistant isolation layer 17 is to isolate the gate and the source.

[0055] The panel isolation layer 37 is SiO2.

[0056] The upper DBC substrate solder layer 4 and the upper chip solder layer 6 have the same structure.

[0057] In one feasible scheme, the lower buffer layer 9 includes a plurality of lower buffer layer molybdenum pillars 21, which are arranged in an array. Adjacent lower buffer layer molybdenum pillars 21 are tangentially arranged. Lower buffer layer graphene pillars 22 are inserted into the gaps formed between the plurality of lower buffer layer molybdenum pillars 21. The lower buffer layer graphene pillars 22 are tangentially arranged with the lower buffer layer molybdenum pillars 21. The gaps formed between the lower buffer layer molybdenum pillars 21 and the lower buffer layer graphene pillars 22 are filled with a high-temperature resistant material.

[0058] The high-temperature resistant material used in this application is high-temperature resistant epoxy resin.

[0059] In one feasible embodiment, the lower DBC substrate includes a lower Si3N4 substrate 12, the bottom surface of the lower Si3N4 substrate 12 is covered with a lower copper cladding layer 13 of the lower DBC substrate, the top surface of the lower Si3N4 substrate 12 is covered with a upper copper cladding layer 11 of the lower DBC substrate, and a drain terminal 16 is connected to one side of the upper copper cladding layer 11 of the lower DBC substrate.

[0060] In one feasible solution, the SiC MOSFET chip 7 is connected to the lower buffer layer 9 via a lower chip solder layer 8, and the lower buffer layer 9 is connected to the lower DBC substrate via a lower DBC substrate solder layer 10. The shapes of the lower chip solder layer 8 and the lower buffer layer 9 are adapted to each other, and the shapes of the lower DBC substrate solder layer 10 and the lower buffer layer 9 are adapted to each other.

[0061] The upper substrate solder layer 4, the upper chip solder layer 6, the lower chip solder layer 8, and the lower DBC substrate solder layer 10 are all made of nano-silver solder.

[0062] In one feasible scheme, the source cylinder 38 of the SiC MOSFET chip 7 is adapted to and corresponds one-to-one with the upper buffer layer molybdenum cylinder 18 and the lower buffer layer molybdenum cylinder 21, and the gate cylinder 39 of the SiC MOSFET chip 7 is adapted to and corresponds one-to-one with the upper buffer layer graphene cylinder 19 and the lower buffer layer graphene cylinder 22.

[0063] The dimensions of the copper layer 11 on the lower DBC substrate, the copper layer 13 on the lower DBC substrate, the copper layer 1 on the upper DBC substrate, and the copper layer 3 on the upper substrate are preferably 10mm × 9mm × 0.3mm.

[0064] The dimensions of the lower Si3N4 substrate and the upper Si3N4 substrate are preferably 10mm × 9mm × 0.65mm;

[0065] The dimensions of the upper substrate solder layer 4, the upper chip solder layer 6, the lower DBC substrate solder layer 10, and the lower chip solder layer 8 are preferably 2.7mm × 2.7mm × 0.1mm;

[0066] The dimensions of the upper buffer layer 5 and the lower buffer layer 9 are preferably 2.7mm × 2.7mm × 1mm;

[0067] The preferred dimensions of the SiC MOSFET chip are 2.8mm × 2.8mm × 0.377mm;

[0068] The preferred dimensions of the source terminal 14, gate terminal 15, and drain terminal 16 are 2mm×0.3mm×0.1mm and 3mm×1.5mm×0.1mm, respectively.

[0069] The SiC MOSFET chip 7 includes a gate panel 23, a source panel 24, a gate interconnect layer 25, a source interconnect layer 26, a source cylinder 38, a gate cylinder 39, a junction terminator 29, a SiC epitaxial layer 30, a SiC substrate layer 31, a drain metal 32, and a polyimide layer 33. The drain metal 32 is located below and connected to the SiC substrate layer 31. The SiC epitaxial layer 30 is located above and connected to the SiC substrate layer 31.

[0070] The polyimide layer 33 is located above the junction terminal 29 and is shaped to match it. Each row of gate cylinders 39 is connected and short-circuited together by a vertically rectangular gate connection layer 25 above. All vertical gate connection layers 25 are connected and short-circuited together by two horizontally rectangular gate connection layers 25. The horizontal gate connection layers 25 below the gate panel 23 are connected and short-circuited together by a circular gate connection layer 25 protrusion. Each row of source cylinders 38 is connected and short-circuited together by a vertically rectangular source connection layer 26 above. The source connection layer 26 is connected to the source panel 24 above, and the height of the upper surface of the source connection layer 26 is the same as the height of the upper surface of the horizontal gate connection layer 25 protrusion. The gate connection layer 25 and the source connection layer 26 are not in contact.

[0071] The gate connection layer 25, source connection layer 26, source cylinder 38, and gate cylinder 39 are arranged vertically and are at the same height as the top surface of the junction terminal 29.

[0072] The outer edge of the source panel 24 is circumferentially covered by a panel isolation layer 37, and the gate panel 23 is located at the inner edge of the panel isolation layer 37. The gate panel 23, the source panel 24 and the panel isolation layer 37 are located on the same plane.

[0073] Source cylinder 38 includes, from top to bottom, source metal 27 and N. + Region 35, P-body region 36, SiC epitaxial layer 30, SiC substrate layer 31, drain metal 32, source metal 27, N + Region 35, P-body region 36, SiC epitaxial layer 30, SiC substrate layer 31, and drain metal 32 are all cylindrical structures with the same upper plane shape and two adjacent surfaces are tightly attached.

[0074] From top to bottom, the gate cylinder 39 consists of gate metal 28, SiO2 layer 34, SiC epitaxial layer 30, SiC substrate layer 31, and drain metal 32. The SiO2 layer 34 has a cylindrical structure. The SiO2 layer 34 and the lower half of the gate metal 28 can be tightly fitted together. The two adjacent surfaces of the SiO2 layer 34, SiC epitaxial layer 30, SiC substrate layer 31, and source metal 27 are tightly attached. The upper plane of the SiO2 layer 34 is higher than the upper plane of the source cylinder 38.

[0075] The structure of the gate-source interlayer 40, from top to bottom, consists of N + Region 35, P-body region 36, SiC epitaxial layer 30, SiC substrate layer 31, drain metal 32, N +The contact areas of region 35, P-body region 36, SiC epitaxial layer 30, SiC substrate layer 31, and drain metal 32 are equal, and two adjacent surfaces are tightly bonded together.

[0076] The structure of the terminal 29, from top to bottom, consists of a SiC epitaxial layer 30 and a SiC substrate layer 31. Both the SiC epitaxial layer 30 and the SiC substrate layer 31 are square-ring hollow cuboids with two adjacent surfaces tightly bonded together.

[0077] Each portion of the gate cylinder 39 is connected to the gate interconnect layer 25, and the gate panel 23 is short-circuited to the gate interconnect layer 25 via a protrusion. Each of the source cylinders 38 is connected to the source interconnect layer 26, which is connected to the upper source panel 24. The height of the upper plane of the source interconnect layer 26 is the same as the height of the upper plane of the lateral protrusion of the gate interconnect layer 25. The gate interconnect layer 25 and the source interconnect layer 26 are not in contact at any viewing angle.

[0078] The polyimide layer 33 is above the junction terminal 29 and below the panel isolation layer 37. The polyimide layer 33 is a hollow cuboid with a bottom area equal to the bottom area of ​​the junction terminal 29. The lower plane of the polyimide layer 33 is tightly attached to the upper plane of the junction terminal 29 in a tangential manner.

[0079] The device structure of this invention has a uniform overcurrent shunt path: the source metal 27 in the SiC MOSFET chip 7 is respectively disposed corresponding to the upper buffer layer molybdenum pillar 18 and the lower buffer layer molybdenum pillar 21, and the diameters of the upper buffer layer molybdenum pillar 18, the lower buffer layer molybdenum pillar 21 and the source metal 27 are the same; the gate metal 28 of the SiC MOSFET chip 7 is respectively disposed corresponding to the upper buffer layer graphene pillar 19 and the lower buffer layer graphene pillar 22, and the diameters of the upper buffer layer graphene pillar 19, the lower buffer layer graphene pillar 22 and the gate metal 28 are the same. This arrangement ensures that when an overcurrent occurs, the current in the upper buffer layer 5, the SiC MOSFET chip 7 and the lower buffer layer 9 is uniformly distributed; and when the device overheats, the thermo-mechanical stress is uniformly distributed to each region of the upper buffer layer 5, the SiC MOSFET chip 7 and the lower buffer layer 9, alleviating stress concentration at a certain local hot spot.

[0080] The device structure of this invention has a unique thermo-mechanical stress buffering mechanism: the upper buffer layer molybdenum pillar 18 above the source cylinder 38 and gate cylinder 39, and the lower buffer layer molybdenum pillar 21 below the source metal 27 have their upper and lower edges aligned, and the top view pattern is a circle of the same shape. The upper and lower edges of the gate cylinder 39, the upper buffer layer graphene pillar 19 above the gate cylinder 39, and the lower buffer layer graphene pillar 22 below the gate cylinder 39 are aligned, and the top view pattern is a circle of the same shape.

[0081] The SiO2 layer 34 below the gate cylinder 39 is the point where the thermo-mechanical stress is most concentrated when an overcurrent occurs. The upper buffer layer graphene pillar 19 of the upper buffer layer 5 and the lower buffer layer graphene pillar 22 of the lower buffer layer 9 are directly opposite the SiO2 layer 34, so that the graphene can directly share, buffer and bear the thermo-mechanical stress from the source cylinder 38, and alleviate the melting of the gate metal 28 in the SiO2 layer 34 and the source panel 24 above the gate cylinder 39.

[0082] The upper buffer layer molybdenum pillar 18 of the upper buffer layer 5 and the lower buffer layer molybdenum pillar 21 of the lower buffer layer 9 are directly opposite the source cylinder 38, so that the overcurrent can flow out of the source terminal 14 and the drain terminal 16 through the upper buffer layer 5 and the lower buffer layer 9 respectively with the shortest current path, thus dissipating the overcurrent with less power consumption. In addition, the upper buffer layer graphene pillar 19, the gate cylinder 39 inside the SiC MOSFET chip 7, and the lower buffer layer graphene pillar 22 are tangent to the four upper buffer layer molybdenum pillars 18 in the upper buffer layer 5, the four source cylinders 38 inside the SiC MOSFET chip 7, and the four lower buffer layer molybdenum pillars 21 in the lower buffer layer 9, respectively. During overcurrent, thermal stress is conducted from the SiCMOSFET chip 7 to the upper buffer layer molybdenum pillar 18 and the lower buffer layer molybdenum pillar 21, causing abnormal pressure between the molybdenum pillars and the gate panel 23 below them under thermal stress. Due to the close and uniform arrangement of the molybdenum pillars and graphene pillars, the graphene can alleviate the thermal and mechanical stress of the molybdenum pillars around it. With the gate cylinder 39 and the upper buffer layer graphene pillar 19 aligned vertically, and the upper buffer layer molybdenum pillar 18 and the source metal 27 aligned vertically, the gate connection layer 25 and the source connection layer 26 can respectively short-circuit the dispersed source cylinder 38 and the gate cylinder 39, so that the dispersed gate cylinder 39 is connected to the gate panel 23, and the dispersed source cylinder 38 is connected to the source panel 24.

[0083] The device structure of this invention exhibits electromagnetic interference (EMI) immunity. The double-sided heat dissipation package eliminates wire bonding, and the source metal 27, the upper buffer layer molybdenum pillar 18 of the upper buffer layer 5, and the lower buffer layer molybdenum pillar 21 of the lower buffer layer 9 are vertically aligned, allowing current to reach the source terminal 14 and the drain terminal 16 via the shortest path, reducing parasitic inductance and resistance. The graphene pillars possess excellent electromagnetic shielding capabilities, further reducing parasitic inductance and suppressing EMI.

[0084] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0085] The above embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A SiC MOSFET device with an overcurrent-resistant dual flexible buffer layer package, comprising a SiC MOSFET chip (7), characterized in that, An upper buffer layer (5) is disposed above the SiC MOSFET chip (7), and an upper DBC substrate is disposed above the upper buffer layer (5). A lower buffer layer (9) is disposed below the SiC MOSFET chip (7), and a lower DBC substrate is disposed below the lower buffer layer (9). The upper buffer layer (5) includes a third region and a fourth region. The third region is disposed vertically and vertically corresponding to the gate panel (23) of the SiC MOSFET chip (7). The fourth region is disposed vertically and vertically corresponding to the source panel (24) of the SiC MOSFET chip (7). The third region and the fourth region are separated by an isolation structure, which is an upper buffer layer diamond block (20). The fourth region includes multiple upper buffer layer molybdenum pillars (18), which are arranged in an array. Adjacent upper buffer layer molybdenum pillars (18) are tangentially arranged. Upper buffer layer graphene pillars (19) are inserted into the gaps formed by the multiple upper buffer layer molybdenum pillars (18). The upper buffer layer graphene pillars (19) are tangentially arranged with the upper buffer layer molybdenum pillars (18). The third region has the same structure as the fourth region. The axes of the upper buffer layer molybdenum pillars (18) and the upper buffer layer graphene pillars (19) are arranged parallel to each other. The gaps formed between the upper buffer layer diamond block (20), the upper buffer layer molybdenum pillars (18), and the upper buffer layer graphene pillars (19) are filled with high-temperature resistant material. The lower buffer layer (9) includes a plurality of lower buffer layer molybdenum pillars (21), which are arranged in an array. Adjacent lower buffer layer molybdenum pillars (21) are tangentially arranged. Lower buffer layer graphene pillars (22) are inserted into the gaps formed between the plurality of lower buffer layer molybdenum pillars (21). The lower buffer layer graphene pillars (22) are tangentially arranged with the lower buffer layer molybdenum pillars (21). The gaps formed between the lower buffer layer molybdenum pillars (21) and the lower buffer layer graphene pillars (22) are filled with high-temperature resistant material.

2. The SiC MOSFET device with overcurrent resistant dual flexible buffer layer package according to claim 1, characterized in that: The upper DBC substrate includes an upper Si3N4 substrate (2), the top surface of the upper Si3N4 substrate (2) is covered with an upper copper layer (1) of the upper DBC substrate, the bottom surface of the upper Si3N4 substrate (2) is covered with a lower copper layer (3) of the upper DBC substrate, and a source terminal (14) and a gate terminal (15) are connected to one side of the lower copper layer (3) of the upper DBC substrate. There is no contact between the source terminal (14) and the gate terminal (15).

3. The SiC MOSFET device with overcurrent resistant dual flexible buffer layer package according to claim 1, characterized in that: The SiC MOSFET chip (7) is connected to the upper buffer layer (5) through the upper chip solder layer (6). The upper buffer layer (5) is connected to the upper DBC substrate through the upper DBC substrate solder layer (4). The upper chip solder layer (6) includes a first region and a second region. The first region is adapted to the gate panel (23) of the SiC MOSFET chip (7) and is arranged vertically and vertically. The second region is adapted to the source panel (24) of the SiC MOSFET chip (7) and is arranged vertically and vertically. A high-temperature resistant isolation layer (17) is provided between the first region and the second region. The upper DBC substrate solder layer (4) has the same structure as the upper chip solder layer (6).

4. The SiC MOSFET device with overcurrent resistant dual flexible buffer layer package according to claim 1, characterized in that: The lower DBC substrate includes a lower Si3N4 substrate (12), the bottom surface of the lower Si3N4 substrate (12) is covered with a lower copper cladding layer (13) of the lower DBC substrate, the top surface of the lower Si3N4 substrate (12) is covered with a lower copper cladding layer (11) of the lower DBC substrate, and a drain terminal (16) is connected to one side of the lower copper cladding layer (11).

5. The SiC MOSFET device with overcurrent resistant dual flexible buffer layer package according to claim 1, characterized in that: The SiC MOSFET chip (7) is connected to the lower buffer layer (9) through a lower chip solder layer (8), and the lower buffer layer (9) is connected to the lower DBC substrate through a lower DBC substrate solder layer (10). The shape of the lower chip solder layer (8) is adapted to that of the lower buffer layer (9), and the shape of the lower DBC substrate solder layer (10) is adapted to that of the lower buffer layer (9).

6. The SiC MOSFET device with overcurrent resistant dual flexible buffer layer package according to claim 1, characterized in that: The source cylinder (38) of the SiC MOSFET chip (7) is adapted to and corresponds one-to-one with the upper buffer layer molybdenum cylinder (18) and the lower buffer layer molybdenum cylinder (21), and the gate cylinder (39) of the SiC MOSFET chip (7) is adapted to and corresponds one-to-one with the upper buffer layer graphene cylinder (19) and the lower buffer layer graphene cylinder (22).

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