Semiconductor devices and their fabrication methods

By incorporating two gates and a regulation structure in the MOSFET device, the problems of inrush current and high on-resistance are solved, resulting in better switching performance and reliability, while reducing losses and the risk of heat accumulation.

CN120547913BActive Publication Date: 2026-03-13BEIJING ZHONGKE XINWEITE SCI & TECH DEV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-07-24
Publication Date
2026-03-13

AI Technical Summary

Technical Problem

Metal-oxide-semiconductor field-effect transistors (MOSFETs) generate surge currents during high-frequency switching, which can damage other components in the circuit and result in high on-resistance.

Method used

By setting two gates and a regulating structure in a semiconductor device, voltage surges can be suppressed, on-resistance can be reduced, the size of the diffusion region can be increased to mitigate surge current, and the electric field distribution can be optimized by adjusting the amount of gate-drain charge in the diffusion region.

Benefits of technology

It effectively suppresses surge current, reduces on-resistance, improves device reliability, reduces switching losses, lowers the probability of heat-induced burnout, and enhances switching performance.

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Abstract

This application discloses a semiconductor device and its fabrication method. The semiconductor device includes a substrate, an epitaxial layer, a well region, a source region, a source electrode, a control electrode, and a first insulating layer. The epitaxial layer is disposed on one side of the substrate along the thickness direction. The well region is located within the epitaxial layer, and the conductivity type of the well region is opposite to that of the epitaxial layer. The source region is located within the well region, and the conductivity type of the source region is the same as that of the epitaxial layer. The source electrode is located on the side of the epitaxial layer facing away from the substrate, and the source electrode is electrically connected to the source region. The control electrode is located on the side of the epitaxial layer facing away from the substrate, and the control electrode includes two gates spaced apart along a first direction and an adjustment structure located between the two gates. The adjustment structure is insulated from the gates and electrically connected to the source electrode. The first insulating layer is sandwiched between the control electrode and the epitaxial layer. The epitaxial layer includes a diffusion region located between two adjacent well regions along the first direction, and the orthographic projection of the adjustment structure on the substrate falls within the orthographic projection range of the diffusion region on the substrate.
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Citation Information

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