Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes a first gate signal line, a second gate signal line, a first gate driving unit and a second gate driving unit, the first gate driving unit and the second gate driving unit each including a buffer unit, the buffer unit including a first transistor, a second transistor and an output electrode outputting a gate control signal, a first electrode of the first transistor and a first electrode of the second transistor being connected with the output electrode, a pixel circuit being electrically connected with the output electrode of the buffer unit, the pixel circuit including an odd row pixel group and an even row pixel group, a second electrode of the first transistor included in the first gate driving unit being connected with the first gate signal line, so that the first gate driving unit provides the odd row pixel group with the gate control signal, and a second electrode of the first transistor included in the second gate driving unit being connected with the second gate signal line, so that the second gate driving unit provides the even row pixel group with the gate control signal.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] The existing gate drive circuit uses a shared gate signal line to provide signals to the gate. The output load of adjacent rows can cause significant noise in the signal on the gate signal line. In a panel with a 1-drive-2 design, the noise in a 2-row cycle can cause charging differences between odd and even rows of pixels, resulting in brightness differences between odd and even rows and causing uneven display effects.

[0003] The information disclosed in this section is only for understanding the background of the technical concept of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, comprising: gate signal lines, including a first gate signal line and a second gate signal line, each of the first gate signal line and the second gate signal line being applied with a first voltage, the first gate signal line and the second gate signal line being spaced apart from each other; a first gate driving unit and a second gate driving unit, each of the first gate driving unit and the second gate driving unit including a buffer unit, the buffer unit including a first transistor, a second transistor, and an output electrode for outputting a gate control signal; a first electrode of the first transistor and the first electrode of the second transistor being connected to the output electrode, the second electrode of the first transistor being connected to the gate signal line; and a pixel circuit electrically connected to the output electrode of the buffer unit, the pixel circuit including odd-numbered rows of pixel groups and even-numbered rows of pixel groups, the pixel groups including at least two rows of pixel circuits; the first gate signal line being connected to the second electrode of the first transistor included in the first gate driving unit, so that the first gate driving unit provides a gate control signal to the odd-numbered rows of pixel groups, and the second gate signal line being connected to the second electrode of the first transistor included in the second gate driving unit, so that the second gate driving unit provides a gate control signal to the even-numbered rows of pixel groups.

[0005] In some exemplary embodiments of this disclosure, the display substrate further includes: a reference gate signal line, the reference gate signal line being subjected to a second voltage, and the reference gate signal line being connected to the second terminal of the second transistor included in the buffer unit.

[0006] In some exemplary embodiments of this disclosure, both the first gate driving unit and the second gate driving unit further include a scanning unit, which is connected to the gate signal line.

[0007] In some exemplary embodiments of this disclosure, the scanning unit in the first gate driving unit is electrically connected to the first gate signal line; the scanning unit in the second gate driving unit is electrically connected to the second gate signal line.

[0008] In some exemplary embodiments of this disclosure, the scanning unit in the first gate driving unit is electrically connected to the second gate signal line; the scanning unit in the second gate driving unit is electrically connected to the first gate signal line.

[0009] In some exemplary embodiments of this disclosure, the gate signal line further includes a third gate signal line, the third gate signal line being applied with the first voltage, the third gate signal line being spaced apart from the first gate signal line and the second gate signal line; the third gate signal line is connected to a scan serial element in the first gate driving unit, and the third gate signal line is connected to a scan unit in the second gate driving unit.

[0010] In some exemplary embodiments of this disclosure, the reference gate signal line is connected to the scan unit in the first gate driving unit, and the reference gate signal line is connected to the scan unit in the second gate driving unit.

[0011] In some exemplary embodiments of this disclosure, the gate signal line includes: a first connection point where the first gate signal line is connected to the first gate driving unit; a second connection point where the second gate signal line is connected to the second gate driving unit; and / or a third connection point where the third gate signal line is connected to the first gate driving unit or the second gate driving unit; and a short-circuit connection point on the gate signal line away from the first connection point, the second connection point and / or the third connection point, so as to short-circuit the first gate signal line, the second gate signal line and / or the third gate signal line.

[0012] In some exemplary embodiments of this disclosure, a voltage-stabilizing capacitor connected to the first gate signal line, the second gate signal line, and / or the third gate signal line is provided at a position on the gate signal line away from the first connection point, the second connection point, and / or the third connection point.

[0013] In some exemplary embodiments of this disclosure, the voltage-stabilizing capacitor is disposed between the first connection point, the second connection point, and / or the third connection point and the short-circuit connection point.

[0014] In some exemplary embodiments of this disclosure, the voltage-stabilizing capacitor includes: a first voltage-stabilizing capacitor connected to the first gate signal line; a second voltage-stabilizing capacitor connected to the second gate signal line; and / or a third voltage-stabilizing capacitor connected to the third gate signal line.

[0015] In some exemplary embodiments of this disclosure, the short-circuit connection point is located at the edge of the display area of ​​the display substrate; or the short-circuit connection point is located in the flexible circuit board included in the display substrate; or the short-circuit connection point is located in the driver integrated circuit included in the display substrate.

[0016] In some exemplary embodiments of this disclosure, the voltage-stabilizing capacitor is disposed within the flexible circuit board included in the display substrate.

[0017] In some exemplary embodiments of this disclosure, the first gate signal line includes at least two lines, and the second gate signal line includes at least two lines.

[0018] In some exemplary embodiments of this disclosure, each pixel group in the pixel circuit includes a first row of pixel circuits and a second row of pixel circuits arranged in parallel, the first row of pixel circuits and the second row of pixel circuits including a common N-type gate; the first row of pixel circuits further includes a first P-type gate, and the second row of pixel circuits includes a second P-type gate.

[0019] In some exemplary embodiments of this disclosure, the output electrode includes a first output electrode, a second output electrode, and a third output electrode; the first output electrode is connected to the N-type gate and provides a first gate signal to the N-type gate; the second output electrode is connected to the first P-type gate and provides a second gate signal to the first P-type gate; the third output electrode is connected to the second P-type gate and provides a third gate signal to the second P-type gate.

[0020] In some exemplary embodiments of this disclosure, the low voltage signal in the second gate signal and the low voltage signal in the third gate signal do not overlap in timing.

[0021] In some exemplary embodiments of this disclosure, the display substrate further includes: a first clock signal line, a second clock signal line, an initial signal line, and a control signal line connected to the scanning unit.

[0022] In some exemplary embodiments of this disclosure, when the first gate signal line provides a gate control signal for the pixel group in the odd-numbered rows, and when the second gate signal line provides a gate control signal for the pixel group in the even-numbered rows, the timing of the maximum pull-down potential of the first gate signal line due to load and the timing of the maximum pull-down potential of the second gate signal line due to load do not overlap; the timing of the low voltage signal of the second gate signal and the timing of the low voltage signal of the third gate signal do not overlap with the timing of the maximum pull-down potential of the first gate signal line due to load and the timing of the maximum pull-down potential of the second gate signal line due to load.

[0023] In another aspect of this disclosure, a display device is provided, including the display substrate described above. Attached Figure Description

[0024] The features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0025] Figure 1A This is a block diagram of a GOA display substrate in the prior art;

[0026] Figure 1B yes Figure 1A A schematic diagram of the gate drive unit in the diagram;

[0027] Figure 2 This is a block diagram of a display substrate according to an embodiment of the present disclosure;

[0028] Figure 3A This is a schematic diagram showing the connection between the first gate signal line, the second gate signal line, and the first gate driving unit and the second gate driving unit of a display substrate according to an embodiment of the present disclosure.

[0029] Figure 3B This is a schematic diagram showing the connection between the first gate signal line, the second gate signal line, and the first gate driving unit and the second gate driving unit of a display substrate according to another embodiment of the present disclosure.

[0030] Figure 3C This is a schematic diagram showing the connection between the first gate signal line, the second gate signal line, the third gate signal line of a display substrate and the first gate driving unit and the second gate driving unit according to an embodiment of the present disclosure.

[0031] Figure 4A This is a schematic diagram of a short-circuit connection between the first gate signal line and the second gate signal line according to an embodiment of the present disclosure;

[0032] Figure 4B This is a schematic diagram of a short-circuit connection between the first gate signal line and the second gate signal line according to another embodiment of the present disclosure;

[0033] Figure 4C This is a schematic diagram showing a short-circuit connection between the first gate signal line and the second gate signal line according to another embodiment of the present disclosure;

[0034] Figure 4D This is a schematic diagram of a short-circuit connection between the first gate signal line and the second gate signal line according to another embodiment of the present disclosure;

[0035] Figure 5A It is based on Figure 3CA schematic diagram showing a short-circuit connection of the first gate signal line, the second gate signal line, and the third gate signal line in one embodiment is shown.

[0036] Figure 5B It is based on Figure 3C A schematic diagram showing the first gate signal line, the second gate signal line, and the third gate signal line short-circuited in another embodiment;

[0037] Figure 5C It is based on Figure 3C A schematic diagram showing the first gate signal line, the second gate signal line, and the third gate signal line short-circuited in another embodiment;

[0038] Figure 5D It is based on Figure 3C A schematic diagram showing the first gate signal line, the second gate signal line, and the third gate signal line short-circuited in another embodiment is shown.

[0039] Figure 6 This is a schematic diagram of the structure of a voltage-stabilizing capacitor according to an embodiment of the present disclosure;

[0040] Figure 7A This is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to an embodiment of the present disclosure;

[0041] Figure 7B This is a schematic diagram showing a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to another embodiment of the present disclosure;

[0042] Figure 7C This is a schematic diagram showing a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to another embodiment of the present disclosure;

[0043] Figure 7D This is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to another embodiment of the present disclosure;

[0044] Figure 8A This is a signal waveform diagram of a display substrate according to an embodiment of the present disclosure, including a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate.

[0045] Figure 8B This is a signal waveform diagram of a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate according to an embodiment of the present disclosure;

[0046] Figure 9AThese are simulation waveforms of the gate control signal on the first gate signal line and the gate control signal on the second gate signal line without a voltage regulator capacitor.

[0047] Figure 9B This is a simulation waveform diagram of the gate control signal on the first gate signal line and the gate control signal on the second gate signal line according to an embodiment of the present disclosure for setting a voltage regulator capacitor;

[0048] Figure 10A This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0049] Figure 10B This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0050] Figure 10C This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0051] Figure 10D This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0052] Figure 10E This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0053] Figure 10F This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0054] Figure 10G This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0055] Figure 10H This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0056] Figure 11 This is a schematic diagram of a display device according to an embodiment of the present disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0058] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0059] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of x, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0060] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0061] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0062] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0063] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0064] In this document, the directional terms "first direction" and "second direction" are used to describe different directions along a pixel region, such as the vertical and horizontal directions of the pixel region, or the row and column directions of the subpixel arrangement. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0065] The transistors used in the embodiments of this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. Since the source and drain of the TFTs used here are symmetrical, their sources and drains can be interchanged. In the embodiments of this disclosure, a transistor may include a gate, a first electrode, and a second electrode, wherein the first electrode may represent one of the source and drain, and the second electrode may represent the other of the source and drain. The following examples primarily describe the case of a P-type TFT used as a driving transistor; other transistors may be of the same or different type as the driving transistor depending on the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type TFT.

[0066] Some exemplary embodiments of this disclosure provide a display substrate, the display substrate comprising: gate signal lines, including a first gate signal line and a second gate signal line, each of the first gate signal line and the second gate signal line being applied with a first voltage, the first gate signal line and the second gate signal line being spaced apart from each other; a first gate driving unit and a second gate driving unit, each of the first gate driving unit and the second gate driving unit including a buffer unit, the buffer unit including a first transistor, a second transistor, and an output electrode for outputting a gate control signal; a first electrode of the first transistor and the first electrode of the second transistor being connected to the output electrode, the second electrode of the first transistor being connected to the gate signal line; a pixel circuit electrically connected to the output electrode of the buffer unit, the pixel circuit including odd-numbered rows of pixel groups and even-numbered rows of pixel groups, the pixel group including at least two rows of pixel circuits; the first gate signal line being connected to the second electrode of the first transistor included in the first gate driving unit, so that the first gate driving unit provides a gate control signal for the odd-numbered rows of pixel groups, the second gate signal line being connected to the second electrode of the first transistor included in the second gate driving unit, so that the second gate driving unit provides a gate control signal for the even-numbered rows of pixel groups.

[0067] In the embodiments of this disclosure, by setting the gate signal line as a first gate signal line connected to the first gate driving unit and a second gate signal line connected to the second gate driving unit, the first gate signal line can provide gate control signals for odd-numbered rows of pixel groups, and the second gate signal line can provide gate control signals for even-numbered rows of pixel groups. This achieves segmented control of the gate control signals, thereby effectively avoiding the problem of uneven display of two rows of pixel circuits within a pixel group caused by noise generated by the gate signal line under load affecting the pixel circuit. This effectively improves the display effect of the display substrate.

[0068] Figure 1A This is a block diagram of a GOA display substrate in the prior art. Figure 1B yes Figure 1A A schematic diagram of the gate drive unit in the diagram.

[0069] like Figure 1A As shown, the existing display substrate includes a display area AA located on the display substrate. In the non-display area NA at the edge of the display area AA, a gate signal line is provided to provide a signal to the gate drive circuit (GOA) that controls each row of pixels. This allows the gate drive circuit to control the gate in the pixel circuit located in the display area AA through the signal output by the output terminal (out), thereby realizing the control of pixel lighting, turning off and brightness.

[0070] like Figure 1A and Figure 1BAs shown, in the existing design, each row of pixels in the display substrate is provided with a signal through a gate driving circuit. Within the display substrate, the gate signal line (VGH) and reference gate signal line (VGL) of different rows of pixels are all shared. One end of the gate signal line and the reference gate signal line are uniformly connected to the flexible circuit board (FPC), and finally connected to the output terminal of the integrated circuit (such as the display driver IC, abbreviated as DDIC, the power management integrated circuit, abbreviated as PMIC, etc.) through the FPC traces.

[0071] like Figure 1B As shown, each row's gate drive circuit also includes multiple clock signal lines, such as the first clock signal line CK, the second clock signal line CB, and a reference gate signal line VGL. The clock signal line CK, gate signal line VGH, and reference gate signal line VGL all use a shared design; the gate signal lines VGH of pixels in different rows are connected to the same gate signal line. When the gate trace in the pixel circuit is charged through the gate signal line, the gate signal line VGH first charges the gate trace through the transistor at the pull-up node. Due to the large instantaneous current, the gate signal line has a load (e.g., a resistive load). At this time, the voltage of the gate signal line VGH is pulled down, generating a pull-down potential, and then returns to the set pull-up voltage. During this process, the voltage on the gate signal line VGH exhibits fluctuating noise. This noise is eventually transmitted to the gate trace in the pixel circuit that is not in a pull-down state, causing noise on the gate trace, which in turn affects the light-emitting state of the pixel unit in the pixel circuit, resulting in local brightness variations.

[0072] When the pixel circuit uses a shared N-type gate to drive the P-type gates of two rows of pixels, the noise states of the corresponding N-type gate signals when the P-type gates of the odd-numbered and even-numbered rows of pixels are turned on will cause differences in the gate signals of the odd-numbered and even-numbered rows. This will eventually result in uneven brightness horizontal stripes in the odd-numbered and even-numbered rows, reducing the display effect of the display substrate.

[0073] To address the aforementioned problems, this disclosure provides a display substrate, which is described below in conjunction with... Figures 2 to 10H The structure of the display substrate according to embodiments of this disclosure will be described.

[0074] Figure 2 This is a block diagram of a display substrate according to an embodiment of the present disclosure.

[0075] Reference Figure 2According to an embodiment of the present disclosure, the display substrate 100 may include a substrate and pixel units disposed on the substrate. The pixel units are arranged along predetermined rows and columns to form a pixel area, for example, arranged along a first direction X and a second direction Y.

[0076] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units are disposed to display images. Each pixel unit will be described later. The non-display area NA is an area where no pixel units are disposed, that is, an area where no images are displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel can be determined based on the width of the non-display area NA.

[0077] The display area AA can have various shapes. For example, the display area AA can be set in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In the embodiments of this disclosure, the display area AA is set as an area having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0078] A non-display area NA may be disposed on at least one side of the display area AA. In embodiments of this disclosure, the non-display area NA may surround the outer periphery of the display area AA. In embodiments of this disclosure, the non-display area NA may include a lateral portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0079] Pixel units are set in the display area AA. A pixel unit is the smallest unit used to display an image, and there can be multiple pixels. For example, a pixel unit may include a light-emitting device that emits white light and / or colored light.

[0080] Pixel units can be configured in multiples, arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units, and pixel units can be arranged in various forms. For example, pixel units can be arranged such that the direction inclined relative to the first direction X and the first direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0081] In other words, multiple pixel units are arranged in an array along the first direction X and the second direction Y to form multiple rows of pixel units and multiple columns of pixel units.

[0082] A pixel unit can include multiple sub-pixels. For example, a pixel unit can include three sub-pixels: a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel.

[0083] It should be noted that in the embodiments of this disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the three mentioned above.

[0084] Each pixel unit is arranged along a set row to form a row of pixels PXL. Each pixel unit has a pixel circuit for controlling the on / off state and brightness of each pixel. Pixel control is achieved through data lines described below and gate signal lines described above. The pixel circuit includes an N-type gate and a P-type gate.

[0085] In this embodiment, two rows of pixels PXL together form a group. For example, the first row of pixels PXL and the second row of pixels PXL form a group, namely pixel group PXU. Each pixel group includes a first row pixel circuit corresponding to the first row of pixels PXL and a second row pixel circuit corresponding to the second row of pixels PXL.

[0086] In some embodiments of this disclosure, the first and second row pixel circuits in two adjacent and parallel rows of pixels PXL include a shared N-type gate. Each row pixel circuit also includes a P-type gate; for example, the first row pixel circuit includes a first P-type gate, and the second row pixel circuit includes a second P-type gate.

[0087] For example, in Figure 2 In the exemplary embodiment shown, scan control signal lines 110 and data lines 120 are schematically illustrated. That is, the display substrate 100 may further include: a plurality of scan control signal lines 110 and a plurality of data lines 120 disposed on the substrate. The plurality of scan control signal lines 110 respectively supply scan control signals to multiple rows of pixel units, i.e., gate control signals output through the output terminals of the first gate driving unit and the second gate driving unit. The plurality of data lines 120 respectively supply data signals to multiple columns of pixel units. The scan control signal lines 110 extend along a first direction X, and the plurality of scan control signal lines 110 are spaced apart along a second direction Y. The data lines 120 extend along the second direction Y, and the plurality of data lines 120 are spaced apart along the first direction X.

[0088] For example, the scan control signal line 110 can be representative of a horizontal trace, and the data line 120 can be representative of a vertical trace. It should be understood that the horizontal trace may also include other types of traces or traces used to supply other signals, and the vertical trace may also include other types of traces or traces used to supply other signals.

[0089] Each subpixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, in an OLED display substrate or display panel, the light-emitting element of a subpixel may include an anode, a light-emitting material layer, and a cathode stacked together. The anodes of the light-emitting elements of each subpixel are spaced apart and arranged in a matrix form along rows extending in a first direction X and columns extending in a first direction Y.

[0090] It should be noted that transistors in pixel circuits can be classified into N-type transistors and P-type transistors based on their semiconductor characteristics. When used as switching transistors, N-type transistors are turned on by a high-level switching signal and turned off by a low-level switching signal. P-type transistors are turned on by a low-level switching signal and turned off by a high-level switching signal.

[0091] In the embodiments of this disclosure, the pixel circuit can employ an LTPO circuit, i.e., an LTPO circuit fabricated using low-temperature polycrystalline silicon (LTPS) technology and indium gallium zinc oxide (IGZO). Low-temperature polycrystalline silicon thin-film transistors (LTPS) use polycrystalline silicon deposition to form the active layer. LTPS has high electron mobility, fast response speed, and advantages such as high brightness, high resolution, and low power consumption. Oxide thin-film transistors (oxide TFTs), for example, use oxide semiconductors as the active layer of the TFT, such as indium gallium zinc oxide (IGZO). Oxide semiconductors have high electron mobility and good turn-off characteristics. Compared to LTPS, oxide semiconductor processes are simpler and have higher compatibility with amorphous silicon processes. Of course, oxide thin-film transistors can also be other metal oxide semiconductors, such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO). Using oxide thin-film transistors can effectively reduce the size of the transistor and prevent leakage current, thereby making the pixel circuit suitable for low-frequency driving while increasing the resolution of the display substrate.

[0092] Figure 3AThis is a schematic diagram showing the connection between the first gate signal line, the second gate signal line, and the first gate driving unit and the second gate driving unit of a display substrate according to an embodiment of the present disclosure. Figure 3B This is a schematic diagram showing the connection between the first gate signal line, the second gate signal line, and the first gate driving unit and the second gate driving unit of a display substrate according to another embodiment of the present disclosure. Figure 3C This is a schematic diagram showing the connection between the first gate signal line, the second gate signal line, the third gate signal line of a display substrate and the first gate driving unit and the second gate driving unit according to an embodiment of the present disclosure.

[0093] The following is combined Figure 2 , Figures 3A to 3C The structure of the display substrate according to embodiments of this disclosure will be described.

[0094] The display substrate 100 includes a gate signal line VGH, a reference gate signal line VGL, a first clock signal line CK, and a second clock signal line CB.

[0095] The gate signal line VGH includes a first gate signal line VGHO and a second gate signal line VGHE. A first voltage V1 is applied to each of the first gate signal line VGHO and the second gate signal line VGHE. The first gate signal line VGHO and the second gate signal line VGHE are spaced apart from each other. For example, the first gate signal line VGHO and the second gate signal line VGHE extend along a second direction Y and are located on the side of the display substrate near the display area AA. A certain distance is provided between the first gate signal line VGHO and the second gate signal line VGHE, thereby separating the first gate signal line VGHO and the second gate signal line VGHE.

[0096] The reference gate signal line VGL and the gate signal line VGH are both disposed on the side of the display substrate near the display area AA, located in the non-display area NA. The reference gate signal line VGL also extends along the second direction Y, and the reference gate signal line VGL and the gate signal line VGH are spaced apart to avoid mutual interference between the signals. A second voltage V2 is applied to the reference gate signal line VGL.

[0097] A first gate driving unit 11 and a second gate driving unit 12 are disposed on the display substrate 100. Both the first gate driving unit 11 and the second gate driving unit 12 include a scanning unit and a buffer unit. The structures of the first gate driving unit 11 and the second gate driving unit 12 can be completely identical. For example, the first gate driving unit 11 includes a scan buffer unit 111 and a scanning unit 112. The second gate driving unit 12 includes a buffer unit 121 and a scanning unit 122.

[0098] In some optional embodiments, the first gate driving unit 11 and / or the second gate driving unit 12 may include one or more gate driving circuits GOA. For example, in this embodiment, the first gate driving unit 11 and the second gate driving unit 12 have the same structure and each includes a gate driving circuit GOA.

[0099] The buffer unit 111 includes a first transistor T1, a second transistor T2, and an output terminal O1 for the output gate control signal. The gate of the first transistor T1 is connected to a pull-up node, and the gate of the second transistor T2 is connected to a pull-down node. The first electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the output terminal O1, and the second electrode of the first transistor T1 is connected to the gate signal line VGH. The second electrode of the second transistor T2 in the buffer unit 111 is connected to the reference gate signal line VGL.

[0100] The display substrate is also provided with pixel circuits, which include a third transistor and a fourth transistor. The third transistor is an N-type transistor. For example, the third transistor is shared by the first row pixel circuit and the second row pixel circuit in a pixel group. The gate of the third transistor is connected to the output of the buffer unit.

[0101] The pixel circuit includes pixel groups PXU in odd-numbered rows and pixel groups PXU in even-numbered rows. For example, both the odd-numbered pixel groups PXU and the even-numbered pixel groups PXU include two rows of pixel circuits PXL.

[0102] In other alternative embodiments, the pixel group PXU may include more rows of pixel circuitry.

[0103] The first gate signal line VGHO is connected to the second electrode of the first transistor T1 included in the first gate driving unit 11, so that the first gate driving unit 11 provides a gate control signal for the odd-numbered row of pixel groups. The second gate signal line VGHE is connected to the second electrode of the first transistor T1 included in the second gate driving unit 12, so that the second gate driving unit 12 provides a gate control signal for the even-numbered row of pixel groups.

[0104] In the embodiments of this disclosure, by separating the first gate signal line VGHO and the second gate signal line VGHE, and providing gate control signals to the odd-numbered pixel groups and the even-numbered pixel groups respectively, the problem of fluctuation interference of the first gate signal line VGHO and the second gate signal line VGHE between odd-numbered and even-numbered rows due to load can be effectively avoided, and the gate control signal between the two rows of pixel circuits in a pixel group can be prevented from being interfered with by noise on the first gate signal line or the second gate signal line.

[0105] In some embodiments, the scanning unit is connected to the gate signal line.

[0106] In one embodiment, such as Figure 3A As shown, the buffer unit 111 in the first gate driving unit 11 is connected to the first gate signal line VGHO. Specifically, the first gate signal line VGH is connected to the second electrode of the first transistor T1 included in the first gate driving unit 11. The scan unit 112 in the first gate driving unit 11 is electrically connected to the first gate signal line VGHO. The buffer unit 121 in the second gate driving unit 12 is connected to the second gate signal line VGHE. Specifically, the second gate signal line VGHE is connected to the second electrode of the first transistor T2 included in the second gate driving unit 12. The scan unit 112 in the second gate driving unit 12 is electrically connected to the second gate signal line VGHE. The reference gate signal line VGL is connected to the scan unit 112 in the first gate driving unit 11 and to the second electrode of the second transistor T2 included in the buffer unit 111 in the first gate driving unit 11. Similarly, the reference gate signal line VGL is connected to the scan unit 122 in the second gate driving unit 12 and to the second electrode of the second transistor T2 included in the buffer unit 121 in the second gate driving unit 12.

[0107] In another embodiment, such as Figure 3B As shown, the buffer unit 111 in the first gate driving unit 11 is connected to the first gate signal line VGHO. Specifically, the first gate signal line VGHO is connected to the second electrode of the first transistor T included in the first gate driving unit 11. The scanning unit 112 in the first gate driving unit 11 is electrically connected to the second gate signal line VGHE. The buffer unit 121 in the second gate driving unit 12 is connected to the second gate signal line VGHE. Specifically, the second gate signal line VGHE is connected to the second electrode of the first transistor T1 included in the second gate driving unit 12. The scanning unit 122 in the second gate driving unit 12 is electrically connected to the first gate signal line VGHO.

[0108] In another embodiment, such as Figure 3C As shown, the gate signal line VGH further includes a third gate signal line VGHC, which is supplied with the first voltage V1. The third gate signal line VGHC is spaced apart from the first gate signal line VGHO and the second gate signal line VGHE.

[0109] The first gate signal line VGHO is connected to the second electrode of the first transistor T1 included in the buffer unit 111 of the first gate driving unit 11, the second gate signal line VGHE is connected to the second electrode of the first transistor T1 included in the buffer unit 121 of the second gate driving unit 12, the third gate signal line VGHC is connected to the scanning unit 112 of the first gate driving unit 11, and the third gate signal line VGHC is connected to the scanning unit 122 of the second gate driving unit 12.

[0110] In some embodiments of this disclosure, the gate signal line VGH includes: a first connection point D1 connecting the first gate signal line VGHO to the first gate driving unit 11; a second connection point D2 connecting the second gate signal line VGHE to the second gate driving unit 12; and / or a third connection point D3 connecting the third gate signal line VGHC to the first gate driving unit 11 or the second gate driving unit 12; and a short-circuit connection point DD on the gate signal line away from the first connection point D1, the second connection point D2 and / or the third connection point D3, so that the first gate signal line VGHO, the second gate signal line VGHE and / or the third gate signal line VGHC are short-circuited.

[0111] For example, the first connection point D1 is, for example, the point where a first gate signal line extending along the second direction Y connects to the second electrode of the first transistor included in the buffer unit of the first gate driving unit. The second connection point D2 is, for example, the point where a second gate signal line extending along the second direction Y connects to the second electrode of the first transistor included in the buffer unit of the second gate driving unit. The third connection point D3 is, for example, the point where a third gate signal line extending along the second direction Y connects to the scan unit of the first gate driving unit or the scan unit connected to the second gate driving unit.

[0112] For example, when the last row is a pixel group with an odd number of rows, the third connection point D3 is the point where the third gate signal line connects to the scan unit of the first gate driving unit; when the last row is a pixel group with an even number of rows, the third connection point D3 is the point where the third gate signal line connects to the scan unit of the second gate driving unit.

[0113] When the gate signal line includes a first gate signal line and a second gate signal line, the short-circuit connection point DD refers to the point where the first gate signal line and the second gate signal line are short-circuited. When the gate signal line includes a first gate signal line, a second gate signal line, and a third gate signal line, the short-circuit connection point refers to the point where the first gate signal line, the second gate signal line, and the third gate signal line are short-circuited simultaneously.

[0114] The following is combined Figures 4A to 4DThe first connection point, the second connection point, and the short-circuit connection point in the first gate signal line and the second gate signal line are described.

[0115] Figure 4A This is a schematic diagram showing a short-circuit connection between the first gate signal line and the second gate signal line according to an embodiment of the present disclosure. Figure 4B This is a schematic diagram of a short-circuit connection between the first gate signal line and the second gate signal line according to another embodiment of the present disclosure. Figure 4C This is a schematic diagram showing a short-circuit connection between the first gate signal line and the second gate signal line according to another embodiment of the present disclosure. Figure 4D This is a schematic diagram of a short-circuit connection between the first gate signal line and the second gate signal line according to another embodiment of the present disclosure.

[0116] exist Figures 4A to 4D In the illustrated embodiment, one first gate signal line VGHO and one second gate signal line VGHE are each provided. The first gate signal line VGHO is used to enable the first gate driving unit 11 to provide gate control signals for the odd-numbered pixel groups, and the second gate signal line VGHE is used to enable the second gate driving unit 12 to provide gate control signals for the even-numbered pixel groups.

[0117] In order to reduce mutual interference caused by voltage fluctuations due to load during the power-on process of the first gate signal line and the second gate signal line, a short-circuit connection point is set away from the first connection point and the second connection point on the gate signal line so that the first gate signal line and the second gate signal line are short-circuited.

[0118] Since the first connection point is connected to the second electrode of the first transistor included in the buffer unit of the first gate driving unit, and the second connection point is connected to the second electrode of the first transistor included in the buffer unit of the second gate driving unit, noise interference will occur when the gate signal lines of different rows are pulled up. If the short-circuit connection point of the first gate signal line and the second gate signal line is placed near the first connection point or the second connection point, it will cause mutual interference between the electrical signals on the first gate signal line and the second gate signal line. Therefore, placing the short-circuit connection point on the gate signal line away from the first connection point and the second connection point can effectively reduce or completely avoid the problem of mutual interference between the electrical signals on the gate signal line.

[0119] A voltage-regulating capacitor C is disposed on the gate signal line VGH at a position away from the first connection point D1 and the second connection point D2, and is connected to the first gate signal line VGHO and the second gate signal line VGHE. The voltage-regulating capacitor C is disposed between the first connection point D1, the second connection point D2 and the short-circuit connection point DD.

[0120] To further reduce the jitter caused by the load during the pull-up process of the electrical signals on the first and second gate signal lines, a voltage stabilizing capacitor is provided at one end of the first and second gate signal lines, thereby reducing noise on the first and second gate signal lines and suppressing jitter.

[0121] The voltage regulator capacitor C includes: a first voltage regulator capacitor C1 connected to the first gate signal line VGHO, and a second voltage regulator capacitor C2 connected to the second gate signal line VGHE. The voltage regulator capacitor is disposed within the flexible circuit board 14 included in the display substrate.

[0122] In some embodiments of this disclosure, a voltage-stabilizing capacitor is provided for each gate signal line. When jitter occurs on different gate signal lines, the noise on the gate signal line can be reduced and jitter suppressed by the voltage-stabilizing capacitor. At the same time, since a voltage-stabilizing capacitor is provided on each gate signal line, the problem of mutual interference between gate signal lines through short-circuit connection points can be avoided, further improving the signal stability of each gate signal line in the entire display substrate.

[0123] like Figure 4A As shown, the short-circuit connection point is located at the edge of the display area of ​​the display substrate, that is, the short-circuit connection point is set in the non-display area NA and located at the edge of the display area AA. Figure 4B As shown, the short-circuit connection point is located in the flexible circuit board 14 included in the display substrate. Figure 4C and Figure 4D As shown, the short-circuit connection point is located in the driver integrated circuit 13 included in the display substrate, such as... Figure 4C As shown, the first gate signal line VGHO and the second gate signal line VGHE are respectively pulled to adjacent pins in the driver integrated circuit 13 and shorted inside the driver integrated circuit, as follows. Figure 4D As shown, the first gate signal line VGHO and the second gate signal line VGHE are respectively pulled to different pins on both sides of the driver integrated circuit 13 and shorted inside the driver integrated circuit.

[0124] Furthermore, each of the first gate signal line VGHO and the second gate signal line VGHE is provided with a voltage stabilizing capacitor, such as a first voltage stabilizing capacitor C1 and a second voltage stabilizing capacitor C2. The first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 are disposed in the flexible circuit board 14, thereby suppressing noise on the signal on each gate signal line and improving the display effect of the display substrate.

[0125] In some embodiments of this disclosure, the gate signal line VGH further includes a third gate signal line VGHC. The following describes the specific implementation of this implementation. Figures 5A to 5DThe first connection point D1, the second connection point D2, the third connection point D3, and the short-circuit connection point DD in the first gate signal line VGHO, the second gate signal line VGHE, and the third gate signal line VGHC included in the embodiments of this disclosure will be described.

[0126] Figure 5A It is based on Figure 3C The diagram shows a schematic of a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line in one embodiment. Figure 5B It is based on Figure 3C A schematic diagram showing the first gate signal line, the second gate signal line, and the third gate signal line short-circuited in another embodiment. Figure 5C It is based on Figure 3C A schematic diagram showing the first gate signal line, the second gate signal line, and the third gate signal line short-circuited in another embodiment. Figure 5D It is based on Figure 3C The diagram shows a short-circuit connection of the first gate signal line, the second gate signal line, and the third gate signal line in another embodiment.

[0127] like Figure 5A and Figure 5D As shown, the gate signal line includes: a first connection point D1 connecting the first gate signal line VGHO to the first gate driving unit 11; a second connection point D2 connecting the second gate signal line VGHE to the second gate driving unit 12; a third connection point D3 connecting the third gate signal line VGHC to the first gate driving unit 11 or the second gate driving unit 12; and a short-circuit connection point DD on the gate signal line away from the first connection point D1, the second connection point D2 and / or the third connection point D3, so that the first gate signal line VGHO, the second gate signal line VGHE and the third gate signal line VGHC are short-circuited together.

[0128] Figure 6 This is a schematic diagram of the structure of a voltage-stabilizing capacitor according to an embodiment of the present disclosure.

[0129] like Figure 6 As shown, a voltage-regulating capacitor C is provided on the gate signal line at a position away from the first connection point D1, the second connection point D2 and the third connection point D3, and is connected to the first gate signal line VGHO, the second gate signal line VGHE and the third gate signal line VGHC.

[0130] The voltage stabilizing capacitor is disposed between the first connection point, the second connection point, the third connection point, and the short-circuit connection point, which is located within the flexible circuit board 14.

[0131] The voltage-stabilizing capacitor C includes: a first voltage-stabilizing capacitor C1 connected to the first gate signal line VGHO; a second voltage-stabilizing capacitor C2 connected to the second gate signal line VGHE; and a third voltage-stabilizing capacitor C3 connected to the third gate signal line VGHC. The voltage-stabilizing capacitor is disposed within the flexible circuit board included in the display substrate.

[0132] In some alternative embodiments of this disclosure, the short-circuit connection point DD may also be located in the driver integrated circuit.

[0133] According to embodiments of this disclosure, by providing a voltage stabilizing capacitor for each gate signal line (e.g., the first gate signal line, the second gate signal line, and the third gate signal line), the influence of signal jitter on other gate signal lines can be avoided, thereby improving the display effect of the display substrate.

[0134] like Figure 5A As shown, the short-circuit connection point is located at the edge of the display area of ​​the display substrate. Figure 5B As shown, the short-circuit connection point is located within the flexible circuit board included in the display substrate. Figure 5C and Figure 5D As shown, the short-circuit connection point is located in the driving integrated circuit included in the display substrate.

[0135] like Figure 5C As shown, the first gate signal line VGHO, the second gate signal line VGHE, and the third gate signal line VGHC are respectively pulled to adjacent pins in the driver integrated circuit 13 and shorted inside the driver integrated circuit, as shown. Figure 5D As shown, the first gate signal line VGHO, the second gate signal line VGHE, and the third gate signal line VGHC are respectively pulled to different pins on both sides of the driver integrated circuit 13 and shorted inside the driver integrated circuit.

[0136] In some embodiments of this disclosure, the first gate signal line includes at least two lines, and the second gate signal line includes at least two lines.

[0137] For example, the first gate signal line includes two lines, and the second gate signal line also includes two lines.

[0138] Figure 7A This is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to an embodiment of the present disclosure. Figure 7B This is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to another embodiment of the present disclosure. Figure 7C This is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to another embodiment of the present disclosure. Figure 7DThis is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines short-circuited together according to another embodiment of the present disclosure.

[0139] like Figures 7A to 7D As shown, the first gate signal line VGHO includes two lines, namely VGHO1 and VGHO2. VGHO1 is connected to the second electrode of the first transistor included in the buffer unit of the first gate driving unit 11 in the first row, so that the first gate driving unit of the first row provides gate control signals to the pixel group of the first row. VGHO2 is connected to the second electrode of the first transistor included in the buffer unit of the first gate driving unit 11' in the third row, so that the first gate driving unit of the third row provides gate control signals to the pixel group of the third row.

[0140] The second gate signal line VHGE also includes two lines, namely VGHE1 and VGHE2. VGHE1 is connected to the second electrode of the first transistor included in the buffer unit of the second gate driving unit 12 in the second row, so that the second gate driving unit of the second row provides gate control signals to the pixel group of the second row. VGHE2 is connected to the second electrode of the first transistor included in the buffer unit of the second gate driving unit 12' in the fourth row, so that the second gate driving unit of the fourth row provides gate control signals to the pixel group of the fourth row.

[0141] The connection methods between the pixel groups in other odd-numbered rows and the pixel groups in even-numbered rows and the first gate signal line and the second gate signal line are similar and will not be repeated here.

[0142] According to embodiments of this disclosure, when two or more first gate signal lines and second gate signal lines are provided, the influence of signal fluctuations caused by indium load between gate signals can be effectively avoided, thereby improving the display effect of the display substrate.

[0143] In some embodiments of this disclosure, the output poles of the buffer unit include a first output pole, a second output pole, and a third output pole; the first output pole is connected to the N-type gate and provides a first gate signal to the N-type gate; the second output pole is connected to the first P-type gate and provides a second gate signal to the first P-type gate; the third output pole is connected to the second P-type gate and provides a third gate signal to the second P-type gate.

[0144] In some embodiments of this disclosure, when the first gate signal line provides a gate control signal for the odd-numbered pixel group, and when the second gate signal line provides a gate control signal for the even-numbered pixel group, the timing of the maximum pull-down potential of the first gate signal line due to load and the timing of the maximum pull-down potential of the second gate signal line due to load do not overlap; the timing of the low voltage signal of the second gate signal and the timing of the low voltage signal of the third gate signal do not overlap with the timing of the maximum pull-down potential of the first gate signal line due to load and the timing of the maximum pull-down potential of the second gate signal line due to load.

[0145] Figure 8A This is a signal waveform diagram of a display substrate according to an embodiment of the present disclosure, including a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate. Figure 8B This is a signal waveform diagram of a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate according to an embodiment of the present disclosure.

[0146] like Figure 8A and Figure 8B As shown, when the first gate signal line VGHO is charged by the pull-up resistor, that is, when the first gate signal line VGHO charges the second electrode of the first transistor included in the buffer unit 111 in the first gate driving unit 11, and is output to the N-type gate, the first P-type gate and the second P-type gate in the pixel circuit through the output of the buffer unit 111, the signal of the first gate signal line VGHO is pulled down due to the large instantaneous current and the influence of the resistive load, thereby generating the maximum pull-down potential due to the load. Similarly, the signal of the second gate signal line VGHE is pulled down, thereby generating the maximum pull-down potential due to the load. Since the first gate signal line VGHO and the second gate signal line VGHE are respectively connected to the gate driving units corresponding to different rows of pixel groups, the maximum pull-down potentials generated by the load do not overlap in timing.

[0147] like Figure 8A and Figure 8B As shown, the first gate signal line VGHO provides a signal to the second electrode of the first transistor included in the buffer unit of the first gate driving unit, which is the waveform corresponding to VGHO. The signal output by the first output electrode of the buffer unit included in the first gate driving unit is the waveform corresponding to Ngate(N), the signal output by the second output electrode is the waveform corresponding to Pgate(N), and the signal output by the third output electrode is the waveform corresponding to Pgate(N+1).

[0148] The second gate signal line VGHE provides a signal to the second electrode of the first transistor included in the buffer unit of the second gate driving unit, which is the waveform corresponding to VGHE. The signal output by the first output electrode of the buffer unit included in the second gate driving unit is the waveform corresponding to Ngate(N+2), the signal output by the second output electrode is the waveform corresponding to Pgate(N+2), and the signal output by the third output electrode is the waveform corresponding to Pgate(N+3).

[0149] like Figure 8A and Figure 8B As shown, the timing of the maximum pull-down potential of the first gate signal line VGHO due to the load and the maximum pull-down potential of the second gate signal line VGHE due to the load do not overlap, that is, they are staggered. This results in a large region between the maximum pull-down potentials of the first gate signal line VGHO and the second gate signal line VGHE due to the load, so that the first gate signal, the second gate signal and the third gate signal output by the output of the buffer unit will not interfere with each other.

[0150] like Figure 8B As shown, in the odd-numbered row pixel group, the low voltage signal in the second gate signal (waveform corresponding to Pgate(N)) and the low voltage signal in the third gate signal (waveform corresponding to Pgate(N+1)) do not overlap in timing. The fluctuation of the first gate signal Ngate(N) caused by the fluctuation of the first gate signal line VGHO is separated from the second and third gate signals, thereby avoiding interference.

[0151] In even-numbered pixel groups, the low-voltage signals in the second gate signal (waveform corresponding to Pgate(N+2)) and the low-voltage signals in the third gate signal (waveform corresponding to Pgate(N+3)) do not overlap in timing. The fluctuations in the first gate signal Ngate(N+2) caused by the fluctuations in the second gate signal line VGHE are spaced apart from the second and third gate signals, thus avoiding interference.

[0152] In some embodiments of this disclosure, the display substrate further includes a first clock signal line CK, a second clock signal line CB, an initial signal line, and a control signal line, which are respectively connected to the scanning units included in the first gate driving unit and the second gate driving unit.

[0153] Figure 9A This is a simulation waveform diagram of the gate control signal on the first gate signal line and the gate control signal on the second gate signal line without a voltage regulator capacitor. Figure 9BThis is a simulation waveform diagram of the gate control signal on the first gate signal line and the gate control signal on the second gate signal line of the voltage regulator capacitor according to an embodiment of the present disclosure.

[0154] like Figure 9A As shown, when no voltage regulator capacitors are set before the short-circuit connection point for the first gate signal line VGHO and the second gate signal line VGHE, although the voltage waveforms on the two gate signal lines are different, the waveforms on the two gate signal lines will interfere with each other because no voltage regulator capacitors are set before the short-circuit connection point. For example, when the voltage signal on the first gate signal line fluctuates due to load fluctuations, it will affect the voltage signal on the second gate signal line, resulting in poor display effect.

[0155] like Figure 9B As shown, by setting voltage-stabilizing capacitors C before the short-circuit connection point of the first gate signal line VGHO and the second gate signal line VGHE, for example, setting a first voltage-stabilizing capacitor C1 on the first gate signal line VGHO and a second voltage-stabilizing capacitor C2 on the second gate signal line VGHE, interference between the first gate signal line VGHO and the second gate signal line VGHE is eliminated. This effectively improves the display effect of the display substrate.

[0156] Figure 10A This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10B This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10C This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10D This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10E This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10F This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10G This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure. Figure 10H This is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure.

[0157] like Figures 10A to 10H A circuit diagram of a first gate driving unit that can be applied to an embodiment of this disclosure is shown. In embodiments of this disclosure, the circuit structures of the first gate driving unit and the second gate driving unit can be completely identical.

[0158] In one embodiment, such as Figure 10A As shown, the circuit structures of the first gate driving unit and the second gate driving unit are as follows:

[0159] The first gate driving unit includes a buffer unit BM and a scanning unit SM.

[0160] The buffer unit includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the pull-up node N4, and the gate of the second transistor T2 is connected to the pull-down node N7. The first electrodes of the first transistor T1 and the second transistor T2 are connected to the output terminal Nout n of the buffer unit. The second electrode of the first transistor T1 is connected to the first gate signal line VGHO, and the second electrode of the second transistor is connected to the reference gate signal line VGL.

[0161] The first clock signal line CK, the second clock signal line CB, the initial signal line STV, the reference gate signal line VGL, and the control signal line NCX are connected to the scan unit.

[0162] exist Figure 3A In the illustrated embodiment, if the circuit structures of the first gate driving unit and the second gate driving unit are as follows: Figure 10A As shown, the scanning unit 112 in the first gate driving unit is also connected to the first gate signal line VGHO. For example, one electrode of the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 in the circuit diagram are all connected to the first gate signal line VGHO. The scanning unit 122 in the second gate driving unit is also connected to the second gate signal line VGHE. For example, one electrode of the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 in the circuit diagram are all connected to the second gate signal line VGHO.

[0163] exist Figure 3B In the illustrated embodiment, if the circuit structures of the first gate driving unit and the second gate driving unit are as follows: Figure 10A As shown, the scanning unit 112 in the first gate driving unit is also connected to the second gate signal line VGHE. For example, one electrode of the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 in the circuit diagram are all connected to the second gate signal line VGHE. The scanning unit 122 in the second gate driving unit is also connected to the first gate signal line VGHO. For example, one electrode of the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 in the circuit diagram are all connected to the first gate signal line VGHO.

[0164] exist Figure 3C In the illustrated embodiment, if the circuit structures of the first gate driving unit and the second gate driving unit are as follows: Figure 10AAs shown, the scanning unit 112 in the first gate driving unit and the scanning unit 122 in the second gate driving unit are both connected to the third gate signal line VGHC. That is, in the first gate driving unit and the second gate driving unit, for example, one electrode of the fifth transistor T5 and one electrode of the eighth transistor T8 and the thirteenth transistor T13 in the circuit diagram are all connected to the first gate signal line VGHC.

[0165] like Figures 10B to 10H As shown, both the first gate driving unit and the second gate driving unit adopt the same circuit structure, both including a buffer unit BM and a scanning unit SM.

[0166] Each buffer unit BM includes a first transistor T1 and a second transistor T2. The second electrode of the first transistor T1 in the buffer unit BM is connected to the corresponding gate signal line; for example, if it is a first gate driving unit, the corresponding gate signal line is the first gate signal line. If it is a second gate driving unit, the corresponding gate signal line is the second gate signal line. The second electrode of the second transistor is connected to the reference gate signal line.

[0167] In embodiments of this disclosure, the scanning unit SM varies depending on the circuit design. The connection methods between the gate signal line and the buffer unit BM and the scanning unit SM specifically include... Figure 3A , Figure 3B as well as Figure 3C The three methods are shown.

[0168] Scanning unit SM in Figure 3A In one embodiment, the scanning unit in the first gate driving unit is connected to the first gate signal line VGHO, and the scanning unit in the second gate driving unit is connected to the second gate signal line VGHE.

[0169] Scanning unit SM in Figure 3B In one embodiment, the scanning unit in the first gate driving unit is connected to the second gate signal line VGHE, and the scanning unit in the second gate driving unit is connected to the first gate signal line VGHO.

[0170] Scanning unit SM in Figure 3C In one embodiment, the scanning units in the first gate driving unit and the second gate driving unit are both connected to the third gate signal line VGHC.

[0171] According to embodiments of this disclosure, by configuring the gate signal line as a first gate signal line connected to a first gate driving unit and a second gate signal line connected to a second gate driving unit, the first gate signal line can provide gate control signals for odd-numbered rows of pixel groups, and the second gate signal line can provide gate control signals for even-numbered rows of pixel groups. This achieves segmented control of the gate control signals, thereby effectively avoiding the problem of uneven display of two rows of pixel circuits within a pixel group caused by noise generated by the gate signal line under load affecting the pixel circuit. This effectively improves the display effect of the display substrate.

[0172] Figure 11 This is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0173] like Figure 11 As shown, at least some embodiments of this disclosure also provide a display device 200. The display device 200 may include the display substrate 100 as described above. The display device 200 includes a display area AA and a non-display area NA. The non-display area NA has a smaller width and a higher pixel density, enabling a display device with narrow bezels and high PPI.

[0174] The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0175] It should be understood that the display device according to the embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be found in the above description and will not be repeated here.

[0176] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0177] While some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, include: The gate signal line includes a first gate signal line and a second gate signal line, each of the first gate signal line and the second gate signal line is applied with a first voltage, and the first gate signal line and the second gate signal line are spaced apart from each other. A first gate driving unit and a second gate driving unit, both of which include a buffer unit. The buffer unit includes a first transistor, a second transistor, and an output terminal for the output gate control signal; The first electrode of the first transistor and the first electrode of the second transistor are connected to the output electrode, and the second electrode of the first transistor is connected to the gate signal line. A pixel circuit is electrically connected to the output of the buffer unit. The pixel circuit includes pixel groups with odd-numbered rows and pixel groups with even-numbered rows. Each pixel group includes at least two rows of pixel circuits. The first gate signal line is connected to the second electrode of the first transistor included in the first gate driving unit, so that the first gate driving unit provides a gate control signal for the odd-numbered row of pixels. The second gate signal line is connected to the second electrode of the first transistor included in the second gate driving unit, so that the second gate driving unit provides a gate control signal for the even-numbered row of pixels; Both the first gate driving unit and the second gate driving unit further include a scanning unit, which is connected to the gate signal line; The gate signal line further includes a third gate signal line, the third gate signal line is applied with the first voltage, and the third gate signal line is spaced apart from the first gate signal line and the second gate signal line. The third gate signal line is connected to the scanning unit in the first gate driving unit, and The third gate signal line is connected to the scanning unit in the second gate driving unit; The gate signal line includes: The first connection point where the first gate signal line connects to the first gate driving unit; The second connection point where the second gate signal line connects to the second gate driving unit; and / or The third connection point where the third gate signal line connects to the first gate driving unit or the second gate driving unit; and A short-circuit connection point on the gate signal line that is far from the first connection point, the second connection point, and / or the third connection point, so that the first gate signal line, the second gate signal line, and / or the third gate signal line are short-circuited.

2. The display substrate according to claim 1, wherein, Also includes: A reference gate signal line is provided with a second voltage and is connected to the second terminal of the second transistor included in the buffer unit.

3. The display substrate according to claim 2, wherein, The scanning unit in the first gate driving unit is electrically connected to the first gate signal line; The scanning unit in the second gate driving unit is electrically connected to the second gate signal line.

4. The display substrate according to claim 2, wherein, The scanning unit in the first gate driving unit is electrically connected to the second gate signal line; The scanning unit in the second gate driving unit is electrically connected to the first gate signal line.

5. The display substrate according to any one of claims 3 or 4, wherein, The reference gate signal line is connected to the scan unit in the first gate driving unit, and The reference gate signal line is connected to the scan unit in the second gate driving unit.

6. The display substrate according to claim 2, wherein, A voltage-stabilizing capacitor is provided on the gate signal line at a position away from the first connection point, the second connection point, and / or the third connection point, and is connected to the first gate signal line, the second gate signal line, and / or the third gate signal line.

7. The display substrate according to claim 6, wherein, The voltage stabilizing capacitor is disposed between the first connection point, the second connection point, and / or the third connection point and the short-circuit connection point.

8. The display substrate according to claim 7, wherein, The voltage-stabilizing capacitor includes: A first voltage-regulating capacitor connected to the first gate signal line; The second Zener capacitor connected to the second gate signal line; and / or A third voltage regulator capacitor connected to the third gate signal line.

9. The display substrate according to claim 8, wherein, The short-circuit connection point is located at the edge of the display area of ​​the display substrate; or The short-circuit connection point is located in the flexible circuit board included in the display substrate; or The short-circuit connection point is located in the driver integrated circuit included in the display substrate.

10. The display substrate according to claim 9, wherein, The voltage-stabilizing capacitor is disposed within the flexible circuit board included in the display substrate.

11. The display substrate according to any one of claims 1 to 4, 6 to 10, wherein, The first gate signal line includes at least two lines, and the second gate signal line includes at least two lines.

12. The display substrate according to claim 1, wherein, Each pixel group in the pixel circuit includes a first row of pixel circuits and a second row of pixel circuits arranged in parallel. The first row of pixel circuits and the second row of pixel circuits include a common N-type gate; The first row of pixel circuits includes a first P-type gate, and the second row of pixel circuits includes a second P-type gate.

13. The display substrate according to claim 12, wherein, The output poles include a first output pole, a second output pole, and a third output pole; The first output terminal is connected to the N-type gate to provide a first gate signal to the N-type gate; The second output terminal is connected to the first P-type gate to provide a second gate signal to the first P-type gate; The third output electrode is connected to the second P-type gate, providing a third gate signal to the second P-type gate.

14. The display substrate according to claim 13, wherein, The low voltage signal in the second gate signal and the low voltage signal in the third gate signal do not overlap in timing.

15. The display substrate according to claim 2, wherein, Also includes: The scanning unit is connected to a first clock signal line, a second clock signal line, an initial signal line, and a control signal line.

16. The display substrate according to claim 13 or 14, wherein, When the first gate signal line provides a gate control signal to the pixel group in the odd-numbered rows, and when the second gate signal line provides a gate control signal to the pixel group in the even-numbered rows, the timing of the maximum pull-down potential of the first gate signal line due to load and the maximum pull-down potential of the second gate signal line due to load do not overlap. The timing of the low voltage signal of the second gate signal and the timing of the low voltage signal of the third gate signal do not overlap with the timing of the maximum pull-down potential of the first gate signal line due to the load and the timing of the maximum pull-down potential of the second gate signal line due to the load.

17. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 16.

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