A method for improving the precision of a missile operation time sequence reference

Abstract

The application discloses a method for improving the precision of a missile working time sequence reference, which rapidly captures the moment of separation by adopting an interrupt mode, eliminates the delay caused by a period inquiry separation characteristic signal, sets a steady state judgment duration of the separation characteristic signal, calculates the corresponding flight controller timer counter counting value, compensates the counting value in the timer counter to complete the compensation of the steady state judgment delay, compensates the delay from the separation characteristic signal to the end of the current calculation period, adjusts the calculation period duration of the flight controller separation moment, makes the steady state judgment to the effective separation signal moment coincide with the calculation period, adjusts the running time of the current period, and makes the flight controller directly start the next calculation period. The method can provide a precise and reliable time zero point for the missile flight, reduces the system time delay, and improves the missile control precision.

Description

Technical Field

[0001] This invention belongs to the field of missile technology, specifically relating to a method for improving the accuracy of missile operating timing references. Background Technology

[0002] To ensure the accuracy of guided weapons in complex battlefield environments, precisely configuring the missile's operational sequence has become a key focus for the next generation of missiles. During missile flight, many of its actions are executed according to pre-designed time nodes. For example, after the missile initiates flight, it sequentially performs actions such as "explosive bolt ignition," "engine ignition," "navigation start calculation," and "fuze release and protection ignition."

[0003] Missile operation based on a specific time sequence means that a time reference is set at a certain point in time, and timing begins from there. When the predetermined time arrives, the missile executes the corresponding action. Therefore, in order to accurately configure the missile's operational timing, it is first necessary to provide the missile with a precise timing reference.

[0004] A precise missile timing reference is a prerequisite for the accuracy of all missile timing actions and a prerequisite for precise and stable missile control. Therefore, a precise and stable time reference needs to be designed for the missile so that it can execute subsequent timing actions based on that reference.

[0005] The timing reference serves as the basis for all missile timing actions. Existing schemes generally select the moment when the missile's disengagement connector separates from the launch device as the missile's operational timing reference. After missile separation, the time increments from zero periodically, using this separation moment as the relative time zero point, and subsequent missile timing actions are executed.

[0006] To identify the missile separation moment and establish a separation time reference, a characteristic signal is typically designed. The difference between this characteristic signal before and after separation is used to determine whether the missile has separated. Existing technologies generally set the separation characteristic signal as a step-level signal, characterized by a low level when the missile is not separated and a jump to a high level after separation. The flight controller uses a periodic query method to determine the missile separation moment. Specifically, it continuously queries the separation characteristic signal N times within a certain calculation cycle. If all N queries indicate "separation completed," the missile is considered separated in that calculation cycle, and a time zero is set. In the next calculation cycle, the time increments from zero, and the missile performs the post-separation actions. Multiple queries prevent misidentification due to abnormal jitter or other reasons.

[0007] This method of setting missile operational timing benchmarks based on periodic queries is simple and reliable, but it has a delay in determining the separation time, with the delay time reaching up to one calculation cycle. For example... Figure 3 As shown, the delay mainly involves three points:

[0008] The first delay is caused by querying the separation feature signal at a certain frequency. Due to the complexity of the flight controller's functions, it cannot continuously query the separation feature signal without performing other tasks; therefore, it needs to query the separation feature signal at a certain frequency, such as... Figure 3 As shown, the separation signal is low for the first, second, and third queries, until the separation signal is high for the k1th query. If the separation time of the k1st query is taken as the time reference, the separation time has already occurred and the duration is △T1. Therefore, the time zero point setting delay caused here is △T1.

[0009] The second issue is the delay ΔT2 caused by the steady-state judgment of the separation characteristic signal. In harsh natural environments such as outdoor fields, the electromagnetic environment is complex and unknown. The flight controller needs to eliminate glitches and interference on the separation characteristic signal during separation judgment to identify the true separation moment. This requires the flight controller to judge a continuous and stable high-level separation characteristic, rather than just judging a single high-level signal. For example... Figure 3 As shown, the width of the dashed box represents the width that the flight controller needs to continuously judge. The high-level separation signal is judged for the k1th time. After judging n times, the nth time is a high-level separation signal. If the separation time is taken as the time reference when the knth query time is used, the separation time has already appeared and the duration is △T2. Therefore, the time zero point setting delay caused here is △T2.

[0010] The third point is the delay ΔT3 between the detection of the separation characteristic signal and the end of the current calculation cycle. Since the separation moment occurs randomly, the position of the separation moment within a certain cycle is also randomly distributed for the flight controller. When missile separation is stably detected within a cycle, after setting the completion time to zero, the time increment can only be accumulated from zero in the next cycle, ignoring the time interval from the completion of the detection to the end of the current cycle. For example... Figure 3 As shown, if the separation time is taken as the starting time of the next cycle, the separation time has already occurred and has lasted for △T3. Therefore, the time zero point setting delay caused here is △T3, and the duration of △T3 is not fixed and cannot be compensated.

[0011] In summary, such as Figure 3 As shown in the figure, "Separation Time" represents the time when the separation characteristic signal appears, and "Time Reference Setting Time" represents the time reference setting time using the existing technical solution. There is a time difference ΔT between the two times. Ideally, the time reference setting time should be the same as the separation time. The existing technical solution has a delay, which is ΔT = ΔT1 + ΔT2 + ΔT3, and the duration of ΔT3 is not fixed and cannot compensate for the delay time. Summary of the Invention

[0012] To overcome the shortcomings of existing technologies, this invention provides a method for improving the accuracy of missile operating timing references. First, an interrupt method is used to rapidly capture the instant of separation, eliminating the delay caused by periodically querying the separation characteristic signal. Next, a steady-state judgment duration for the separation characteristic signal is set, and the corresponding flight controller timer counter count value is calculated. Compensation is then applied to the count value in the timer counter to compensate for the steady-state judgment delay. The delay from judging the separation characteristic signal to the end of the current calculation cycle is also compensated. Finally, by adjusting the calculation cycle duration where the flight controller's separation moment occurs, the moment of steady-state judgment of the valid separation signal coincides with the calculation cycle, thus adjusting the cycle's running time. The flight controller then directly begins the next calculation cycle. This method provides a precise and reliable time zero point for missile flight, reduces system time delay, and improves missile control accuracy.

[0013] The technical solution adopted by this invention to solve its technical problem is as follows:

[0014] Step 1: Capture the instant of separation using an interrupt method to eliminate the delay △T1 caused by periodically querying the separation characteristic signal;

[0015] Step 2: Set the steady-state judgment duration △T2 for the separated characteristic signal, and calculate the count value △M of the flight controller timer counter corresponding to the time △T2. Then, compensate △M of the count value in the timer counter to complete the compensation for the steady-state judgment delay △T2.

[0016] Step 3: Compensate for the delay ΔT3 between the detection of the separation feature signal and the end of the current solution cycle; by adjusting the duration of the solution cycle in which the separation moment of the flight controller occurs, the moment when the effective separation signal is detected in steady state coincides with the solution cycle, that is, ΔT3 is compressed to 0, the running time of the current cycle is adjusted, and the flight controller directly starts the next solution cycle.

[0017] Preferably, step 1 specifically comprises:

[0018] Initialize the signal interrupt source of the interrupt controller, enable the I / O interrupt of the interrupt controller, configure it as an edge-triggered interrupt, initialize the interrupt configuration as IRQ, and assign it a priority of vector interrupt 0;

[0019] After the interrupt initialization is completed, if the separation characteristic signal jumps from low level to high level, the flight controller immediately recognizes the rising edge of the separation characteristic signal and jumps to the pre-set interrupt service subroutine. The moment when the program jumps to the interrupt service subroutine is the separation moment.

[0020] Preferably, step 2 specifically comprises:

[0021] Set the steady-state judgment duration ΔT2 for the separation characteristic signal;

[0022] The calculation time △T2 corresponds to the flight controller timer counter count value △M; the timer is an internal module of the flight controller, providing time services for the flight controller; the flight controller timing principle is as follows: the internal crystal oscillator of the flight controller provides the clock reference, which is multiplied to provide the external clock PCLK; the external clock frequency PCLK is divided by the prescaler register PR to obtain the frequency PCLK_PR, and this frequency PCLK is divided by the matching register MR to obtain the frequency PCLK_MR, which is the frequency of the flight controller's calculation cycle;

[0023]

[0024] Based on the proportional relationship, we can obtain:

[0025]

[0026] so:

[0027]

[0028] After simplification, we get:

[0029]

[0030] That is, the accumulated value of the timer counter during the time period △T2.

[0031] Preferably, the steady-state judgment duration ΔT2 is 1ms, meaning that glitch signals with a pulse width of less than 1ms will be filtered out.

[0032] A computer program that causes a computer to execute the above-described method for improving the accuracy of missile operational timing references.

[0033] An electronic device includes a processor and a memory; the memory stores a computer program, and the processor executes the computer program stored in the memory to enable the electronic device to perform the aforementioned method for improving the accuracy of missile operational timing references.

[0034] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method for improving the accuracy of missile operational timing references.

[0035] A chip includes a processor for retrieving and running a computer program from a memory, causing a device equipped with the chip to perform the aforementioned method for improving the accuracy of missile operational timing references.

[0036] A computer program product includes a computer storage medium storing a computer program, the computer program including instructions executable by at least one processor, which, when executed by the at least one processor, implement the method described above for improving the accuracy of missile operational timing references.

[0037] The beneficial effects of this invention are as follows:

[0038] Innovation Point 1. Precise and rapid capture of possible separation moments. This invention utilizes the external interrupt feature of the processor to rapidly capture possible separation characteristic signal transition moments.

[0039] Innovation Point 2. From the perspective of solution cycle generation, the length of the solution cycle in which the separation moment occurs is adjusted in principle to compensate for the delay △T3 from the judgment of the separation characteristic signal to the end of the current solution cycle, so that the separation moment coincides with the start of the adjusted solution cycle. Then, the missile time zero point is directly set in this cycle. The comparison diagram of the flight controller working timing before and after the adjustment is shown in the figure below. Figure 4 As shown.

[0040] The method of this invention has the following innovations: innovation 1 can eliminate delay △T1, innovation 2 can eliminate delay △T3, which can solve the problem of time zero point setting delay caused by the existing flight controller's missile separation time judgment, and can compensate for the delay time, providing a precise and reliable time zero point for missile flight, reducing system time delay, and improving missile control accuracy. Attached Figure Description

[0041] Figure 1 This is the overall flowchart of the present invention;

[0042] Figure 2 The working principle of the flight controller timer;

[0043] Figure 3 Analysis diagram for determining the source of error at the moment of separation of flight controller;

[0044] Figure 4 A comparison chart of the flight controller's calculation cycle before and after compensation. Detailed Implementation

[0045] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0046] In order to provide a precise timing reference for missile operation, this invention discloses a method for improving the accuracy of missile operation timing reference. This method can provide a precise and reliable timing reference for missile flight and improve the accuracy of missile timing actions.

[0047] Based on the above analysis, the present invention aims to provide a method for improving the accuracy of missile operating timing references, the specific steps of which include the following:

[0048] (1) The interrupt method is used to quickly capture the moment of separation and eliminate the delay △T1 caused by periodic query of the separation characteristic signal.

[0049] (2) The steady-state judgment time △T2 of the separation characteristic signal is set manually, and the count value △M of the flight controller timer counter corresponding to the time △T2 is calculated. Then, the count value △M in the timer counter is compensated to complete the compensation for the steady-state judgment delay △T2.

[0050] (3) Compensate for the delay △T3 between the detection of the separation feature signal and the end of the current solution cycle. By adjusting the duration of the solution cycle in which the separation moment of the flight controller occurs, the moment when the effective separation signal is detected in steady state coincides with the solution cycle. That is, △T3 is artificially compressed to 0, the running time of the current cycle is adjusted, and the flight controller directly starts the next solution cycle.

[0051] Example:

[0052] Step 1: Use an interrupt method to quickly capture the moment of separation and eliminate the delay △T1 caused by periodically querying the separation characteristic signal.

[0053] The interrupt mechanism refers to the process where an event interrupts the main program currently being executed by the CPU (Central Processing Unit), causing the CPU to execute an interrupt service routine before returning to the main program. The interrupt controller is an internal module of the flight controller's CPU. Through the interrupt controller, the attributes of event-triggered interrupts can be configured, such as enabling, disabling, and prioritizing. After the interrupt controller's initialization configuration is complete, it simply waits for the interrupt trigger condition to occur.

[0054] For example, the separation signal of a conventional tactical missile is low before separation and high after separation, which is a step signal from low to high. Initialize the signal interrupt source of the interrupt controller, enable the I / O (Input / Output) interrupt of the interrupt controller, configure it as an edge-triggered interrupt, initialize the interrupt configuration as IRQ (Interrupt Request), and assign it the priority of vector interrupt 0.

[0055] After the interrupt initialization is completed, if the separation characteristic signal jumps from low level to high level, the flight controller immediately recognizes the rising edge of the separation characteristic signal and jumps to the pre-set interrupt service subroutine. The moment when the program jumps to the interrupt service subroutine is the separation moment.

[0056] Step 2: Manually set the steady-state judgment duration ΔT2 for the separated characteristic signals, and calculate the flight controller timer counter count value ΔM corresponding to time ΔT2. Then, compensate ΔM of the count value in the timer counter to complete the compensation for the steady-state judgment delay ΔT2. Figure 2 As shown.

[0057] Based on the actual working conditions of the missile, the steady-state judgment time △T2 of the separation characteristic signal is set. The purpose of this time is to filter out interference and other glitch signals. Here, △T2 is initially set to 1ms, that is, glitch signals with a pulse width of less than 1ms will be filtered out.

[0058] The following calculates the flight controller timer counter value ΔM corresponding to time ΔT2. The timer is an internal module of the flight controller, providing time services. The flight controller's timing principle is as follows: the internal crystal oscillator provides the clock reference, which, after frequency multiplication, provides the external clock PCLK. The external clock frequency PCLK is divided by the prescaler register PR to obtain the frequency PCLK_PR. This frequency PCLK is then divided by the matching register MR to obtain the frequency PCLK_MR. This frequency is the frequency of the flight controller's calculation cycle.

[0059]

[0060] Based on the proportional relationship, we can obtain

[0061]

[0062] so:

[0063]

[0064] After simplification, we get:

[0065]

[0066] That is, the accumulated value of the timer counter during the time period △T2.

[0067] Assuming the flight controller PCLK frequency is 60MHz in this example, in order to set the flight controller calculation period to 5ms, according to formula (1), the prescaler value can be set to 100 and the matching register MR value can be set to 3000.

[0068] Accordingly, in order to calculate the flight controller timer counter count value ΔM corresponding to ΔT2, assume ΔT2 is 1ms.

[0069] The calculation yields:

[0070]

[0071] That is, ΔT2 is 1ms, and its corresponding timer counter ΔM value is 600. In other words, in order to compensate for the steady-state judgment delay of ΔT2 = 1ms, the timer counter TC value needs to be increased by 600.

[0072] Step 3: Compensate for the delay ΔT3 between the detection of the separation feature signal and the end of the current solution cycle. By adjusting the duration of the solution cycle in which the separation moment of the flight controller occurs, the moment when the effective separation signal is detected in steady state coincides with the solution cycle. In other words, ΔT3 is artificially compressed to 0, thus adjusting the running time of the current cycle. The flight controller then directly begins the next solution cycle.

[0073] According to formula (1), continuing with the flight controller example in this case, when the timer counter count is 0, it indicates the start of a solution cycle, and when the timer counter count is 3000, it indicates the end of a solution cycle. Therefore, the current value of the timer counter can be cleared, that is, △T3 can be set to 0, indicating the start of the next solution cycle, that is, the duration of this cycle can be adjusted so that the start time of the separation signal coincides with the start time of the cycle.

[0074] Step 4: Step 2 corrects the timer counter value to "current value + ΔM", and Step 3 corrects the timer counter value to "-current value". Combining Steps 2 and 3, the timer counter value is corrected to ΔM. That is, after the judgment is completed, the current time is directly set to the time of the next cycle. Figure 4 As shown.

[0075] Combination Figure 1 The principle of this invention is further illustrated through experiments:

[0076] Suppose that when an interrupt is detected, the timer counter value M1 is read as 1500. After continuously judging the separation signal for 1ms, the timer counter value M2 is read as 2100, indicating that the missile has separated. The first cycle is compensated, and the judgment time is compensated for 1ms, that is, the timer counter TC value is set to 600.

[0077] Now suppose that when an interrupt is detected, the timer counter TC value M1 is read as 2800. After continuously checking the separation signal for 1ms, the timer counter TC value M2 is read as 400. At this time, M2

Claims

1. A method for improving the accuracy of missile operating timing reference, characterized in that, Includes the following steps: Step 1: Capture the instant of separation using an interrupt method to eliminate the delay △T1 caused by periodically querying the separation characteristic signal; Initialize the signal interrupt source of the interrupt controller, enable the I / O interrupt of the interrupt controller, configure it as an edge-triggered interrupt, initialize the interrupt configuration as IRQ, and assign it a priority of vector interrupt 0; After the interrupt initialization is completed, if the separation characteristic signal changes from low level to high level, the flight controller will immediately recognize the rising edge of the separation characteristic signal and jump to the pre-set interrupt service subroutine. The moment when the program jumps to the interrupt service subroutine is the separation moment. Step 2: Set the steady-state judgment duration △T2 for the separated characteristic signal, and calculate the count value △M of the flight controller timer counter corresponding to time △T2. Then, compensate △M of the count value in the timer counter to complete the compensation for the steady-state judgment delay △T2. Step 3: Compensate for the delay ΔT3 between the detection of the separation feature signal and the end of the current solution cycle; by adjusting the duration of the solution cycle in which the separation moment of the flight controller occurs, the moment when the effective separation signal is detected in steady state coincides with the solution cycle, that is, ΔT3 is compressed to 0, the running time of the current cycle is adjusted, and the flight controller directly starts the next solution cycle.

2. The method for improving the accuracy of missile operating timing reference according to claim 1, characterized in that, Step 2 specifically involves: Set the steady-state judgment duration ΔT2 for the separation characteristic signal; Calculate the count value △M of the flight controller timer counter corresponding to the time △T2; the timer is an internal module of the flight controller that provides time service to the flight controller; the timing principle of the flight controller is: the internal crystal oscillator of the flight controller provides the clock reference, which is multiplied to provide the external clock PCLK; The peripheral clock frequency PCLK is divided by the prescaler register PR to obtain the frequency PCLK_PR. This frequency PCLK_PR is then divided by the matching register MR to obtain the frequency PCLK_MR. This frequency is the frequency of the flight controller's calculation cycle. Timer period = (1) Based on the proportional relationship, we can obtain: so: After simplification, we get: That is, the accumulated value of the timer counter during the time period △T2. .

3. The method for improving the accuracy of missile operating timing reference according to claim 2, characterized in that, The steady-state judgment duration ΔT2 is 1ms, meaning that glitch signals with a pulse width of less than 1ms will be filtered out.

4. An electronic device, characterized in that, include: Processor and memory; The memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to cause the electronic device to perform the method as described in any one of claims 1 to 3.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 3.

6. A chip, characterized in that, include: A processor for retrieving and running a computer program from memory, causing a device on which the chip is mounted to perform the method as described in any one of claims 1 to 3.

7. A computer program product, characterized in that, The computer program product includes a computer storage medium storing a computer program, the computer program including instructions executable by at least one processor, which, when executed by the at least one processor, implement the method as described in any one of claims 1 to 3.

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