A crosstalk-resistant arc detection device and method for fire faults

Abstract

This invention discloses an anti-crosstalk arc fault detection device and method, relating to smart grids. It solves the problem that existing arc fault detection methods cannot correctly identify the source of electromagnetic noise, causing malfunctions in arc fault protection equipment. The key technical points are: signals are collected by a pair of current sensors installed on the internal electrical circuit to obtain a first analog signal and a second analog signal; the first and second analog signals are digitally shaped by a pair of digital waveform shapers to obtain a first high-low level signal and a second high-low level signal; the first and second digital signals are synchronously captured by a timing clock and a pair of waveform capture circuits to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; and the first and second high-low level waveform sequences are matched and compared by a waveform judgment circuit to determine the signal source; thus solving the aforementioned problems.

Description

Technical Field

[0001] This invention relates to smart grids, and more specifically, to a crosstalk-resistant arc detection device and method for fire faults. Background Technology

[0002] Arc fault detection technology is a key technology for solving electrical fires caused by aging electrical circuits and poor contact. This technology has been proposed for nearly forty years, and the world's first product standard UL1699 (AFCI) has been formulated for more than 25 years. It has been promoted and applied for more than 20 years, but its application has not been widespread in the world. One key reason is that arc fault protection devices are prone to malfunction, and abnormal tripping and power outages affect consumers' life experience.

[0003] One challenge in detecting arc faults is the impact of grid crosstalk signals on detection reliability. Because the phase and neutral wires of all load circuits within the same AC power grid area are connected, load changes and switching actions from numerous loads, coupled with electromagnetic field coupling signals, and especially the increasingly prevalent high-frequency electromagnetic noise from power electronic circuits, propagate along these circuits to various electrical components, including arc fault protection devices. This high-frequency electromagnetic noise is easily confused with the signal generated during an arc fault. Secondly, the objective of arc fault protection devices is to protect the load-side circuits from fire; they are not permitted to operate if an arc fault occurs on the bypass side of the power supply. Therefore, accurately and reliably identifying whether this high-frequency electromagnetic noise originates from the load side or is external crosstalk from the power supply side is a crucial challenge in ensuring the reliability of arc fault protection devices. Figure 1 As shown, Figure 1 This is a schematic diagram of a current arc fault protection device. Both the load side and the power supply side may generate high-frequency electromagnetic signals that are transmitted into the arc fault protection device, but only the high-frequency electromagnetic signals from the load side need to be processed.

[0004] The impact of external crosstalk signals from the power supply side on fault arc detection is mainly concentrated in the following two aspects: 1. The morphology of external crosstalk signals from the power supply side is extremely similar to that of fault arc signals, easily leading to false alarms in fault arc detection. 2. Even if a fault arc actually occurs on the external bypass electrical lines, it should not trigger the operation of the fault arc protection device. In summary, existing fault arc detection methods cannot correctly distinguish the source of electromagnetic noise, i.e., whether it originates from the load side or external crosstalk from the power supply side, easily causing false alarms in fault arc protection devices.

[0005] Therefore, this application provides an anti-crosstalk arc detection device and method for fire faults, solving the above-mentioned problems. Summary of the Invention

[0006] The purpose of this application is to provide an anti-crosstalk arc fault detection device and method to solve the problem that existing arc fault detection cannot correctly distinguish the source of electromagnetic noise, i.e., whether it is external crosstalk from the load side or the power supply side, causing the arc fault protection equipment to malfunction. This application uses dual current sensors at different locations to detect high-frequency signals on the line, and then uses a signal processing circuit to determine whether there is external crosstalk signal, thus solving the above problem.

[0007] This application first provides a crosstalk-resistant arc fault detection device, comprising: a pair of current sensors: a first sensor and a second sensor, the first sensor and the second sensor being located on the internal electrical circuit of the arc fault protection device and being a certain distance apart, the first sensor first acquiring the signal from the external power supply side, and the second sensor first acquiring the signal from the internal load side; a pair of signal waveform digital shapers: a first signal waveform digital shaper and a second signal waveform digital shaper, the first signal waveform digital shaper being connected to the first sensor, and the second signal waveform digital shaper being connected to the second sensor; a pair of waveform capture circuits: a first waveform capture circuit and a second waveform capture circuit, the first waveform capture circuit being connected to the first signal waveform digital shaper, and the second waveform capture circuit being connected to the second signal waveform digital shaper; a waveform judgment circuit, connected to the first waveform capture circuit and the second waveform capture circuit, used to determine the signal source by waveform matching timing comparison, and decide whether to perform subsequent arc fault identification based on the signal source; and a timing clock, connected to the first waveform capture circuit, the second waveform capture circuit, and the waveform judgment circuit.

[0008] In one possible implementation, the only connection between the first and second sensors is a wire of the same specification.

[0009] In one possible implementation, the signal waveform digital shaper employs a digital comparator to convert the analog signals output by the first and second sensors into high and low level signals.

[0010] In one possible implementation, the waveform capture circuit uses a TDC circuit, which includes: multiple corresponding D flip-flops and delay units. Multiple delay units are cascaded to form a delay line connected to the high and low level signals output by the signal waveform digital shaper. The D input terminal of the D flip-flop is connected to the output of the corresponding delay unit. The clock terminal of the D flip-flop is connected to a timing clock through a clock signal line. The output terminal of the D flip-flop outputs the latched high and low levels. Multiple D flip-flops form a D flip-flop chain and output the latched high and low level waveform sequence.

[0011] In one possible implementation, let the signal arrival time difference between a pair of current sensors be... Time difference This is reflected in the high and low level waveform sequences. If the difference is 1 bit, then the delay time of each delay unit on the delay line of the TDC circuit is at most 1 bit. The set capture interval time given by the clock is Then the number of D flip-flops in the delay chain of the TDC circuit is .

[0012] In one possible implementation, a waveform judgment circuit is used to match two high-low level waveform sequences: if for each consecutive 1 sequence segment in one high-low level waveform sequence, a matching or approximately matching consecutive 1 sequence segment can be found in the other high-low level waveform sequence, and the time difference of the consecutive 1 sequence segments is consistent or approximately consistent, then the two high-low level waveform sequences are considered matched. Approximate matching means that the sequence length deviation of the consecutive 1 sequence segments is less than a threshold, and approximately consistent means that the time difference deviation is less than a threshold. For the matched two high-low level waveform sequences, the current sensor that the signal arrives at first is determined based on the time difference between the two high-low level waveform sequences, and the source of the signal is determined based on the location of the first arriving current sensor. Whether the signal source is the external power supply side or the internal load side is determined based on the signal source. Whether subsequent fault arc identification is performed is determined based on the signal source.

[0013] In one possible implementation, matching two high-low level waveform sequences is performed, including: assuming the two high-low level waveform sequences include a first high-low level waveform sequence from a first sensor and a second high-low level waveform sequence from a second sensor; firstly assuming the signal of the first high-low level waveform sequence comes first, performing continuous 1-segment matching and position difference comparison on the first and second high-low level waveform sequences; if continuous 1-segment matching and the position difference are consistent, the assumption is valid, and the signal comes from the external power supply side; if the assumption that the signal of the first high-low level waveform sequence comes first is not valid, then assuming the signal of the second high-low level waveform sequence comes first, performing continuous 1-segment matching and position difference comparison on the second and first high-low level waveform sequences; if continuous 1-segment matching and the position difference are consistent, the assumption is valid, and the signal comes from the internal load side; if neither assumption is valid, it indicates signal aliasing, and the direction cannot be determined.

[0014] In one possible implementation, the decision to perform fault arc identification is based on the signal source; this includes: a timer clock generating periodic clock pulses to trigger a waveform judgment circuit to perform a signal source identification, generating a mask code to control the MCU of the fault arc protection device to filter and process the signal; for signals from the external power supply side, fault arc identification is not performed, and the mask code is 0; for signals from the internal load side, fault arc identification is performed, and the mask code is 1; for aliased signals with no signal or unidentifiable source, fault arc identification is not performed, and the mask code is 0.

[0015] In one possible implementation, the Mask code is used to control the MCU of the fault arc protection device to filter the signal collected by the current sensor, extracting only the time slice signal with Mask code 1 and masking the time slice signal with Mask code 0.

[0016] This application also provides a crosstalk-resistant arc fault detection method, which is executed based on the aforementioned crosstalk-resistant arc fault detection device. The method includes: S1, acquiring signals based on a pair of current sensors installed on the internal electrical circuit to obtain a first analog signal and a second analog signal; S2, digitally shaping the first analog signal and the second analog signal based on a pair of signal waveform digital shapers to obtain a first high-low level signal and a second high-low level signal; S3, synchronously capturing the first high-low level signal and the second high-low level signal based on a timing clock and a pair of waveform capture circuits to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; S4, matching and comparing the first high-low level waveform sequence and the second high-low level waveform sequence based on a waveform judgment circuit to determine the signal source.

[0017] Compared with the prior art, this application has the following advantages: The anti-crosstalk arc detection device and method for fire faults in this application uses dual current sensors at different locations to detect high-frequency signals on the line, and then uses a signal processing circuit to determine whether there is external crosstalk signal; the signal processing circuit is mainly divided into three parts, namely a waveform digital shaper, a waveform capture circuit, and a waveform judgment circuit; the waveform digital shaper is used to convert the analog signal collected by the current sensor into high and low level signals according to the set comparison reference voltage and send them to the waveform capture circuit to output a high and low level waveform sequence; the waveform capture circuit is used to accurately record The system records the transmission process of digital signals on the delay line and can accurately capture the timing difference of the signals induced on two current sensors. It then sends two high- and low-level waveform sequences to the waveform judgment circuit. The waveform judgment circuit is used to determine the source of the high-frequency signal based on the two sets of time-synchronized high- and low-level waveform sequences captured by the waveform capture circuit, thereby determining whether there is external crosstalk signal. Based on the Mask sequence obtained by the above circuit, the MCU of the fault arc protection device performs shielding and filtering on the sensor analog signals collected by the AD converter, thereby avoiding false operation caused by crosstalk and improving the accuracy of fault arc handling. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 This is a schematic diagram of the current fault arc protection equipment;

[0020] Figure 2 A schematic diagram of the anti-crosstalk fire fault arc detection device provided in the embodiments of this application;

[0021] Figure 3 This is a schematic diagram of a digital signal waveform shaper provided in an embodiment of this application;

[0022] Figure 4 A schematic diagram of the analog signal provided in the embodiments of this application;

[0023] Figure 5 A schematic diagram of the waveform capture circuit provided in an embodiment of this application;

[0024] Figure 6 A schematic diagram illustrating the shaping and capture of a single-pulse waveform provided in an embodiment of this application;

[0025] Figure 7 A schematic diagram of a pulse group signal provided in an embodiment of this application;

[0026] Figure 8 This is a schematic diagram illustrating the shaping and capture of a multi-pulse signal provided in an embodiment of this application.

[0027] Figure 9 A flowchart of the signal source identification algorithm provided in the embodiments of this application;

[0028] Figure 10 A schematic diagram illustrating the shielding process of the high-frequency AD data to be processed by the MCU provided in this embodiment of the application;

[0029] Figure 11 A schematic diagram of air conditioner fault arc detection provided in an embodiment of this application;

[0030] Figure 12 A flowchart of an anti-crosstalk arc detection method for fire faults provided in an embodiment of this application. Detailed Implementation

[0031] In the following, the terms “comprising” or “may include” as used in the various embodiments of this application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in the various embodiments of this application, the terms “comprising,” “having,” and their cognates are intended only to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or the possibility of adding one or more combinations of the foregoing.

[0032] In various embodiments of this application, the expression "or" or "at least one of B and / or C" includes any combination or all combinations of the words listed simultaneously. For example, the expression "B or C" or "at least one of B and / or C" may include B, may include C, or may include both B and C.

[0033] The terms used in the various embodiments of this application (such as "first," "second," etc.) may modify various constituent elements in the various embodiments, but do not limit the corresponding constituent elements. For example, the above terms do not limit the order and / or importance of the elements. The above terms are only used for the purpose of distinguishing one element from other elements. For example, a first user device and a second user device refer to different user devices, although both are user devices. For example, without departing from the scope of the various embodiments of this application, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0034] It should be noted that if a description refers to "connecting" a component to another component or "connecting" it to another component, then the first component can be directly connected to the second component, and a third component can be "connected" between the first and second components. Conversely, when a component is "directly connected" to another component or "directly connected" to another component, it can be understood that there is no third component between the first and second components.

[0035] The terminology used in the various embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments of this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in a generally used dictionary) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this application are only for explaining this application and are not intended to limit this application.

[0037] First, the existing fault arc detection technologies are described to help those skilled in the art determine the improvements in this application. Currently, common fault arc detection technologies all rely on acquiring current waveforms on the line and analyzing waveform distortion for identification. This distortion is present not only in low-frequency current signals but also in high-frequency current signals. Because low-frequency current signals have linear superposition properties—that is, the current signals from multiple loads are linearly added at the fault arc protection device location—if a fault arc occurs in a small current branch, it is easily masked by the overall current. Therefore, common technologies acquire current signals over a wide frequency band, especially at high frequencies, to sensitively identify fault arcs in small current branches. Regarding bypass crosstalk, although relevant product standards (UL1699, IEC62606, GB / T31143) include related test items, these are primarily special treatments for standard testing scenarios. They do not fundamentally address the various crosstalk signals encountered in real-world applications, which is a major obstacle to the reliability and widespread application of such products.

[0038] In short, current arc fault protection devices are highly susceptible to confusing high-frequency crosstalk noise from the external power supply side with the arc fault signal from the internal load side that needs to be identified. Please refer to [link to relevant documentation]. Figure 1 As shown. The purpose of this invention is to identify the source of the aforementioned signals through circuitry and logic, thereby preventing malfunctions of arc fault protection devices.

[0039] Please see Figure 2 As shown, Figure 2 This is a schematic diagram of a crosstalk-resistant arc fault detection device provided in an embodiment of this application. The device includes: a pair of current sensors: a first sensor and a second sensor, located on the internal electrical circuit of the arc fault protection device and a certain distance apart; the first sensor first acquires the signal from the external power supply side, and the second sensor first acquires the signal from the internal load side; a pair of signal waveform digital shapers: a first signal waveform digital shaper and a second signal waveform digital shaper, the first signal waveform digital shaper being connected to the first sensor and the second signal waveform digital shaper being connected to the second sensor; a pair of waveform capture circuits: a first waveform capture circuit and a second waveform capture circuit, the first waveform capture circuit being connected to the first signal waveform digital shaper and the second waveform capture circuit being connected to the second signal waveform digital shaper; a waveform judgment circuit, connected to the first waveform capture circuit and the second waveform capture circuit, used to determine the signal source through waveform matching timing comparison and decide whether to perform subsequent arc fault identification based on the signal source; and a timing clock, connected to the first waveform capture circuit, the second waveform capture circuit, and the waveform judgment circuit.

[0040] The detection principle of the arc fault detection device provided by this invention lies in the installation of a pair of current sensors spaced a certain distance apart on the internal electrical circuit of the arc fault protection equipment. Signal recognition is achieved through a signal processing circuit. Although the transmission of high-frequency electromagnetic signals on the line is approximately at the speed of light, the distributed capacitance and inductance on the conductor cause a certain delay in the signal reaching the two sensors. If the signal originates from the load side, the sensor closer to the load side arrives first, and then reaches the power supply side sensor after a certain delay. Conversely, electromagnetic signals from the power supply side arrive first at the sensor closer to the power supply side, and then reach the load side after a certain delay. Therefore, it is possible to identify high-frequency crosstalk noise on the power supply side and arc fault signals on the load side.

[0041] Specifically, the device includes a pair of current sensors, two signal waveform digital shapers, and a waveform capture circuit. The current sensors detect high-frequency current signals on the line, convert them into voltage signals, and then input them to the signal waveform digital shapers. After shaping, the waveform capture circuit receives the sensor's signal waveform, essentially taking a snapshot of the waveform. Then, two sets of time-captured 0 / 1 sequence signals are input to a logic judgment circuit to determine whether the signal is external power supply side crosstalk or a high-frequency arc signal from the load side. If it is external crosstalk, the subsequent fault arc identification is not performed; otherwise, fault arc identification is required based on the sensor signal. Fault arc identification is performed by the MCU of the fault arc protection device using an analog-to-digital converter (AD converter) to convert the analog signal collected by the sensors, and then using the judgment result from the logic judgment circuit.

[0042] Please refer to the pair of current sensors Figure 2 As shown, in one possible implementation, there is only a wire between the first sensor and the second sensor, and the wires are of the same specification.

[0043] Specifically, a pair of identical current sensors, spaced a certain distance apart, are used. One sensor is located near the external power supply side, and the other is located near the load side. They synchronously detect signals on the line. When there is external crosstalk signal from the power supply side, the first sensor will detect it first; while when there is a high-frequency signal from the load side, the second sensor will detect it first. The current sensors can be connected to filters, amplifiers, etc., as needed to process the acquired signals and output analog signals.

[0044] Please refer to the signal waveform digital shaper. Figure 3 As shown, Figure 3 This is a schematic diagram of a digital signal waveform shaper provided in an embodiment of this application. In one possible implementation, the digital signal waveform shaper employs a digital comparator to convert the analog signals output by the first and second sensors into high and low level signals.

[0045] Specifically, please see Figure 4 As shown, Figure 4 This is a schematic diagram of the analog signal provided in an embodiment of this application. Figure 4 The demonstration showed an analog signal with a high-frequency pulse impact, which was shaped into a signal with varying high and low levels after being passed through a digital comparator.

[0046] It should be noted that traditional analog-to-digital conversion of high-frequency signal waveforms mostly uses ADC conversion circuits. However, based on the specific application scenario of this invention, the cost of using a high-speed ADC is very high in order to meet the extremely high waveform matching timing comparison requirements of high-frequency signals. Therefore, this invention uses a digital comparator to convert analog waveforms into high and low level waveforms, which has a high conversion rate and low cost. It also reduces the complexity of waveform matching timing comparison implementation, allowing for high-speed execution of waveform matching timing comparison directly using logic circuits. For example... Figure 2 When the digital shaper of the first and second signal waveforms shown is running, it acquires signals from the first and second sensors. The signals pass through the digital comparator. If the signal level is higher than the comparison reference voltage, the digital comparator outputs a high level; otherwise, it outputs a low level, forming a high-low level waveform.

[0047] Please refer to the waveform capture circuit. Figure 5 As shown, in one possible implementation, the waveform capture circuit adopts a TDC circuit, which includes: multiple corresponding D flip-flops and delay units. Multiple delay units are cascaded to form a delay line connected to the high and low level signals output by the signal waveform digital shaper. The D input terminal of the D flip-flop is connected to the output of the corresponding delay unit. The clock terminal of the D flip-flop is connected to a timing clock through a clock signal line. The output terminal of the D flip-flop outputs the latched high and low levels. Multiple D flip-flops form a D flip-flop chain and output the latched high and low level waveform sequence.

[0048] Furthermore, let the signal arrival time difference between a pair of current sensors be... Time difference This is reflected in the high and low level waveform sequences. If the difference is 1 bit, then the delay time of each delay unit on the delay line of the TDC circuit is at most 1 bit. The set capture interval time given by the clock is Then the number of D flip-flops in the delay chain of the TDC circuit is .

[0049] Specifically, due to the size limitations of the fault arcing equipment, the distance between a pair of current sensors cannot be too far, generally a few centimeters. Based on calculations and experiments, the properties of copper conductors and PVC insulation in low-voltage power distribution scenarios indicate that the current signal transmission rate is approximately 60% of the speed of light, resulting in a delay on the order of hundreds of picoseconds. Therefore, this invention needs to achieve precise timing resolution on the order of hundreds of picoseconds for the signal. This requires a high-speed waveform capture circuit capable of capturing the rapid waveform changes of high-frequency current signals, facilitating accurate waveform timing comparison of the signals input from the two sensors. This allows for determining whether the signals acquired by the two sensors originate from the same source and identifying which sensor's waveform arrives first and which lags behind.

[0050] The waveform capture circuit of this invention applies the TDC principle. The timing clock generates a synchronous clock signal at a certain time interval (e.g., 1µs). Under the action of the synchronous clock edge, the two waveform capture circuits latch the high and low level signals generated by the digital waveform shaper into the D flip-flop chain.

[0051] like Figure 5 As shown, to build a high-precision TDC circuit, this invention uses the delay line method, employing buffer gates as delay units. The basic principle of the TDC circuit is that high and low level signals sequentially pass through several delay units. When the clock signal arrives, due to the synchronicity of the clock network wiring, the clock pulse edge synchronously reaches all D flip-flops, latching the signal at each instantaneous D input terminal into the D flip-flop; that is, the D flip-flop chain latches the current delay line state. In this invention, the time delay of the signal output from the signal waveform digital shaper after passing through a single delay unit is known and equal. The D flip-flops are latching units; when the clock signal arrives, the level state between the buffer gates on the delay line will be latched to the corresponding D flip-flop Q terminal (output terminal).

[0052] The high and low levels of the delay line are fed into the serial D flip-flop chain, thus generating a set of 01 serial codes on the serial D flip-flop chain of the TDC circuit, which is equivalent to taking a snapshot of the signal waveform on the delay chain.

[0053] For example, for Figure 4 The single-pulse waveform shown assumes that the pulse exceeds the threshold high-level time by 1 ns. If each delay unit in the delay chain has a delay of 33 ps, the captured high and low level waveform sequence is approximately as follows:

[0054] 00…011111111111111111111…11111111111111111111100…0;

[0055] The number of segments with both ends set to 0 and the pulse high level (i.e., 1) is 30 consecutive segments of 1ns / 33ps.

[0056] If the signal is a multi-pulse waveform, the above sequence will contain multiple alternating sequences of 0 and 1, similar to the following figure:

[0057] 00…0111111111111000000111111111111111111111100000011111111111111100…0

[0058] This sequence represents a waveform with three consecutive 1s, representing a multi-pulse signal with three pulse impacts.

[0059] This invention utilizes two waveform capture circuits based on the TDC principle. Driven by a timing clock, it synchronously captures high and low level waveform sequences passing through a serial D flip-flop chain every 1µs. Considering the size of the fault arc circuit breaker, the installation distance between a pair of current sensors cannot be too far, for example, 0.03 meters. This is because the current transmission speed is approximately 60% of the speed of light, or about 1.8 × 10⁻⁶. 8 The speed is meters per second, and the arrival time difference between the two sensor signals is approximately 167 picoseconds. If we denote this time difference as Td, for reliability, the TDC circuit should be able to reliably represent this time difference. That is, the delay time of the delay line between each flip-flop in the TDC circuit should reliably be less than Td to reliably reflect the signal time difference in the output serial code. For example, this time difference should at least reflect a 3-bit difference in the serial code, meaning the delay of each delay unit on the TDC circuit's delay line is at most Td / 3. For a time difference of 167 picoseconds, the delay time of each delay line is at least 167ps / 3 ≈ 55ps. For a 1µs timing capture, the number of D flip-flops in the TDC circuit's delay chain is approximately 1µs / 55ps ≈ 18181.

[0060] The waveform judgment circuit performs signal source identification. In one possible implementation, the waveform judgment circuit is used to match two high-low level waveform sequences: if for each consecutive 1 sequence segment in one high-low level waveform sequence, a matching or approximately matching consecutive 1 sequence segment can be found in the other high-low level waveform sequence, and the time difference of the consecutive 1 sequence segments is consistent or approximately consistent, then the two high-low level waveform sequences are considered matched. Approximate matching means that the sequence length deviation of the consecutive 1 sequence segments is less than a threshold, and approximately consistent means that the time difference deviation is less than a threshold. For the matched two high-low level waveform sequences, the current sensor that the signal arrives at first is determined based on the time difference between the two high-low level waveform sequences, and the source of the signal is determined based on the location of the first arriving current sensor, whether it is from the external power supply side or the internal load side. The signal source determines whether to perform subsequent fault arc identification.

[0061] Specifically, the waveform determination circuit uses two sets of high and low level waveform sequences captured by the synchronous clock to correspond to the signals of the two sensors respectively. Since the two sensors are separated only by a copper wire with no circuit components in between, for a pair of sensors with the same parameters, their output analog signal waveforms are the same, and the shaped high and low level signals are also the same. The only difference is that there is a sequence position difference between the high and low level waveform sequences due to signal delay.

[0062] like Figure 6 As shown, this is a sequence of high and low level waveforms obtained by a waveform capture circuit after a single pulse waveform is acquired by a pair of sensors, shaped by a digital waveform shaper, and captured by a single-pulse waveform. It can be seen that the two sets of signal waveforms are identical, only their timing is different. Triggered by a timing clock, the waveform capture circuit converts the high and low level signals into a sequence of 0s and 1s representing high and low level waveforms. It can be seen that the binary encoding sequences are identical, indicating that they originate from the same signal source. The timing relationship of the consecutive 1s in high and low level waveform sequences 1 and 2 indicates which signal arrived first and which arrived later. By comparing their sensor positions, it is possible to distinguish whether the signal originates from the power supply side or the load side, thus making a decision regarding arc detection.

[0063] like Figure 7 As shown, real-world electric arcs or interference signals typically manifest as pulse group signals. For example... Figure 8 The diagram shows the high and low level signals of a multi-pulse signal and their corresponding high and low level waveform sequences (high and low level waveform sequence 1, high and low level waveform sequence 2). A closer analysis suggests that if we first scan high and low level waveform sequence 2, we encounter three consecutive segments of length 1. Then, scanning high and low level waveform sequence 1, we also find consecutive segments of length 1 with a time interval of 13. Continuing to scan high and low level waveform sequence 2, we encounter a consecutive segment of length 6. Scanning high and low level waveform sequence 1 again, we similarly encounter a consecutive segment of length 6. If we can find consecutive segments of length 1 with the same or similar width in another sequence, they may be matching high-pulse segments. If for each such consecutive segment of length 1, a matching segment can be found, and their time differences remain consistent, it indicates that the two waveforms are matched, and the source of the signal can be deduced from the relationship of the time differences. For example, if the high / low level waveform sequence 1 is a load-side signal waveform that lags behind the high / low level waveform sequence 2 in timing, it indicates that the signal source is a power supply-side crosstalk signal and will not be included in the subsequent fault arc identification to avoid misjudgment; conversely, if the high / low level waveform sequence 1 is a power supply-side signal waveform that also lags behind the high / low level waveform sequence 2, it indicates that the signal source is the load side and needs to be included in the subsequent fault arc identification.

[0064] Furthermore, the two high- and low-level waveform sequences are matched, including: assuming the two high- and low-level waveform sequences include a first high- and low-level waveform sequence from a first sensor and a second high- and low-level waveform sequence from a second sensor; firstly assuming the signal of the first high- and low-level waveform sequence comes first, the first and second high- and low-level waveform sequences are matched and their position differences are compared using a continuous 1-segment matching method. If the continuous 1-segment matching and the position differences are consistent, the assumption is valid, and the signal comes from the external power supply side; if the assumption that the signal of the first high- and low-level waveform sequence comes first is not valid, then the second high- and low-level waveform sequence is assumed to come first, and the second and first high- and low-level waveform sequences are matched and their position differences are compared using a continuous 1-segment matching method. If the continuous 1-segment matching and the position differences are consistent, the assumption is valid, and the signal comes from the internal load side; if neither assumption is valid, it indicates signal aliasing, and the direction cannot be determined.

[0065] Specifically, such as Figure 9 As shown (the two high and low level waveform sequences are referred to as serial code 1 and serial code 2), the signal source identification algorithm executed by the waveform judgment circuit is as follows: First, assuming that the serial code 1 signal comes first, start scanning and processing serial code 1. If a continuous segment of 1 is found, record the length of the segment. Then, scan the continuous segment of 1 in serial code 2 and compare whether their lengths are equal (considering digitization error, the length deviation can be ±1). If they are equal, it indicates that the segments are matched, and the position difference of the matched segments is recorded. Continue scanning the next continuous segment of 1. If a continuous segment of 1 in serial code 1 cannot find a matching segment, assume an error, and perform scanning and processing with serial code 2 coming first. If the continuous segment of 1 in serial code 1 finds a matching segment in serial code 2, and the position difference of each matching segment pair is consistent (also allowing an approximate consistency with a deviation of ±1), it indicates that the delay is equal, the assumption is true, and the signal source is the external power supply side. If the assumption that the serial code 1 signal comes first is not true, start scanning serial code 2 again, and perform continuous segment matching in the same way. If all segments are successfully matched and the position differences are equal, it indicates that the signal source is the load side. If neither of the two assumptions holds true, it means that the signals are aliased and the direction cannot be determined.

[0066] Furthermore, the decision to perform fault arc identification is based on the signal source; this includes: a timer clock generates periodic clock pulses to trigger the waveform judgment circuit to perform a signal source identification, generating a mask code to control the MCU of the fault arc protection device to filter and process the signal; for signals from the external power supply side, fault arc identification is not performed, and the mask code is 0; for signals from the internal load side, fault arc identification is performed, and the mask code is 1; for aliased signals with no signal or unidentifiable source, fault arc identification is not performed, and the mask code is 0.

[0067] Specifically, the synchronization clock generates a clock pulse every 1µs, triggering a signal source determination and generating a corresponding 1-bit Mask code. There are three possible signal sources: a signal from an external power supply, which is ignored and has a Mask code of 0; a signal from an internal load, which needs to be processed and has a Mask code of 1; and no signal, which does not need to be processed and also has a Mask code of 0.

[0068] Because the synchronization clock interval is very short (1µs), the probability of signal aliasing is very low, and the source direction can be effectively determined in most cases. Therefore, it can effectively prevent misjudgment caused by crosstalk noise on the power supply side, and can effectively extract the fault arc signal, thereby improving the reliability of fault arc identification.

[0069] Furthermore, the Mask code is used to control the MCU of the fault arc protection device to filter the signals collected by the current sensor, extracting only the time-slice signals with Mask code 1 and masking the time-slice signals with Mask code 0.

[0070] Specifically, the MCU of the arc fault protection device extracts the arc fault signal based on the Mask sequence (composed of Mask codes) to identify the arc fault. For example... Figure 2 The device shown uses a clock pulse generated by a timer to trigger a waveform judgment circuit to perform signal source identification, such as every 1µs. Based on the identification result, a mask code is generated and transmitted to the MCU of the arc fault protection device. The MCU of the arc fault protection device typically performs identification based on half a cycle of the power frequency AC signal; for a 50Hz power frequency line, this time interval is 10ms. Using the mask sequence generated every 1µs for valid or ignored signal periods, the MCU performs masking processing on the high-frequency AD data to be processed, such as... Figure 10 As shown, the MCU of the arc fault protection device filters the raw signal collected by the current sensor by using the Mask sequence output by the waveform judgment circuit. It extracts only the time-slice signal with a value of 1 in the Mask sequence and masks the time-slice signal with a value of 0. Finally, during the software algorithm identification, crosstalk or undetermined aliasing signals from the power supply side are masked, retaining only the high-frequency signal from the load side. This not only improves the reliability of identification but also helps to improve the accuracy of arc fault identification.

[0071] Understandably, the anti-crosstalk arc detection device for fire faults in this application employs dual current sensors at different locations in its hardware circuitry to detect high-frequency signals on the line. The signal processing circuit then determines the presence of external crosstalk signals. The signal processing circuit is mainly divided into three parts: a waveform digital shaper, a waveform capture circuit, and a waveform judgment circuit. The waveform digital shaper converts the analog signals acquired by the current sensors into high and low level signals based on a set comparison reference voltage and sends them to the waveform capture circuit, outputting a high and low level waveform sequence. The waveform capture circuit accurately records the transmission process of the digital signal on the delay line and precisely captures the timing difference between the signals sensed by the two current sensors, sending the two high and low level waveform sequences to the waveform judgment circuit. The waveform judgment circuit determines the source of the high-frequency signal based on the two sets of time-synchronized high and low level waveform sequences captured by the waveform capture circuit, thereby determining the presence of external crosstalk signals. Finally, based on the Mask sequence obtained by the above circuit, the MCU of the fault arc protection device performs shielding and filtering on the sensor analog signals collected by the AD according to the Mask sequence, thereby avoiding false operation caused by crosstalk and improving the accuracy of fault arc handling.

[0072] Please see Figure 11 As shown, Figure 11 This is a schematic diagram of air conditioner fault arc detection provided in an embodiment of this application. Figure 11 As shown, after completing the hardware connection, the following internal steps are executed: 1. The waveform judgment circuit identifies the order of the two sensor signals. If it determines that there is external crosstalk signal on the line, then fault arc detection is not performed at this time. Otherwise, it is assumed that the noise on the line comes from the air conditioner load, and fault arc detection is required. 2. If it is confirmed that fault arc detection is required, the sensor signal after filtering and amplification by the signal processing circuit is sent to the MCU. 3. The MCU uses the Mask sequence generated by the waveform judgment circuit at a 10ms time interval to filter the signals collected by the AD converter. 4. The MCU runs the existing software algorithm to extract feature quantities. 5. The extracted feature quantities are sent to the existing arc recognition model, and the presence of fault arc is determined based on the feature quantities and the model.

[0073] Similarly, it can be extended to other types of home appliance load scenarios and applied to general-purpose arc fault circuit interrupters (AFCI / AFDD).

[0074] Please see Figure 12 , Figure 12 This is a flowchart of a crosstalk-resistant arc detection method for fire faults provided in an embodiment of this application, based on, as Figure 2The anti-crosstalk arc detection device for fire faults shown in the figure executes the following method: S1, acquiring signals based on a pair of current sensors installed on the internal electrical circuit to obtain a first analog signal and a second analog signal; S2, digitally shaping the first analog signal and the second analog signal based on a pair of signal waveform digital shapers to obtain a first high-low level signal and a second high-low level signal; S3, synchronously capturing the first high-low level signal and the second high-low level signal based on a timing clock and a pair of waveform capture circuits to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; S4, matching and comparing the first high-low level waveform sequence and the second high-low level waveform sequence based on a waveform judgment circuit to determine the signal source.

[0075] Specifically, the crosstalk-resistant arc fault detection method provided by this invention utilizes a pair of waveform capture circuits to synchronously capture high and low level waveform sequences every 1µs, driven by a timing clock. A signal source determination circuit compares and matches two sets of 0 and 1 sequences. If the waveforms are identical or highly similar, the timing relationship between the two sets of waveforms is determined. If the waveforms indicate the signal originates from the load side, subsequent arc fault identification proceeds; if the signal waveform originates from an external power supply side, identification of that time segment is abandoned, thus eliminating interference from external crosstalk signals and improving the reliability of arc fault detection. If the signal originates from two directions, the waveforms will overlap and cannot be matched, indicating that the time segment is noisy, and identification is also abandoned.

[0076] It is evident that the anti-crosstalk arc detection device and method provided in this application can improve the detection accuracy and reliability of arc faults occurring on lines while eliminating external noise interference.

[0077] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A crosstalk-resistant arc detection device for fire faults, characterized in that, include: A pair of current sensors: a first sensor and a second sensor, the first sensor and the second sensor are located on the internal electrical circuit of the fault arc protection device and are a certain distance apart, the first sensor first collects the signal from the external power supply side, and the second sensor first collects the signal from the internal load side; A pair of signal waveform digital shapers: a first signal waveform digital shaper and a second signal waveform digital shaper, wherein the first signal waveform digital shaper is connected to the first sensor and the second signal waveform digital shaper is connected to the second sensor; A pair of waveform capture circuits: a first waveform capture circuit and a second waveform capture circuit, wherein the first waveform capture circuit is connected to the first signal waveform digital shaper, and the second waveform capture circuit is connected to the second signal waveform digital shaper; The waveform judgment circuit, connected to the first waveform capture circuit and the second waveform capture circuit, is used to determine the signal source by waveform matching timing comparison, and decide whether to perform subsequent fault arc identification based on the signal source. A timing clock is connected to the first waveform capture circuit, the second waveform capture circuit, and the waveform judgment circuit. The waveform capture circuit employs a TDC circuit, which includes multiple corresponding D flip-flops and delay units. Multiple delay units are cascaded to form a delay line connected to the high and low level signals output by a digital waveform shaper. The D input of the D flip-flop is connected to the output of the corresponding delay unit. The clock input of the D flip-flop is connected to a timing clock via a clock signal line. The output of the D flip-flop outputs latched high and low levels. Multiple D flip-flops form a D flip-flop chain, outputting a latched high and low level waveform sequence. The first sensor and the second sensor are connected only by a wire of the same specifications.

2. The anti-crosstalk arc detection device for fire faults according to claim 1, characterized in that, The signal waveform digital shaper uses a digital comparator to convert the analog signals output by the first and second sensors into high and low level signals.

3. The anti-crosstalk arc detection device for fire faults according to claim 1, characterized in that, it is provided that... The time difference between the arrival signals of a pair of current sensors is Time difference This is reflected in the high and low level waveform sequences. If the difference is 1 bit, then the delay time of each delay unit on the delay line of the TDC circuit is at most 1 bit. The set capture interval time given by the clock is Then the number of D flip-flops in the delay chain of the TDC circuit is .

4. The anti-crosstalk arc detection device for fire faults according to claim 1, characterized in that, The waveform judgment circuit is used to match two high and low level waveform sequences: if for each consecutive 1 sequence segment in one high and low level waveform sequence, a matching or approximately matching consecutive 1 sequence segment can be found in the other high and low level waveform sequence, and the time difference of the consecutive 1 sequence segments is consistent or approximately consistent, then it means that the two high and low level waveform sequences are matched. The approximately matching means that the sequence length deviation of the consecutive 1 sequence segments is less than a threshold, and the approximately consistent means that the time difference deviation is less than a threshold. For the two matched high and low level waveform sequences, the current sensor that the signal arrives first is determined based on the time difference between the two high and low level waveform sequences, and the source of the signal is determined based on the location of the current sensor that arrives first, whether it is from the external power supply side or the internal load side. Whether to proceed with subsequent fault arc identification depends on the source of the signal.

5. The anti-crosstalk arc detection device for fire faults according to claim 4, characterized in that, Matching two high and low level waveform sequences; including: Assume the two high-low level waveform sequences include: a first high-low level waveform sequence from the first sensor and a second high-low level waveform sequence from the second sensor; First, assume that the signal of the first high-low level waveform sequence comes first. Then, perform continuous segment matching and position difference comparison on the first high-low level waveform sequence and the second high-low level waveform sequence. If the continuous segment matching and the position difference are consistent, it means that the assumption is valid and the signal comes from the external power supply side. If the assumption that the signal of the first high-low level waveform sequence comes first is not true, then assume that the signal of the second high-low level waveform sequence comes first. Perform continuous 1-segment matching and position difference comparison on the second high-low level waveform sequence and the first high-low level waveform sequence. If the continuous 1-segment matching and the position difference are consistent, it means that the assumption is true and the signal comes from the internal load side. If neither of the two assumptions is established, it indicates signal aliasing, and the direction cannot be determined.

6. The anti-crosstalk arc detection device for fire faults according to claim 4, characterized in that, Whether to perform fault arc identification depends on the source of the signal; include: The timing clock generates periodic clock pulses, triggering the waveform judgment circuit to identify the signal source and generate a mask code, which is used to control the MCU of the fault arc protection equipment to filter and process the signal. For signals from the external power supply side, they are not entered into fault arc identification, and the Mask code is 0. For signals from the internal load side, enter the fault arc identification, and the Mask code is 1; For aliased signals with no signal or whose source cannot be identified, the fault arc identification is not initiated, and the Mask code is 0.

7. The anti-crosstalk arc detection device for fire faults according to claim 6, characterized in that, The Mask code is used to control the MCU of the fault arc protection device to filter the signals collected by the current sensor, extracting only the time slice signals with Mask code 1 and masking the time slice signals with Mask code 0.

8. A method for detecting fire-causing arc faults with anti-crosstalk, characterized in that, The method is performed based on the anti-crosstalk arc detection device for fire faults as described in any one of claims 1-7, and includes: S1. Based on a pair of current sensors installed on the internal electrical circuit, signals are collected to obtain a first analog signal and a second analog signal; S2. Based on a pair of signal waveform digital shapers, the first analog signal and the second analog signal are digitally shaped to obtain a first high-low level signal and a second high-low level signal. S3. Based on a timing clock and a pair of waveform capture circuits, the first high-low level signal and the second high-low level signal are synchronously captured to obtain the first high-low level waveform sequence and the second high-low level waveform sequence. S4. Based on the waveform judgment circuit, the first high and low level waveform sequences and the second high and low level waveform sequences are matched and compared to determine the signal source.

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