Solutions and systems for conflicts when dual-motherboard BMC accesses shared devices

Abstract

This invention discloses a solution, system, and computer device for resolving conflicts when dual-motherboard BMC accesses shared devices. Belonging to the computer field, this method replaces traditional CPLD chips with GPIO cross-interconnection by physically connecting the hardware interlocking paths of the GPIOs of the two motherboards via electrical signals. This saves on the design and manufacturing costs of control cards between the two motherboards, allowing the freed-up chassis space to be used for other devices, thus enhancing product competitiveness. Simultaneously, it reduces overall power consumption, improves chassis heat dissipation, reduces latency, and increases processing efficiency.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, specifically to a solution and system for resolving conflicts when dual-motherboard BMCs access shared devices. Background Technology

[0002] The dual-controller storage server has two motherboards, each with its own BMC chip. These two motherboards share a common power supply and a common VPD sensor. In addition to monitoring its own motherboard's hardware information, each motherboard's BMC chip also needs to access the shared power supply and VPD sensor via an I2C link.

[0003] To resolve conflicts caused by two motherboards' BMCs accessing a shared device via I2C, current technology typically involves designing a small card inside the chassis. This card's CPLD stores the current access status of the shared device. Alternatively, separate CPLDs can be configured on each of the two motherboards. Regardless of which motherboard's BMC needs to access the shared device, it first checks the CPLD register. If the CPLD register is in a busy state, it indicates that the other motherboard is currently accessing the device, and the motherboard must wait until the busy state changes to an idle state before it can access the device.

[0004] While this solution solves the problem of multiple BMCs accessing a shared device, it requires adding a small card inside the machine or adding a design to the motherboard, increasing design and manufacturing costs, increasing device power consumption, and occupying valuable space inside the chassis.

[0005] Therefore, how to achieve conflict-free access to shared devices by dual motherboard BMCs without adding a dedicated control chip, while meeting the space constraints and cost control requirements of the server chassis, is the technical problem that this invention urgently needs to solve.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] To overcome the shortcomings of existing technologies, a solution and method for resolving conflicts when dual motherboard BMCs access shared devices are provided. This addresses the problems of increased design and manufacturing costs, increased device power consumption, and limited effective space within the chassis caused by using a CPLD as an access arbitrator.

[0008] To achieve the above objectives, a solution to the conflict of dual-motherboard BMC accessing a shared device is provided, including: In a dual-motherboard architecture, the first motherboard and the second motherboard each have a Baseboard Management Controller (BMC), and the two BMCs are connected to a common device. The BMC of the first motherboard is connected to the first GPIO group, and the BMC of the second motherboard is connected to the second GPIO group. The output terminal of the first GPIO group and the input terminal of the second GPIO group are cross-interconnected to form a hardware interlocking path. When the first motherboard (BMC) needs to access the shared device, it performs the following operations: S1: The first motherboard BMC detects the level signal status of the second GPIO group of the second motherboard BMC through the first GPIO group; S2: If the second GPIO group is detected to be occupied, wait for a preset time t1 and then re-execute step S1; S3: If the second GPIO group is detected to be in an unoccupied state, the first GPIO group of the first motherboard BMC is set to an occupied signal, and the second GPIO group of the second motherboard BMC is synchronously triggered to be in an occupied state through the hardware interlocking path; S4: The first motherboard BMC performs exclusive access to the shared device; S5: After the access is completed, the first motherboard BMC resets the first GPIO group to an unoccupied state, and synchronously resets the second GPIO group of the second motherboard BMC through the hardware interlocking path.

[0009] Preferably, the occupied state is defined as a high-level signal state; the unoccupied state is defined as a low-level signal state.

[0010] Preferably, the shared device includes a VPD sensor and a PMIC power management chip, and the access operation includes reading device identification information and adjusting power parameters; the BMC communicates via I... 2 The C-bus reads sensor data or sends control commands.

[0011] Preferably, the first GPIO group includes GPIO_11 and GPIO_12 interfaces, and the second GPIO group includes GPIO_21 and GPIO_22 interfaces; the GPIO_11 and GPIO_21 interfaces are physically connected, and the GPIO_12 and GPIO_22 interfaces are physically connected; the first GPIO group implements at least one of the following operations: The GPIO_12 interface detected the level signal status of the GPIO_22 interface; The GPIO_11 interface is set to a high / low level signal state; The GPIO_11 interface synchronously triggers the level signal state of the GPIO_21 interface through a hardware interlocking path; The second GPIO group must implement at least one of the following operations: The GPIO_21 interface detected the level signal status of the GPIO_11 interface; The GPIO_22 interface is set to a high / low level signal state; The GPIO_22 interface synchronously triggers the level signal state of the GPIO_12 interface through a hardware interlocking path.

[0012] Preferably, the exclusive access operation time in S4 does not exceed the preset time t2. If no release command is received within the timeout period, the following processing flow is automatically triggered: Send fault codes via a separate fault signal pin; Force all GPIO group levels to low; Record the "GPIO timeout forced release" event in the system log.

[0013] Preferably, a heartbeat detection mechanism is also included, in which the first motherboard and the second motherboard periodically send heartbeat signals to each other. When either motherboard does not receive a heartbeat signal from the other for at least one cycle, it forcibly resets all GPIO groups to an unoccupied state and takes over the access permissions of shared devices until the heartbeat is restored.

[0014] This invention also provides a system for resolving conflicts when dual-motherboard BMC accesses a shared device, comprising: The first motherboard has a baseboard management controller (BMC) and a first GPIO group. The BMC of the first motherboard is connected to a shared device. The first motherboard also has a first GPIO control module for controlling the output level signal state of the first GPIO group, and a first conflict detection module for determining the occupancy state of the shared device based on the level signal state. The second motherboard is equipped with a baseboard management controller (BMC) and a second GPIO group. The BMC of the second motherboard is connected to the shared device. The second motherboard is also equipped with a second GPIO control module for controlling the output level signal status of the second GPIO group. The second motherboard is also equipped with a second conflict detection module for determining the occupancy status of the shared device based on the level signal status. The output of the first GPIO group and the input of the second GPIO group are interconnected to form a hardware interlocking path.

[0015] Preferably, both the first motherboard and the second motherboard are configured with a timeout forced release module, configured to perform at least one of the following behaviors when the duration of the GPIO occupied signal exceeds a threshold t2: Send a preset fault code via an independent fault signal pin; Force all GPIO group levels to low; Record timeout events and snapshots of abnormal states in the BMC log.

[0016] Preferably, both the first motherboard and the second motherboard are equipped with a heartbeat monitoring module, which is used for the two motherboards to periodically send heartbeat signals to each other. When either motherboard does not receive a heartbeat signal from the other for at least one cycle, it forcibly resets all GPIO groups to an unoccupied state and takes over the access permissions of the shared device until the heartbeat is restored.

[0017] The present invention also provides a computer device including one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the device, cause the device to perform the method as described above.

[0018] The beneficial effect of this invention is that it saves the design and manufacturing costs of the control card between the two motherboards, allowing the saved chassis space to be used to add other devices and enhance the competitiveness of the product.

[0019] The beneficial effect of this invention is that by eliminating one card inside the chassis, the overall power consumption can be reduced and the heat dissipation effect of the chassis can be enhanced.

[0020] The beneficial effect of this invention is that the hardware interlocking path of the GPIO of the dual motherboards, through the physical direct connection of electrical signals, can reduce latency and improve processing efficiency. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the system architecture for resolving conflicts when dual motherboard BMCs access shared devices, according to an embodiment of the present invention.

[0022] Figure 2 This is a flowchart illustrating a conflict resolution system for dual-motherboard BMC access to shared devices according to an embodiment of the present invention.

[0023] Figure 3 This is another flowchart illustrating the conflict resolution system for dual-motherboard BMC access to shared devices according to an embodiment of the present invention. Detailed Implementation

[0024] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] Example of a solution to conflicts when dual-motherboard BMC accesses a shared device Reference Figures 1 to 3 As shown, this embodiment discloses a solution to the conflict of dual motherboard BMC accessing a shared device. The method is applied in a dual motherboard architecture, where the first motherboard and the second motherboard each set up a Baseboard Management Controller (BMC), and the two BMCs are connected to a shared device.

[0027] Specifically, the BMCs of the two motherboards communicate via I 2 The C-bus connects to a shared device. Furthermore, this shared device may include the following key devices: VPD sensors: store hardware identification information (such as serial number and firmware version). PMIC power management chip: monitors and adjusts CPU / memory power supply parameters.

[0028] Furthermore, the BMC of the first motherboard is connected to the first GPIO group, and the BMC of the second motherboard is connected to the second GPIO group. The output terminals of the first GPIO group and the input terminals of the second GPIO group are cross-interconnected to form a hardware interlocking path. The first GPIO group and the second GPIO group can be directly connected through physical circuitry. Furthermore, the first GPIO group includes GPIO_11 and GPIO_12 interfaces, and the second GPIO group includes GPIO_21 and GPIO_22 interfaces; the GPIO_11 and GPIO_21 interfaces are physically connected, and the GPIO_12 and GPIO_22 interfaces are physically connected.

[0029] Furthermore, both the first and second motherboards are equipped with independent communication channels for periodic heartbeat detection. Preferably, an I2C_1 is provided on both the first and second motherboards as an independent communication channel specifically designed for heartbeat detection between the two motherboards. This channel is physically isolated from the I2C bus (hereinafter referred to as the device access bus) used to access shared devices and is used only for transmitting heartbeat signals and system health status data between the two motherboards.

[0030] When the first motherboard (BMC) needs to access the shared device, it performs the following operations: S1: The first motherboard BMC detects the level signal status of the second GPIO group of the second motherboard BMC through the first GPIO group.

[0031] Specifically, the first motherboard BMC detects the level signal status of the GPIO_22 interface through the GPIO_12 interface of the first GPIO group. Preferably, in this embodiment, the occupied / unoccupied state is set by the level signal status. Further, in this embodiment, a high level signal status is preset to represent the occupied state of the shared device, and a low level signal status represents the unoccupied state of the shared device.

[0032] S2: If the second GPIO group is detected to be occupied, wait for a preset time t1 and then re-execute step S1.

[0033] Specifically, if the GPIO_12 interface detects a high level on the GPIO_22 interface, it indicates that the second motherboard, according to a preset definition, is exclusively accessing the shared device, and the shared device is occupied. The first motherboard's BMC will then re-detect after a preset time t1. Furthermore, the preset time t1 can be 1 second or is not limited to this.

[0034] S3: If the second GPIO group is detected to be unoccupied, the first motherboard BMC sets the first GPIO group to an occupied state and synchronously triggers the second motherboard BMC to be occupied through the hardware interlocking path.

[0035] Specifically, after the first motherboard completes the initial detection or several preset time t1 detection cycles, if the GPIO_12 interface detects that the GPIO_22 interface is at a low level, it means that the second motherboard, according to the preset definition, ends exclusive access to the shared device at this time, and the shared device is not occupied.

[0036] S4: The first motherboard BMC performs exclusive access to the shared device.

[0037] Specifically, after the GPIO_12 interface detects that the GPIO_22 interface is at a low level and the shared device is not occupied, the first motherboard BMC initiates an access operation.

[0038] S5: After the access is completed, the first motherboard BMC resets the first GPIO group to an unoccupied state, and synchronously resets the second GPIO group of the second motherboard BMC through the hardware interlocking path.

[0039] Specifically, during access by the first motherboard's BMC, the GPIO_11 interface is set to a high-level signal state. At the same time, the GPIO_11 interface synchronously triggers the GPIO_21 interface to a low-level signal state through a hardware interlocking path, enabling the second motherboard to recognize, according to a preset definition, that the shared device is being exclusively accessed and operated by the first motherboard and is in an occupied state.

[0040] It should be noted that the high / low level signal states are predefined as occupied / unoccupied states. The above is just one form of expression and is not the only one.

[0041] In a preferred embodiment of this example, the exclusive access operation time in S4 does not exceed a preset time t2. If no release command is received after the timeout, the following processing flow is automatically triggered: Send fault codes via a separate fault signal pin; Force all GPIO group levels to low; The system log records a "GPIO timeout forced release" event. This scenario corresponds to one motherboard experiencing a timeout deadlock during access, preventing the other motherboard from recognizing and accessing it. For example, after 180 days of continuous operation, the BMC of a dual-controller server in a financial data center experienced a memory leak, causing the GPIO release thread to become blocked. The timeout forced release module, upon reaching the 10-second threshold, sends a fault code 0x55 to the chassis management module via GPIO_13, triggering an alarm SMS notification; uses the strong pull-down function of the SN74LVC1T45 level converter chip to forcibly reset the GPIO_11 / 12 level to 0V; and generates a fault entry in the BMC log.

[0042] As a preferred embodiment of this method, the method also includes a heartbeat detection mechanism. The first motherboard and the second motherboard periodically exchange heartbeat signals. When either motherboard fails to receive a heartbeat signal from the other for at least one cycle, it forcibly resets all GPIO groups to an unoccupied state and takes over the access permissions of the shared device until the heartbeat is restored. This scenario corresponds to a failure of one of the motherboards resulting in the loss of the heartbeat. For example: the first motherboard sends an encrypted heartbeat packet to the second motherboard every second via I2C_1; the second motherboard replies with a heartbeat signal after verifying the signature validity; the BMCs of both motherboards exchange health data such as temperature and load. If the heartbeat of the second motherboard is lost, the first motherboard forcibly takes over the GPIO until the heartbeat of the other motherboard returns to normal. Specifically, if the first motherboard (healthy) detects that the second motherboard (faulty) has failed to respond to the heartbeat three times consecutively via I2C_1, it forcibly pulls the input of GPIO_22 of the second motherboard low by outputting a low level on its GPIO_12; and forcibly pulls the input of GPIO_21 of the second motherboard low by outputting a low level on its GPIO_11.

[0043] Exemplary dual-motherboard BMC access shared device conflict resolution system A dual-motherboard BMC conflict resolution system for accessing a shared device includes a first motherboard and a second motherboard. The first motherboard has a Baseboard Management Controller (BMC) and a first GPIO group, and its BMC is connected to the shared device. The first motherboard also has a first GPIO control module for controlling the output level signal state of the first GPIO group, and a first conflict detection module for determining the shared device's occupancy status based on the level signal state. The second motherboard has a Baseboard Management Controller (BMC) and a second GPIO group, and its BMC is connected to the shared device. The second motherboard also has a second GPIO control module for controlling the output level signal state of the second GPIO group, and a second conflict detection module for determining the shared device's occupancy status based on the level signal state. Furthermore, the output terminals of the first GPIO group and the input terminals of the second GPIO group are cross-interconnected, forming a hardware interlocked path.

[0044] Preferably, both the first motherboard and the second motherboard are configured with a timeout forced release module, configured to perform at least one of the following behaviors when the duration of the GPIO occupied signal exceeds a threshold t2: Send a preset fault code via an independent fault signal pin; Force all GPIO group levels low (through strong pull-down circuits; pull-up / pull-down resistors are common circuit designs, so they will not be elaborated on). Record timeout events and snapshots of abnormal states in the BMC log.

[0045] Preferably, both the first motherboard and the second motherboard are equipped with a heartbeat monitoring module, which is used for the two motherboards to periodically send heartbeat signals to each other. When either motherboard does not receive a heartbeat signal from the other for at least one cycle, it forcibly resets all GPIO groups to an unoccupied state and takes over the access permissions of the shared device until the heartbeat is restored.

[0046] Furthermore, the configurations of the first and second motherboards are identical. BMC: Equipped with an ARM Cortex-A9 processor, running OpenBMC firmware; First GPIO group (including GPIO_11 (output) and GPIO_12 (input); Timeout forced release module: Integrated MAX6374 hardware timer (accuracy ±1%); Heartbeat monitoring module: Sends encrypted heartbeat packets via I2C_1; First and second conflict detection modules: Such as level comparators, state machines, etc.; First and second GPIO control modules: Level conversion circuit (using SN74LVC1T45 chip, supporting 3.3V / 5V dual voltage).

[0047] Exemplary computer device This embodiment provides a computer device including one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the device, cause the device to perform the dual-motherboard BMC access shared device conflict resolution method as described above.

[0048] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A solution to conflicts arising from dual-motherboard BMC accessing a shared device, characterized in that, include: In a dual-motherboard architecture, the first motherboard and the second motherboard each have a Baseboard Management Controller (BMC), and the two BMCs are connected to a common device. The BMC of the first motherboard is connected to the first GPIO group, and the BMC of the second motherboard is connected to the second GPIO group. The output terminal of the first GPIO group and the input terminal of the second GPIO group are cross-interconnected to form a hardware interlocking path. When the first motherboard (BMC) needs to access the shared device, it performs the following operations: S1: The first motherboard BMC detects the level signal status of the second GPIO group of the second motherboard BMC through the first GPIO group; S2: If the second GPIO group is detected to be occupied, wait for a preset time t1 and then re-execute step S1; S3: If the second GPIO group is detected to be in an unoccupied state, the first GPIO group of the first motherboard BMC is set to an occupied signal, and the second GPIO group of the second motherboard BMC is synchronously triggered to be in an occupied state through the hardware interlocking path; S4: The first motherboard BMC performs an exclusive access operation on the shared device; the exclusive access operation time in S4 does not exceed a preset time t2. If no release command is received after the timeout, the following processing flow is automatically triggered: Send fault codes via a separate fault signal pin; Force all GPIO group levels to low; Record the "GPIO timeout forced release" event in the system log; S5: After the access is completed, the first motherboard BMC resets the first GPIO group to an unoccupied state, and synchronously resets the second GPIO group of the second motherboard BMC through the hardware interlocking path; It also includes a heartbeat detection mechanism, in which the first motherboard and the second motherboard periodically send heartbeat signals to each other. When either motherboard does not receive a heartbeat signal from the other for at least one cycle, it forcibly resets all GPIO groups to an unoccupied state and takes over the access permissions of shared devices until the heartbeat is restored.

2. The method for resolving conflicts when dual-motherboard BMC accesses a shared device according to claim 1, characterized in that, The occupied state is defined as a high-level signal state; the unoccupied state is defined as a low-level signal state.

3. The method for resolving conflicts when dual-motherboard BMCs access shared devices according to claim 1, characterized in that, The shared equipment includes a VPD sensor and a PMIC power management chip, and the access operation includes reading device identity information and adjusting power parameters; the BMC communicates via I... 2 The C-bus reads sensor data or sends control commands.

4. The method for resolving conflicts when dual-motherboard BMC accesses a shared device according to claim 1, characterized in that, The first GPIO group includes GPIO_11 and GPIO_12 interfaces, and the second GPIO group includes GPIO_21 and GPIO_22 interfaces; the GPIO_11 and GPIO_21 interfaces are physically connected, and the GPIO_12 and GPIO_22 interfaces are physically connected; the first GPIO group implements at least one of the following operations: The GPIO_12 interface detected the level signal status of the GPIO_22 interface; The GPIO_11 interface is set to a high / low level signal state; The GPIO_11 interface synchronously triggers the level signal state of the GPIO_21 interface through a hardware interlocking path; The second GPIO group must implement at least one of the following operations: The GPIO_21 interface detected the level signal status of the GPIO_11 interface; The GPIO_22 interface is set to a high / low level signal state; The GPIO_22 interface synchronously triggers the level signal state of the GPIO_12 interface through a hardware interlocking path.

5. A dual-motherboard BMC access shared device conflict resolution system that implements the dual-motherboard BMC access shared device conflict resolution method as described in claim 1, characterized in that, include: The first motherboard has a baseboard management controller (BMC) and a first GPIO group. The BMC of the first motherboard is connected to a shared device. The first motherboard also has a first GPIO control module for controlling the output level signal state of the first GPIO group, and a first conflict detection module for determining the occupancy state of the shared device based on the level signal state. The second motherboard is equipped with a baseboard management controller (BMC) and a second GPIO group. The BMC of the second motherboard is connected to the shared device. The second motherboard is also equipped with a second GPIO control module for controlling the output level signal status of the second GPIO group. The second motherboard is also equipped with a second conflict detection module for determining the occupancy status of the shared device based on the level signal status. The output of the first GPIO group and the input of the second GPIO group are interconnected to form a hardware interlocking path.

6. The dual-motherboard BMC access shared device conflict resolution system according to claim 5, characterized in that, Both the first motherboard and the second motherboard are configured with a timeout forced release module, configured to perform at least one of the following behaviors when the duration of the GPIO occupied signal exceeds a threshold t2: Send a preset fault code via an independent fault signal pin; Force all GPIO group levels to low; Record timeout events and snapshots of abnormal states in the BMC log.

7. The dual-motherboard BMC access shared device conflict resolution system according to claim 5, characterized in that, Both the first motherboard and the second motherboard are equipped with a heartbeat monitoring module, which is used for the two motherboards to periodically send heartbeat signals to each other. When either motherboard does not receive a heartbeat signal from the other for at least one cycle, it will forcibly reset all GPIO groups to an unoccupied state and take over the access permissions of shared devices until the heartbeat is restored.

8. A computer device comprising one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the device, cause the device to perform the method as claimed in any one of claims 1 to 4.

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