Driving circuit, driving method, driving module and display device

Abstract

The present disclosure provides a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; N is a positive integer; the first gating circuit controls writing of a gating input signal into a first first node under control of a gating control signal; the first output circuit controls communication between an Nth output driving end and a first voltage end under control of a potential of a first second node, and controls communication between the Nth output driving end and a second voltage end under control of a potential of a first third control node; the first third control node and the first second control node are different nodes. The present disclosure can realize updating of a local picture of a display screen by controlling the gating input signal, thereby reducing power consumption.

Description

[0001] This application is a divisional application of the invention application filed on December 18, 2023, with application number 202380012374.2. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving method, driving module and display device. Background Technology

[0003] In related technologies, when updating the screen of an OLED (Organic Light Emitting Diode) display, the pixel voltage of all row pixel circuits needs to be initialized and written within one frame. However, in certain special screen conditions (such as Always-On Display (AOD) screens, where only a portion of the screen is illuminated without lighting up the entire phone screen), static screens, or screens with infrequent updates), most pixel circuits on the screen do not need to update their pixel voltages. That is, most pixel circuits can maintain their original display brightness through low-leakage LTPO (Low Temperature Polycrystalline Oxide) TFTs (Thin Film Transistors). Repeatedly writing and updating these pixel circuits results in wasted power consumption. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a driving circuit, including a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit, and a first output circuit; N is a positive integer;

[0005] The first drive signal generation circuit is electrically connected to the first first control node, the first second control node and the Nth stage drive signal output terminal, respectively, and is used to generate and output the Nth stage drive signal through the Nth stage drive signal output terminal under the control of the potential of the first first control node and the potential of the first second control node.

[0006] The first output control circuit is electrically connected to the first first node, the first first control node, and the first second node, respectively, and is used to control the connection between the first first control node and the first second node under the control of the potential of the first first node;

[0007] The first gating circuit is electrically connected to the first first node, the gating input terminal and the gating control terminal respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first first node under the control of the gating control signal provided by the gating control terminal;

[0008] The first energy storage circuit is electrically connected to the first first node and the first second node respectively, and is used to control the potential of the first second node according to the potential of the first first node;

[0009] The first second energy storage circuit is electrically connected to the first third control node and the Nth stage output drive terminal respectively, and is used to control the potential of the first third control node according to the Nth stage drive output signal provided by the Nth stage output drive terminal;

[0010] The first output circuit is electrically connected to the first second node, the first third control node, the first voltage terminal, the second voltage terminal, and the Nth stage output drive terminal, respectively. It is used to control the Nth stage output drive terminal to connect with the first voltage terminal under the control of the potential of the first second node, and to control the Nth stage output drive terminal to connect with the second voltage terminal under the control of the potential of the first third control node.

[0011] The first third control node is a different node from the first second control node.

[0012] Optionally, the first gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first first node when the potential of the first third node in the N-1th stage is the second voltage and the potential of the Nth stage driving signal is the second voltage.

[0013] Optionally, the first gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0014] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the first gating circuit includes a first first transistor and a first second transistor;

[0015] The gate of the first transistor is electrically connected to the first gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the first second transistor.

[0016] The gate of the first second transistor is electrically connected to the second gating control terminal, and the second terminal of the first second transistor is electrically connected to the gating input terminal.

[0017] The first gating control terminal is the Nth stage drive signal output terminal, and the second gating control terminal is the first third node of the (N-1)th stage. Both the first first transistor and the first second transistor are p-type transistors; or...

[0018] The first gating control terminal is the first third node of the (N-1)th stage, the second gating control terminal is the drive signal output terminal of the Nth stage, and both the first first transistor and the first second transistor are p-type transistors; or...

[0019] The first gating control terminal is the output terminal of the (N-1)th stage drive signal, the second gating control terminal is the output terminal of the Nth stage drive signal, the first transistor is an n-type transistor, and the first transistor is a p-type transistor; or...

[0020] The first gating control terminal is the output terminal of the Nth stage drive signal, the second gating control terminal is the output terminal of the (N-1)th stage drive signal, the first transistor is a p-type transistor, and the first transistor is an n-type transistor; or...

[0021] The first gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal, and the second gating control terminal is the output terminal of the Nth stage drive signal. Both the first transistor and the first second transistor are p-type transistors; or...

[0022] The first gating control terminal is the output terminal of the Nth stage drive signal, and the second gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal; both the first first transistor and the first second transistor are p-type transistors; or,

[0023] The first gating control terminal is the (N-1)th stage drive signal terminal, and the second gating control terminal is connected to the inverted signal of the Nth stage drive signal. Both the first transistor and the first second transistor are n-type transistors; or...

[0024] The first gating control terminal is connected to the inverted signal of the Nth stage drive signal, the second gating control terminal is the N-1th stage drive signal terminal, and the first first transistor and the first second transistor are both n-type transistors.

[0025] Optionally, the first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor;

[0026] The first terminal of the first capacitor is electrically connected to the first first node, and the second terminal of the first capacitor is electrically connected to the first second node;

[0027] The first terminal of the first second capacitor is electrically connected to the first third control node, and the second terminal of the first second capacitor is electrically connected to the Nth stage output drive terminal.

[0028] Optionally, the first output control circuit includes a first third transistor;

[0029] The gate of the first third transistor is electrically connected to the first first node, the first electrode of the first third transistor is electrically connected to the first first control node, and the second electrode of the first third transistor is electrically connected to the first second node.

[0030] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first second node control circuit;

[0031] The first second node control circuit is electrically connected to the first third control node, the first second node, and the first voltage terminal, respectively, and is used to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node.

[0032] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first second node control circuit;

[0033] The first second node control circuit is electrically connected to the first third control node, the Nth stage output drive terminal, the first second node, and the first voltage terminal, respectively, and is used to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage drive output signal provided by the Nth stage output drive terminal.

[0034] Optionally, the first second node control circuit includes a first fourth transistor;

[0035] The gate of the first fourth transistor is electrically connected to the first third control node, the first terminal of the first fourth transistor is electrically connected to the first second node, and the second terminal of the first fourth transistor is electrically connected to the first voltage terminal.

[0036] Optionally, the first second node control circuit includes a first fourth transistor and a first control transistor;

[0037] The gate of the first fourth transistor is electrically connected to the first third control node, the first terminal of the first fourth transistor is electrically connected to the second terminal of the first control transistor, and the second terminal of the first fourth transistor is electrically connected to the first voltage terminal.

[0038] The gate of the first control transistor is electrically connected to the Nth stage output drive terminal, and the first electrode of the first control transistor is electrically connected to the first second node.

[0039] Optionally, the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor;

[0040] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the first fifth transistor is electrically connected to the Nth stage output drive terminal.

[0041] The gate of the first sixth transistor is electrically connected to the first third control node, the first terminal of the first sixth transistor is electrically connected to the Nth stage output drive terminal, and the second terminal of the first sixth transistor is electrically connected to the second voltage terminal.

[0042] The first terminal of the first third capacitor is electrically connected to the first second node, and the second terminal of the first third capacitor is electrically connected to the first voltage terminal.

[0043] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first initialization circuit;

[0044] The first initialization circuit is electrically connected to the initial control terminal, the second voltage terminal, and the first first node, respectively, and is used to control the connection between the first first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0045] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit;

[0046] The first node control circuit is electrically connected to the first fourth node, the second voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the first fourth node.

[0047] Optionally, the first initialization circuit includes a first seventh transistor;

[0048] The gate of the first seventh transistor is electrically connected to the initial control terminal, the first terminal of the first seventh transistor is electrically connected to the first first node, and the second terminal of the first seventh transistor is electrically connected to the second voltage terminal.

[0049] Optionally, the first node control circuit includes a first eighth transistor;

[0050] The gate of the first eighth transistor is electrically connected to the first fourth node, the first terminal of the first eighth transistor is electrically connected to the first first node, and the second terminal of the first eighth transistor is electrically connected to the second voltage terminal.

[0051] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first third control node control circuit;

[0052] The first third control node control circuit is electrically connected to the first first node, the first fifth node, the first second control node, the first third control node, and the first sixth node, respectively. It is used to control the connection between the first fifth node and the first third control node under the control of the potential of the first first node, control the connection between the first second control node and the first sixth node under the control of the potential of the first sixth node, and control the connection between the first sixth node and the first third control node.

[0053] Optionally, the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor;

[0054] The gate of the first ninth transistor is electrically connected to the first first node, the first electrode of the first ninth transistor is electrically connected to the first fifth node, and the second electrode of the first ninth transistor is electrically connected to the first third control node.

[0055] The gate and the second terminal of the first tenth transistor are both electrically connected to the first sixth node, and the first terminal of the first tenth transistor is electrically connected to the first second control node;

[0056] The gate of the first eleventh transistor and the first terminal of the first eleventh transistor are both electrically connected to the first sixth node, and the second terminal of the first eleventh transistor is electrically connected to the first third control node.

[0057] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first output pull-down circuit;

[0058] The first output pull-down circuit is electrically connected to the first control node, the Nth stage drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the first control node.

[0059] Optionally, the first drive signal generation circuit includes a first first drive output circuit, a first second drive output circuit, a first first control node control circuit, and a first second control node control circuit.

[0060] The first control node control circuit is used to control the potential of the first control node;

[0061] The first second control node control circuit is used to control the potential of the first second control node;

[0062] The first first drive output circuit is electrically connected to the first first control node, the first voltage terminal and the Nth stage drive signal output terminal respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the potential of the first first control node;

[0063] The first second drive output circuit is electrically connected to the first second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the first second control node.

[0064] Optionally, the first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit.

[0065] The first seventh node control circuit is electrically connected to the seventh node, the second voltage terminal, the first clock signal terminal and the first fifth node respectively, and is used to control the connection between the first seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of the potential of the first fifth node.

[0066] The first eighth node control circuit is electrically connected to the second voltage terminal, the first seventh node, and the first eighth node, respectively, and is used to control the connection between the first seventh node and the first eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0067] The first third node control circuit is electrically connected to the first eighth node, the second clock signal terminal, and the first third node, respectively. It is used to control the first third node to be electrically connected to the second clock signal terminal under the control of the potential of the first eighth node, and to control the potential of the first third node according to the potential of the first eighth node.

[0068] The first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node, and the first voltage terminal, respectively. It is used to control the connection between the first third node and the first first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node.

[0069] Optionally, the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit.

[0070] The first sixth node control circuit is electrically connected to the second voltage terminal, the first ninth node, the first sixth node, and the first fourth node, respectively, and is used to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the first sixth node according to the potential of the first fourth node.

[0071] The first fifth node control circuit is electrically connected to the N-1 level drive signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, respectively. It is used to control the connection between the first fifth node and the N-1 level drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first fifth node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0072] The first ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal and the first ninth node respectively, and is used to control the connection between the first ninth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal.

[0073] The first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively. It is used to control the connection between the first fourth node and the first voltage terminal under the control of the potential of the first seventh node, and to control the connection between the first fourth node and the second clock signal terminal under the control of the potential of the first sixth node.

[0074] The first second control circuit is electrically connected to the second voltage terminal, the first fifth node, and the first second control node, respectively, and is used to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal.

[0075] Optionally, the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor.

[0076] The gate of the first twelfth transistor is electrically connected to the first clock signal terminal, the first terminal of the first twelfth transistor is electrically connected to the second voltage terminal, and the second terminal of the first twelfth transistor is electrically connected to the first seventh node.

[0077] The gate of the first thirteenth transistor is electrically connected to the first fifth node, the first terminal of the first thirteenth transistor is electrically connected to the first seventh node, and the second terminal of the first thirteenth transistor is electrically connected to the first clock signal terminal.

[0078] The gate of the first fourteenth transistor is electrically connected to the second voltage terminal, the first terminal of the first fourteenth transistor is electrically connected to the first seventh node, and the second terminal of the first fourteenth transistor is electrically connected to the first eighth node.

[0079] The gate of the first fifteenth transistor is electrically connected to the first eighth node, the first terminal of the first fifteenth transistor is electrically connected to the second clock signal terminal, and the second terminal of the first fifteenth transistor is electrically connected to the first third node;

[0080] The first terminal of the first fourth capacitor is electrically connected to the first eighth node, and the second terminal of the first fourth capacitor is electrically connected to the first third node.

[0081] The gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the first sixteenth transistor is electrically connected to the first third node, and the second terminal of the first sixteenth transistor is electrically connected to the first first control node.

[0082] The gate of the first seventeenth transistor is electrically connected to the first fifth node, the first terminal of the first seventeenth transistor is electrically connected to the first first control node, and the second terminal of the first seventeenth transistor is electrically connected to the first voltage terminal.

[0083] Optionally, the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor.

[0084] The gate of the first eighteenth transistor is electrically connected to the second voltage terminal, the first terminal of the first eighteenth transistor is electrically connected to the first ninth node, and the second terminal of the first eighteenth transistor is electrically connected to the first sixth node.

[0085] The first terminal of the first fifth capacitor is electrically connected to the first fourth node, and the second terminal of the first fifth capacitor is electrically connected to the first sixth node;

[0086] The gate of the first nineteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the first nineteenth transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the first nineteenth transistor is electrically connected to the first fifth node.

[0087] The gate of the first twentieth transistor is electrically connected to the initial control terminal, the first terminal of the first twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the first twentieth transistor is electrically connected to the first fifth node.

[0088] The gate of the first twenty-first transistor is electrically connected to the first clock signal terminal, the first terminal of the first twenty-first transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the first twenty-first transistor is electrically connected to the first ninth node.

[0089] The gate of the first twenty-second transistor is electrically connected to the first seventh node, the first terminal of the first twenty-second transistor is electrically connected to the first voltage terminal, and the second terminal of the first twenty-second transistor is electrically connected to the first fourth node.

[0090] The gate of the first twenty-third transistor is electrically connected to the first sixth node, the first terminal of the first twenty-third transistor is electrically connected to the first fourth node, and the second terminal of the first twenty-third transistor is electrically connected to the second clock signal terminal.

[0091] The gate of the first twenty-fourth transistor is electrically connected to the second voltage terminal, the first terminal of the first twenty-fourth transistor is electrically connected to the first ninth node, and the second terminal of the first twenty-fourth transistor is electrically connected to the first second control node.

[0092] Optionally, the first first drive output circuit includes a first twenty-fifth transistor and a first sixth capacitor, and the first second drive output circuit includes a first twenty-sixth transistor and a first seventh capacitor;

[0093] The gate of the first twenty-fifth transistor is electrically connected to the first first control node, the first terminal of the first twenty-fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the first twenty-fifth transistor is electrically connected to the Nth stage drive signal output terminal.

[0094] The first terminal of the first sixth capacitor is electrically connected to the first first control node, and the second terminal of the first sixth capacitor is electrically connected to the first voltage terminal.

[0095] The gate of the first twenty-sixth transistor is electrically connected to the first second control node, the first terminal of the first twenty-sixth transistor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the first twenty-sixth transistor is electrically connected to the second voltage terminal.

[0096] The first terminal of the first seventh capacitor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the first seventh capacitor is electrically connected to the second voltage terminal.

[0097] Optionally, the first output pull-down circuit includes a first twenty-seventh transistor;

[0098] The gate of the first twenty-seventh transistor is electrically connected to the first first control node, the first terminal of the first twenty-seventh transistor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the first twenty-seventh transistor is electrically connected to the second voltage terminal.

[0099] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving circuit, the driving method comprising:

[0100] The first drive signal generation circuit generates and outputs the Nth-level drive signal through the Nth-level drive signal output terminal under the control of the potential of the first first control node and the potential of the first second control node.

[0101] The first output control circuit controls the connection between the first first control node and the first second node under the control of the potential of the first first node;

[0102] Under the control of the gating control signal, the first gating circuit controls the gating input signal to be written into the first node;

[0103] The first energy storage circuit controls the potential of the first second node based on the potential of the first first node;

[0104] The first second energy storage circuit controls the potential of the first third control node according to the Nth stage drive output signal provided by the Nth stage output drive terminal;

[0105] Under the control of the potential of the first second node, the first output circuit controls the connection between the Nth stage output drive terminal and the first voltage terminal. Under the control of the potential of the first third control node, the first output circuit controls the connection between the Nth stage output drive terminal and the second voltage terminal.

[0106] The first third control node is a different node from the first second control node, and N is a positive integer.

[0107] In a third aspect, embodiments of this disclosure provide a driving module including multiple levels of the driving circuits described above;

[0108] The Nth stage drive circuit is electrically connected to the drive signal output terminals of the (N-1)th stage drive circuit; N is a positive integer.

[0109] In a fourth aspect, embodiments of this disclosure provide a display device including the driving module described above. Attached Figure Description

[0110] Figure 1 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0111] Figure 2 It is the circuit diagram of the relevant pixel circuit;

[0112] Figure 3 yes Figure 2 The timing diagram of the relevant pixel circuit is shown below;

[0113] Figure 4 It is the circuit diagram of the relevant pixel circuit;

[0114] Figure 5 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0115] Figure 6 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0116] Figure 7 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0117] Figure 8This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0118] Figure 9 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0119] Figure 10 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0120] Figure 11 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0121] Figure 12 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0122] Figure 13 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0123] Figure 14 This is a circuit diagram of at least one embodiment of the first gating circuit in the driving circuit described in the embodiments of this disclosure;

[0124] Figure 15 This is a circuit diagram of at least one embodiment of the first inverter;

[0125] Figure 16 This is a circuit diagram of at least one embodiment of the second inverter;

[0126] Figure 17A This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0127] Figure 17B This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0128] Figure 18A This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0129] Figure 18B This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0130] Figure 18C This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0131] Figure 18D This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0132] Figure 19AThis is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0133] Figure 19B This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0134] Figure 19C This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0135] Figure 19D This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0136] Figure 20A This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0137] Figure 20B This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0138] Figure 20C This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0139] Figure 20D This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0140] Figure 21A This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0141] Figure 21B This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0142] Figure 21C This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0143] Figure 21D This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0144] Figure 22A This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0145] Figure 22B This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0146] Figure 22C This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0147] Figure 22D This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0148] Figure 23 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0149] Figure 24A This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0150] Figure 24B This is a simulation timing diagram of at least one embodiment of the drive circuit shown in Figure 24;

[0151] Figure 25 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0152] Figure 26 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0153] Figure 27 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0154] Figure 28 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0155] Figure 29 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0156] Figure 30 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0157] Figure 31 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0158] Figure 32 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0159] Figure 33 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0160] Figure 34 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0161] Figure 35 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0162] Figure 36 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0163] Figure 37 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0164] Figure 38 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0165] Figure 39 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0166] Figure 40 yes Figure 39 The timing diagram of at least one embodiment of the driving circuit shown;

[0167] Figure 41 yes Figure 39 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0168] Figure 42 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0169] Figure 43 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0170] Figure 44 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0171] Figure 45 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0172] Figure 46 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0173] Figure 47 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0174] Figure 48 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0175] Figure 49 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0176] Figure 50 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0177] Figure 51 yes Figure 50 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0178] Figure 52 yes Figure 50 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0179] Figure 53 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0180] Figure 54 yes Figure 53Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0181] Figure 55 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0182] Figure 56 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0183] Figure 57 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0184] Figure 58 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0185] Figure 59 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0186] Figure 60 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0187] Figure 61 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0188] Figure 62 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0189] Figure 63 yes Figure 62 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0190] Figure 64 yes Figure 62 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0191] Figure 65 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0192] Figure 66 yes Figure 65 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0193] Figure 67 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0194] Figure 68 yes Figure 67 The timing diagram of at least one embodiment of the driving circuit shown;

[0195] Figure 69 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0196] Figure 70 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0197] Figure 71 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0198] Figure 72 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0199] Figure 73 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0200] Figure 74 yes Figure 73 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0201] Figure 75 yes Figure 73 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0202] Figure 76 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0203] Figure 77 yes Figure 76 Simulation timing diagram of at least one embodiment of the driving circuit shown;

[0204] Figure 78 This is a structural diagram of the drive module described in at least one embodiment of the present disclosure;

[0205] Figure 79 yes Figure 78 Timing diagram of at least one embodiment of the driving module shown;

[0206] Figure 80 This is a waveform diagram of the first clock signal provided by GCK and the second clock signal provided by GCB. Detailed Implementation

[0207] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0208] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0209] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0210] like Figure 1 As shown, the driving circuit described in this embodiment includes a first driving signal generation circuit 110, a first gating circuit 111, a first output control circuit 112, a first output circuit 113, a first first energy storage circuit 114, and a first second energy storage circuit 115; N is a positive integer;

[0211] The first drive signal generation circuit 110 is electrically connected to the first first control node NC1-1, the first second control node NC1-2 and the Nth stage drive signal output terminal NS(N), respectively, and is used to generate and output the Nth stage drive signal through the Nth stage drive signal output terminal NS(N) under the control of the potential of the first first control node NC1-1 and the potential of the first second control node NC1-2.

[0212] The first gating circuit 111 is electrically connected to the first node N1-1, the gating input terminal VCT, and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1-1 under the control of the gating control signal provided by the gating control terminal CX.

[0213] The first output control circuit 112 is electrically connected to the first first node N1-1, the first first control node NC1-1 and the first second node N1-2 respectively, and is used to control the connection between the first first control node NC1-1 and the first second node N1-2 under the control of the potential of the first first node N1-1;

[0214] The first energy storage circuit 114 is electrically connected to the first first node N1-1 and the first second node N1-2 respectively, and is used to control the potential of the first second node N1-2 according to the potential of the first first node N1-1;

[0215] The first second energy storage circuit 115 is electrically connected to the first third control node NC1-3 and the Nth stage output drive terminal NO(N), respectively, and is used to control the potential of the first third control node NC1-3 according to the Nth stage drive output signal provided by the Nth stage output drive terminal NO(N);

[0216] The first output circuit 113 is electrically connected to the first second node N1-2, the first third control node NC1-3, the first voltage terminal V1, the second voltage terminal V2, and the Nth stage output drive terminal NO(N), respectively. It is used to control the Nth stage output drive terminal NO(N) to be connected with the first voltage terminal V1 under the control of the potential of the first second node N1-2, and to control the Nth stage output drive terminal NO(N) to be connected with the second voltage terminal V2 under the control of the potential of the first third control node NC1-3.

[0217] The first third control node NC1-3 is a different node from the first second control node NC1-2.

[0218] This disclosure Figure 1 In the embodiment of the driving circuit shown, during operation, the first driving signal generation circuit 110, under the control of the potential of the first first control node NC1-1 and the potential of the first second control node NC1-2, generates and outputs the Nth stage driving signal through the Nth stage driving signal output terminal NS(N); the first gating circuit 111, under the control of the gating control signal provided by the gating control terminal CX, controls the gating input signal provided by the gating input terminal VCT to be written to the first first node N1-1; the first output control circuit 112, under the control of the potential of the first first node N1-1, controls the first first control node NC1-1 and the first second node N1-2 to... -2 are connected; the first first energy storage circuit 114 controls the potential of the first second node N1-2 according to the potential of the first first node N1-1; the first second energy storage circuit 115 controls the potential of the first third control node NC1-3 according to the Nth stage drive output signal provided by the Nth stage output drive terminal NO(N); the first output circuit 113 controls the Nth stage output drive terminal NO(N) to be connected with the first voltage terminal V1 under the control of the potential of the first second node N1-2, and controls the Nth stage output drive terminal NO(N) to be connected with the second voltage terminal V2 under the control of the potential of the first third control node NC1-3.

[0219] Optionally, the first voltage terminal can be a high voltage terminal, but is not limited thereto.

[0220] This disclosure Figure 1 The embodiment of the driving circuit shown can be the Nth stage driving circuit.

[0221] This disclosure Figure 1 The illustrated driving circuit embodiment, when in operation, within one frame time,

[0222] Before the Nth stage of driving signal provision, the first gating circuit 111, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT into the first first node N1-1;

[0223] When the strobe input signal is a high voltage signal, during the Nth stage of driving signal provision, the Nth stage driving signal output terminal NS(N) outputs a high voltage signal, the potential of the first node N1-1 is high voltage, the first output control circuit 112 controls the first control node NC1-1 to disconnect from the first second node N1-2 under the control of the potential of the first node N1-1, the first energy storage circuit 114 controls the potential of the first second node N1-2 to be high voltage according to the potential of the first node N1-1, and the first output circuit 113 controls the output drive terminal NO(N) to maintain a low voltage signal, which can control the corresponding row pixel circuit not to update the pixel voltage;

[0224] When the strobe input signal is a low voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal, the potential of the first first node N1-1 is low voltage, and the first output control circuit 112 controls the connection between the first first control node NC1-1 and the first second node N1-2 under the control of the potential of the first first node N1-1, so that the potential of the first second node N1-2 is low voltage. The first output circuit 113 controls the connection between the output drive terminal NO(N) and the first voltage terminal V1 under the control of the potential of the first second node N1-2, so that NO(N) outputs a high voltage signal, which can control the corresponding row pixel circuit to update the pixel voltage.

[0225] This disclosure Figure 1 When the driving circuit shown in the embodiment is in operation, when the potential of the Nth stage driving output signal provided by NO(N) decreases from a high voltage to a low voltage, the potential of the first third control node NC1-3 can be pulled down, so that the transistors whose gates are electrically connected to the first third control node NC1-3 included in the first output circuit 113 can be turned on better, and the potential of the Nth stage driving output signal is maintained at a low voltage.

[0226] This disclosure embodiment can update a portion of the display screen by controlling the gating input signal provided by the gating input terminal VCT, thereby reducing power consumption, or achieve ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and notebook computers by updating the display screen partially.

[0227] like Figure 2 As shown, the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light-emitting diode O1.

[0228] The gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3.

[0229] The gate of M2 is electrically connected to the first scan terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0230] The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3.

[0231] The gate of M5 is electrically connected to the light-emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3.

[0232] The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS.

[0233] The gate of M7 is electrically connected to the second scan terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0234] In specific implementation, the first reset terminal NR(N) can be the first scan terminal NG(N) of the N-1th stage, but is not limited thereto.

[0235] exist Figure 2 In the related pixel circuit shown, M1 and M2 are n-type transistors, M3, M4, M5, M6 and M7 are all p-type transistors, M1 and M2 are IGZO TFTs with low leakage current, and M3, M4, M5, M6 and M7 are all LTPS TFTs.

[0236] exist Figure 2In the related pixel circuit shown, M1 and M2 are IGZO TFTs. When using low-frequency displays, IGZO TFTs can ensure that Cst can maintain the gate voltage of M3 for a longer period of time.

[0237] exist Figure 2 In the related pixel circuit shown, the second scan terminal PG(N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line to the source of the driving transistor. The first scan terminal NG(N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor), and writing the data voltage to the gate of the driving transistor.

[0238] In specific implementation, the first scan signal provided by the first scanning terminal NG(N) and the second scan signal provided by the second scanning terminal PG(N) can be inversely related, but are not limited thereto.

[0239] The driving circuit described in at least one embodiment of this disclosure can provide a first scanning signal to the first scanning terminal NG(N) through the output driving terminal NO(N), but is not limited thereto.

[0240] like Figure 3 As shown, Figure 2 When the related pixel circuit shown is working, the display cycle may include a first display control stage t1, a second display control stage t2, and a third display control stage t3 set sequentially.

[0241] In the first display control phase t1, E(N) outputs a high voltage signal, NR(N) provides a high voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled low to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit.

[0242] In the second display control phase t2, E(N) outputs a high voltage signal, NR(N) provides a low voltage signal, PG(N) provides a low voltage signal, and NG(N) provides a high voltage signal. M5 and M6 are turned off, M1 is turned off, M2 is turned on, and M4 is turned on. M2 and M3 form a diode structure, charging Cst through the data voltage Vdata provided by data line D1 until M3 is turned off. At this time, the gate voltage of M3 is Vdata + Vth, where Vth is the threshold voltage of M3. M7 is turned on to reset the anode voltage of O1.

[0243] In the third display control stage t3, E(N) outputs a low voltage signal, NR(N) provides a low voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned on, and M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.

[0244] As can be seen from the above-mentioned pixel circuit operation process, NG(N) can control whether the data voltage Vdata (which can be the pixel voltage) is written into the gate of M3 during the second display control stage.

[0245] Figure 4 This is the circuit diagram of the relevant pixel circuit.

[0246] like Figure 4 As shown, the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light-emitting diode O1.

[0247] The gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3.

[0248] The gate of M2 is electrically connected to the first scan terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0249] The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3.

[0250] The gate of M5 is electrically connected to the light-emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3.

[0251] The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS.

[0252] The gate of M7 is electrically connected to the fourth reset terminal RST2, the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0253] Figure 4 When the related pixel circuit shown is working, NG(N) can control whether the data voltage Vdata on the data line D1 is written to the gate of the driving transistor M3.

[0254] In practical implementation, the first scan signal provided by NG(N) can be used to control whether the first second transistor is turned on or off, thereby controlling whether the data voltage on the data line is written to the gate of the driving transistor, and thus controlling whether the brightness of the current row of pixel circuits is updated. When NG(N) outputs a high voltage signal, the first second transistor is turned on, and the brightness of the current row of pixel circuits can be updated. When NG(N) outputs a low voltage signal, the first second transistor is always turned off, and the change in data voltage on the data line is not written to the gate of the driving transistor, so the brightness of the organic light-emitting diode does not change, that is, the display brightness of the current row of pixel circuits remains unchanged in the current frame. In summary, the pixel brightness can be refreshed by controlling the turning on or off of the N-type transistor. Therefore, when it is desired that some pixels are not refreshed, the N-type transistor should be turned off.

[0255] In at least one embodiment of this disclosure, the first gating circuit is used to control the gating input signal provided by the gating input terminal to be written into the first first node when the potential of the first third node in the N-1th stage is the second voltage and the potential of the Nth stage driving signal is the second voltage.

[0256] Optionally, the second voltage can be a low voltage, but is not limited thereto.

[0257] Optionally, the first gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0258] like Figure 5 As shown, the first gating circuit may include a first transistor T1-1;

[0259] The gate of the first transistor T1-1 is electrically connected to the gating control terminal S0, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the gating input terminal VCT.

[0260] T1-1 is a p-type transistor.

[0261] like Figure 6 As shown, the first gating circuit may include a first transistor T1-1;

[0262] The gate of the first transistor T1-1 is electrically connected to the gating control terminal S0, the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the gating input terminal VCT.

[0263] T1-1 is an n-type transistor.

[0264] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the first gating circuit includes a first first transistor and a first second transistor;

[0265] The gate of the first transistor is electrically connected to the first gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the first second transistor.

[0266] The gate of the first second transistor is electrically connected to the second gating control terminal, and the second terminal of the first second transistor is electrically connected to the gating input terminal.

[0267] The first gating control terminal is the Nth stage drive signal output terminal, and the second gating control terminal is the first third node of the (N-1)th stage. Both the first first transistor and the first second transistor are p-type transistors; or...

[0268] The first gating control terminal is the first third node of the (N-1)th stage, the second gating control terminal is the drive signal output terminal of the Nth stage, and both the first first transistor and the first second transistor are p-type transistors; or...

[0269] The first gating control terminal is the output terminal of the (N-1)th stage drive signal, the second gating control terminal is the output terminal of the Nth stage drive signal, the first transistor is an n-type transistor, and the first transistor is a p-type transistor; or...

[0270] The first gating control terminal is the output terminal of the Nth stage drive signal, the second gating control terminal is the output terminal of the (N-1)th stage drive signal, the first transistor is a p-type transistor, and the first transistor is an n-type transistor; or...

[0271] The first gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal, and the second gating control terminal is the output terminal of the Nth stage drive signal. Both the first transistor and the first second transistor are p-type transistors; or...

[0272] The first gating control terminal is the output terminal of the Nth stage drive signal, and the second gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal; both the first first transistor and the first second transistor are p-type transistors; or,

[0273] The first gating control terminal is the (N-1)th stage drive signal terminal, and the second gating control terminal is connected to the inverted signal of the Nth stage drive signal. Both the first transistor and the first second transistor are n-type transistors; or...

[0274] The first gating control terminal is connected to the inverted signal of the Nth stage drive signal, the second gating control terminal is the N-1th stage drive signal terminal, and the first first transistor and the first second transistor are both n-type transistors.

[0275] like Figure 7 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0276] The gate of the first transistor T1-1 is electrically connected to the (N-1)th stage drive signal output terminal NS(N-1), the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2.

[0277] The gate of the first second transistor T1-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0278] T1-1 is an n-type transistor, and T1-2 is a p-type transistor.

[0279] like Figure 8 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0280] The gate of the first transistor T1-1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the source of the first transistor T1-2.

[0281] The gate of the first second transistor T1-2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0282] T1-1 is a p-type transistor, and T1-2 is an n-type transistor.

[0283] like Figure 9 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0284] The gate of the first transistor T1-1 is electrically connected to the first third node N1-3 (N-1) of the (N-1)th stage, the drain of the first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2.

[0285] The gate of the first second transistor T1-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0286] T1-1 is a p-type transistor, and T1-2 is a p-type transistor.

[0287] In at least one embodiment of this disclosure, the first third node N1-3(N-1) of the N-1th stage can be the first third node in the N-1th stage driving circuit.

[0288] like Figure 10 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0289] The gate of the first transistor T1-1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2.

[0290] The gate of the first second transistor T1-2 is electrically connected to the first third node N1-3 (N-1) of the N-1th stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0291] T1-1 is a p-type transistor, and T1-2 is a p-type transistor.

[0292] like Figure 11 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0293] The gate of the first transistor T1-1 is electrically connected to the first inverting drive signal terminal NGI1, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2; the first inverting drive signal provided by the first inverting drive signal terminal NGI1 is inverted with the N-1th stage drive signal provided by the (N-1)th stage drive signal output terminal NS(N-1);

[0294] The gate of the first second transistor T1-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0295] T1-1 is a p-type transistor, and T1-2 is a p-type transistor.

[0296] like Figure 12 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0297] The gate of the first transistor T1-1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2.

[0298] The gate of the first second transistor T1-2 is electrically connected to the first inverting drive signal terminal NGI1, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; the first inverting drive signal provided by the first inverting drive signal terminal NGI1 is inverted with the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1);

[0299] T1-1 is a p-type transistor, and T1-2 is a p-type transistor.

[0300] like Figure 13 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0301] The gate of the first transistor T1-1 is electrically connected to the (N-1)th stage drive signal output terminal NS(N-1), the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the source of the first transistor T1-2.

[0302] The gate of the first second transistor T1-2 is electrically connected to the second inverting drive signal terminal NGI2, and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; the second inverting drive signal provided by the second inverting drive signal terminal NGI2 is inverted with the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N);

[0303] T1-1 is an n-type transistor, and T1-2 is an n-type transistor.

[0304] like Figure 14 As shown, the first gating circuit may include a first transistor T1-1 and a first transistor T1-2;

[0305] The gate of the first transistor T1-1 is electrically connected to the second inverting drive signal terminal NGI2, the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the source of the first second transistor T1-2; the second inverting drive signal provided by the second inverting drive signal terminal NGI2 is inverted with the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N);

[0306] The gate of the first second transistor T1-2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0307] T1-1 is an n-type transistor, and T1-2 is an n-type transistor.

[0308] like Figure 15 As shown, the N-1 stage drive signal provided by the N-1 stage drive signal output terminal NS(N-1) can be inverted by the first inverter to obtain the first inverted drive signal provided by the first inverted drive signal terminal NGI1.

[0309] The first inverter includes a first inverting control transistor T01 and a second inverting control transistor T02;

[0310] T01 is a p-type transistor, and T02 is an n-type transistor.

[0311] like Figure 16 As shown, the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) can be inverted by the second inverter to obtain the second inverted drive signal provided by the second inverted drive signal terminal NGI2;

[0312] The second inverter includes a third inverting control transistor T03 and a fourth inverting control transistor T04;

[0313] T03 is a p-type transistor, and T04 is an n-type transistor.

[0314] In at least one embodiment of this disclosure, the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor;

[0315] The first terminal of the first capacitor is electrically connected to the first first node, and the second terminal of the first capacitor is electrically connected to the first second node;

[0316] The first terminal of the first second capacitor is electrically connected to the first third control node, and the second terminal of the first second capacitor is electrically connected to the Nth stage output drive terminal.

[0317] Optionally, the first output control circuit includes a first third transistor;

[0318] The gate of the first third transistor is electrically connected to the first first node, the first electrode of the first third transistor is electrically connected to the first first control node, and the second electrode of the first third transistor is electrically connected to the first second node.

[0319] The driving circuit described in at least one embodiment of this disclosure may further include a first second node control circuit;

[0320] The first second node control circuit is electrically connected to the first third control node, the first second node, and the first voltage terminal, respectively, and is used to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node.

[0321] In a specific implementation, the driving circuit may further include a first second node control circuit;

[0322] The first second node control circuit controls the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node.

[0323] like Figure 17A As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit further includes a first second node control circuit 120;

[0324] The first second node control circuit 120 is electrically connected to the first third control node NC1-3, the first second node N1-2 and the first voltage terminal V1, respectively, and is used to control the connection between the first second node N1-2 and the first voltage terminal V1 under the control of the potential of the first third control node NC1-3.

[0325] Figure 17A In at least one embodiment of the driving circuit shown, when the potential of the first third control node NC1-3 is an effective voltage, the potential of the first second node N1-2 can be a first voltage.

[0326] Optionally, the first second node control circuit includes a first fourth transistor;

[0327] The gate of the first fourth transistor is electrically connected to the first third control node, the first terminal of the first fourth transistor is electrically connected to the first second node, and the second terminal of the first fourth transistor is electrically connected to the first voltage terminal.

[0328] The driving circuit described in at least one embodiment of this disclosure may further include a first second node control circuit;

[0329] The first second node control circuit is electrically connected to the first third control node, the Nth stage output drive terminal, the first second node, and the first voltage terminal, respectively, and is used to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage drive output signal provided by the Nth stage output drive terminal.

[0330] In a specific implementation, the driving circuit may further include a first second node control circuit;

[0331] The first second node control circuit controls the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage drive output signal provided by the Nth stage output drive terminal.

[0332] like Figure 17B As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit further includes a first second node control circuit 120;

[0333] The first second node control circuit 120 is electrically connected to the first third control node NC1-3, the Nth stage output drive terminal NO(N), the first second node N1-2, and the first voltage terminal V1, respectively. It is used to control the connection between the first second node N1-2 and the first voltage terminal V1 under the control of the potential of the first third control node NC1-3 and the Nth stage drive output signal provided by the Nth stage output drive terminal NO(N).

[0334] Figure 17B In at least one embodiment of the driving circuit shown, when the potential of the first third control node NC1-3 is an effective voltage and the potential of the Nth stage drive output signal is an effective voltage, the potential of the first second node N1-2 can be a first voltage.

[0335] Optionally, the first second node control circuit includes a first fourth transistor and a first control transistor;

[0336] The gate of the first fourth transistor is electrically connected to the first third control node, the first terminal of the first fourth transistor is electrically connected to the second terminal of the first control transistor, and the second terminal of the first fourth transistor is electrically connected to the first voltage terminal.

[0337] The gate of the first control transistor is electrically connected to the Nth stage output drive terminal, and the first electrode of the first control transistor is electrically connected to the first second node.

[0338] Optionally, the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor;

[0339] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the first fifth transistor is electrically connected to the Nth stage output drive terminal.

[0340] The gate of the first sixth transistor is electrically connected to the first third control node, the first terminal of the first sixth transistor is electrically connected to the Nth stage output drive terminal, and the second terminal of the first sixth transistor is electrically connected to the second voltage terminal.

[0341] The first terminal of the first third capacitor is electrically connected to the first second node, and the second terminal of the first third capacitor is electrically connected to the first voltage terminal.

[0342] The driving circuit described in at least one embodiment of this disclosure further includes a first initialization circuit;

[0343] The first initialization circuit is electrically connected to the initial control terminal, the second voltage terminal, and the first first node, respectively, and is used to control the connection between the first first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0344] In a specific implementation, the driving circuit may further include a first initialization circuit. When the display device is powered on, the first initialization circuit controls the connection between the first node and the second voltage terminal under the control of the initial control signal, so as to control the potential of the first node to be the second voltage. The first output control circuit controls the connection between the first control node and the first second node under the control of the potential of the first node.

[0345] The driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit;

[0346] The first node control circuit is electrically connected to the first fourth node, the second voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the first fourth node.

[0347] In a specific implementation, the driving circuit may further include a first first node control circuit. Under the control of the potential of the first fourth node, the first first node control circuit controls the connection between the first first node and the second voltage terminal. After the Nth stage of driving signal provision, when the potential of the first fourth node is an effective voltage, the first first node control circuit controls the connection between the first first node and the second voltage terminal so that the potential of the first first node is the second voltage. Under the control of the potential of the first first node, the first output control circuit controls the connection between the first first control node and the first second node.

[0348] In at least one embodiment of this disclosure, when the transistor included in the first node control circuit is a p-type transistor, the effective voltage can be a low voltage; when the transistor included in the first node control circuit is an n-type transistor, the effective voltage can be a high voltage.

[0349] like Figure 18A As shown, in Figure 17A Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a first first node control circuit 122;

[0350] The first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the potential of the first fourth node N1-4.

[0351] like Figure 18B As shown, in Figure 17B Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a first first node control circuit 122;

[0352] The first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the potential of the first fourth node N1-4.

[0353] like Figure 18C As shown, in Figure 17ABased on at least one embodiment of the driving circuit shown, the driving circuit may further include a first initialization circuit 121 and a first node control circuit 122;

[0354] The first initialization circuit 121 is electrically connected to the initial control terminal NCX, the first first node N1-1 and the second voltage terminal V2 respectively, and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX.

[0355] The first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the potential of the first fourth node N1-4.

[0356] like Figure 18D As shown, in Figure 17B Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a first initialization circuit 121 and a first node control circuit 122;

[0357] The first initialization circuit 121 is electrically connected to the initial control terminal NCX, the first first node N1-1 and the second voltage terminal V2 respectively, and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX.

[0358] The first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the potential of the first fourth node N1-4.

[0359] Optionally, the first initialization circuit includes a first seventh transistor;

[0360] The gate of the first seventh transistor is electrically connected to the initial control terminal, the first terminal of the first seventh transistor is electrically connected to the first first node, and the second terminal of the first seventh transistor is electrically connected to the second voltage terminal.

[0361] Optionally, the first node control circuit includes a first eighth transistor;

[0362] The gate of the first eighth transistor is electrically connected to the first fourth node, the first terminal of the first eighth transistor is electrically connected to the first first node, and the second terminal of the first eighth transistor is electrically connected to the second voltage terminal.

[0363] The driving circuit described in at least one embodiment of this disclosure further includes a first third control node control circuit;

[0364] The first third control node control circuit is electrically connected to the first first node, the first fifth node, the first second control node, the first third control node, and the first sixth node, respectively. It is used to control the connection between the first fifth node and the first third control node under the control of the potential of the first first node, control the connection between the first second control node and the first sixth node under the control of the potential of the first sixth node, and control the connection between the first sixth node and the first third control node.

[0365] In a specific implementation, the driving circuit may include a first third control node control circuit, which controls the potential of the first third control node under the control of the potential of the first first node and the potential of the first sixth node.

[0366] like Figure 19A As shown, in Figure 18A Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first third control node control circuit 130;

[0367] The first third control node control circuit 130 is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively. It is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, control the connection between the first second control node NC1-2 and the first sixth node N1-6 under the control of the potential of the first sixth node N1-6, and control the connection between the first sixth node N1-6 and the first third control node NC1-3.

[0368] like Figure 19B As shown, in Figure 18B Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first third control node control circuit 130;

[0369] The first third control node control circuit 130 is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively. It is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, control the connection between the first second control node NC1-2 and the first sixth node N1-6 under the control of the potential of the first sixth node N1-6, and control the connection between the first sixth node N1-6 and the first third control node NC1-3.

[0370] like Figure 19C As shown, in Figure 18C Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first third control node control circuit 130;

[0371] The first third control node control circuit 130 is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively. It is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, control the connection between the first second control node NC1-2 and the first sixth node N1-6 under the control of the potential of the first sixth node N1-6, and control the connection between the first sixth node N1-6 and the first third control node NC1-3.

[0372] like Figure 19D As shown, in Figure 18D Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first third control node control circuit 130;

[0373] The first third control node control circuit 130 is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively. It is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, control the connection between the first second control node NC1-2 and the first sixth node N1-6 under the control of the potential of the first sixth node N1-6, and control the connection between the first sixth node N1-6 and the first third control node NC1-3.

[0374] Optionally, the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor;

[0375] The gate of the first ninth transistor is electrically connected to the first first node, the first electrode of the first ninth transistor is electrically connected to the first fifth node, and the second electrode of the first ninth transistor is electrically connected to the first third control node.

[0376] The gate and the second terminal of the first tenth transistor are both electrically connected to the first sixth node, and the first terminal of the first tenth transistor is electrically connected to the first second control node;

[0377] The gate of the first eleventh transistor and the first terminal of the first eleventh transistor are both electrically connected to the first sixth node, and the second terminal of the first eleventh transistor is electrically connected to the first third control node.

[0378] In at least one embodiment of this disclosure, the first drive signal generation circuit includes a first first drive output circuit, a first second drive output circuit, a first first control node control circuit, and a first second control node control circuit.

[0379] The first control node control circuit is used to control the potential of the first control node;

[0380] The first second control node control circuit is used to control the potential of the second control node;

[0381] The first first drive output circuit is electrically connected to the first first control node, the first voltage terminal and the Nth stage drive signal output terminal respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the potential of the first first control node;

[0382] The first second drive output circuit is electrically connected to the first second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the first second control node.

[0383] like Figure 20A As shown, in Figure 19A Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134.

[0384] The first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1.

[0385] The first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2.

[0386] The first first drive output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the first first control node NC1-1.

[0387] The first second drive output circuit 134 is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the first second control node NC1-2.

[0388] like Figure 20B As shown, in Figure 19B Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134.

[0389] The first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1.

[0390] The first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2.

[0391] The first first drive output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the first first control node NC1-1.

[0392] The first second drive output circuit 134 is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the first second control node NC1-2.

[0393] like Figure 20C As shown, in Figure 19C Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134.

[0394] The first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1.

[0395] The first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2.

[0396] The first first drive output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the first first control node NC1-1.

[0397] The first second drive output circuit 134 is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the first second control node NC1-2.

[0398] like Figure 20D As shown, in Figure 19D Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134.

[0399] The first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1.

[0400] The first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2.

[0401] The first first drive output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the first first control node NC1-1.

[0402] The first second drive output circuit 134 is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the first second control node NC1-2.

[0403] In at least one embodiment of this disclosure, the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit.

[0404] The first seventh node control circuit is electrically connected to the first seventh node, the second voltage terminal, the first clock signal terminal, and the first fifth node, respectively. It is used to control the connection between the first seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of the potential of the first fifth node.

[0405] The first eighth node control circuit is electrically connected to the second voltage terminal, the first seventh node, and the first eighth node, respectively, and is used to control the connection between the first seventh node and the first eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0406] The first third node control circuit is electrically connected to the first eighth node, the second clock signal terminal, and the first third node, respectively. It is used to control the first third node to be electrically connected to the second clock signal terminal under the control of the potential of the first eighth node, and to control the potential of the first third node according to the potential of the first eighth node.

[0407] The first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node, and the first voltage terminal, respectively. It is used to control the connection between the first third node and the first first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node.

[0408] In a specific implementation, the first control node control circuit may include a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first control circuit; the first seventh node control circuit controls the potential of the first seventh node under the control of the first clock signal and the potential of the first fifth node; the first eighth node control circuit controls the connection between the first seventh node and the first eighth node under the control of the second voltage signal; the first third node control circuit controls the electrical connection between the first third node and the second clock signal terminal under the control of the potential of the first eighth node, and controls the potential of the first third node according to the potential of the first eighth node; the first first control circuit controls the connection between the first third node and the first first control node under the control of the second clock signal, and controls the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node.

[0409] In at least one embodiment of this disclosure, the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit.

[0410] The first sixth node control circuit is electrically connected to the second voltage terminal, the first ninth node, the first sixth node, and the first fourth node, respectively, and is used to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the first sixth node according to the potential of the first fourth node.

[0411] The first fifth node control circuit is electrically connected to the N-1 level drive signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, respectively. It is used to control the connection between the first fifth node and the N-1 level drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first fifth node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0412] The first ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal and the first ninth node respectively, and is used to control the connection between the first ninth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal.

[0413] The first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively. It is used to control the connection between the first fourth node and the first voltage terminal under the control of the potential of the first seventh node, and to control the connection between the first fourth node and the second clock signal terminal under the control of the potential of the first sixth node.

[0414] The first second control circuit is electrically connected to the second voltage terminal, the first fifth node, and the first second control node, respectively, and is used to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal.

[0415] In specific implementation, the first second control node control circuit may include a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit; the first fourth node control circuit controls the potential of the first fourth node under the control of the potential of the first seventh node and the potential of the first sixth node; the first sixth node control circuit controls the connection between the first ninth node and the first sixth node under the control of the second voltage signal, and controls the potential of the first sixth node according to the potential of the first fourth node; the first fifth node control circuit controls the first... The first fifth node is connected to the output terminal of the (N-1)th stage drive signal. Under the control of the initial control signal, the first fifth node is connected to the first voltage terminal. The first ninth node control circuit, under the control of the first clock signal, controls the first ninth node to be connected to the output terminal of the (N-1)th stage drive signal. The first fourth node control circuit, under the control of the potential of the first seventh node, controls the first fourth node to be connected to the first voltage terminal, and under the control of the potential of the first sixth node, controls the first fourth node to be connected to the second clock signal terminal. The first second control circuit, under the control of the second voltage signal, controls the first fifth node to be connected to the first second control node.

[0416] like Figure 21A As shown, in Figure 20ABased on at least one embodiment of the driving circuit shown, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144.

[0417] The first seventh node control circuit 141 is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, respectively. It is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5.

[0418] The first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the seventh node N1-7 and the first eighth node N1-8 respectively, and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of the second voltage signal provided by the second voltage terminal V2.

[0419] The first third node control circuit 143 is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, respectively. It is used to control the first third node N1-3 to be electrically connected to the second clock signal terminal GCB under the control of the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8.

[0420] The first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, respectively. It is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5.

[0421] The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155.

[0422] The first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, the first ninth node N1-9, the first sixth node N1-6, and the first fourth node N1-4, respectively. It is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4.

[0423] The first fifth node control circuit 152 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX, and the first voltage terminal V1, respectively. It is used to control the connection between the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0424] The first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1) and the first ninth node N1-9 respectively, and is used to control the connection between the first ninth node N1-9 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK.

[0425] The first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, respectively. It is used to control the first fourth node N1-4 to be electrically connected to the first voltage terminal V1 under the control of the potential of the first seventh node N1-7, and to control the first fourth node N1-4 to be connected to the second clock signal terminal GCB under the control of the potential of the first sixth node N1-6.

[0426] The first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 and the first second control node NC1-2 respectively, and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0427] like Figure 21B As shown, in Figure 20BBased on at least one embodiment of the driving circuit shown, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144.

[0428] The first seventh node control circuit 141 is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, respectively. It is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5.

[0429] The first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 and the first eighth node N1-8 respectively, and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of the second voltage signal provided by the second voltage terminal V2.

[0430] The first third node control circuit 143 is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, respectively. It is used to control the first third node N1-3 to be electrically connected to the second clock signal terminal GCB under the control of the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8.

[0431] The first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, respectively. It is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5.

[0432] The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155.

[0433] The first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, the first ninth node N1-9, the first sixth node N1-6, and the first fourth node N1-4, respectively. It is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4.

[0434] The first fifth node control circuit 152 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX, and the first voltage terminal V1, respectively. It is used to control the connection between the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0435] The first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1) and the first ninth node N1-9 respectively, and is used to control the connection between the first ninth node N1-9 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK.

[0436] The first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, respectively. It is used to control the first fourth node N1-4 to be electrically connected to the first voltage terminal V1 under the control of the potential of the first seventh node N1-7, and to control the first fourth node N1-4 to be connected to the second clock signal terminal GCB under the control of the potential of the first sixth node N1-6.

[0437] The first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 and the first second control node NC1-2 respectively, and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0438] like Figure 21C As shown, in Figure 20CBased on at least one embodiment of the driving circuit shown, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144.

[0439] The first seventh node control circuit 141 is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, respectively. It is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5.

[0440] The first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 and the first eighth node N1-8 respectively, and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of the second voltage signal provided by the second voltage terminal V2.

[0441] The first third node control circuit 143 is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, respectively. It is used to control the first third node N1-3 to be electrically connected to the second clock signal terminal GCB under the control of the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8.

[0442] The first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, respectively. It is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5.

[0443] The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155.

[0444] The first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, the first ninth node N1-9, the first sixth node N1-6, and the first fourth node N1-4, respectively. It is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4.

[0445] The first fifth node control circuit 152 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX, and the first voltage terminal V1, respectively. It is used to control the connection between the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0446] The first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1) and the first ninth node N1-9 respectively, and is used to control the connection between the first ninth node N1-9 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK.

[0447] The first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, respectively. It is used to control the first fourth node N1-4 to be electrically connected to the first voltage terminal V1 under the control of the potential of the first seventh node N1-7, and to control the first fourth node N1-4 to be connected to the second clock signal terminal GCB under the control of the potential of the first sixth node N1-6.

[0448] The first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 and the first second control node NC1-2 respectively, and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0449] like Figure 21D As shown, in Figure 20DBased on at least one embodiment of the driving circuit shown, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144.

[0450] The first seventh node control circuit 141 is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, respectively. It is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5.

[0451] The first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 and the first eighth node N1-8 respectively, and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of the second voltage signal provided by the second voltage terminal V2.

[0452] The first third node control circuit 143 is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, respectively. It is used to control the first third node N1-3 to be electrically connected to the second clock signal terminal GCB under the control of the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8.

[0453] The first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, respectively. It is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5.

[0454] The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155.

[0455] The first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, the first ninth node N1-9, the first sixth node N1-6, and the first fourth node N1-4, respectively. It is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4.

[0456] The first fifth node control circuit 152 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N5, the initial control terminal NCX, and the first voltage terminal V1, respectively. It is used to control the connection between the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0457] The first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1) and the first ninth node N1-9 respectively, and is used to control the connection between the first ninth node N1-9 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK.

[0458] The first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, respectively. It is used to control the first fourth node N1-4 to be electrically connected to the first voltage terminal V1 under the control of the potential of the first seventh node N1-7, and to control the first fourth node N1-4 to be connected to the second clock signal terminal GCB under the control of the potential of the first sixth node N1-6.

[0459] The first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 and the first second control node NC1-2 respectively, and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0460] Optionally, the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor.

[0461] The gate of the first twelfth transistor is electrically connected to the first clock signal terminal, the first terminal of the first twelfth transistor is electrically connected to the second voltage terminal, and the second terminal of the first twelfth transistor is electrically connected to the first seventh node.

[0462] The gate of the first thirteenth transistor is electrically connected to the first fifth node, the first terminal of the first thirteenth transistor is electrically connected to the first seventh node, and the second terminal of the first thirteenth transistor is electrically connected to the first clock signal terminal.

[0463] The gate of the first fourteenth transistor is electrically connected to the second voltage terminal, the first terminal of the first fourteenth transistor is electrically connected to the first seventh node, and the second terminal of the first fourteenth transistor is electrically connected to the first eighth node.

[0464] The gate of the first fifteenth transistor is electrically connected to the first eighth node, the first terminal of the first fifteenth transistor is electrically connected to the second clock signal terminal, and the second terminal of the first fifteenth transistor is electrically connected to the first third node;

[0465] The first terminal of the first fourth capacitor is electrically connected to the first eighth node, and the second terminal of the first fourth capacitor is electrically connected to the first third node.

[0466] The gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the first sixteenth transistor is electrically connected to the first third node, and the second terminal of the first sixteenth transistor is electrically connected to the first first control node.

[0467] The gate of the first seventeenth transistor is electrically connected to the first fifth node, the first terminal of the first seventeenth transistor is electrically connected to the first first control node, and the second terminal of the first seventeenth transistor is electrically connected to the first voltage terminal.

[0468] Optionally, the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor.

[0469] The gate of the first eighteenth transistor is electrically connected to the second voltage terminal, the first terminal of the first eighteenth transistor is electrically connected to the first ninth node, and the second terminal of the first eighteenth transistor is electrically connected to the first sixth node.

[0470] The first terminal of the first fifth capacitor is electrically connected to the first fourth node, and the second terminal of the first fifth capacitor is electrically connected to the first sixth node;

[0471] The gate of the first nineteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the first nineteenth transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the first nineteenth transistor is electrically connected to the first fifth node.

[0472] The gate of the first twentieth transistor is electrically connected to the initial control terminal, the first terminal of the first twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the first twentieth transistor is electrically connected to the first fifth node.

[0473] The gate of the first twenty-first transistor is electrically connected to the first clock signal terminal, the first terminal of the first twenty-first transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the first twenty-first transistor is electrically connected to the first ninth node.

[0474] The gate of the first twenty-second transistor is electrically connected to the first seventh node, the first terminal of the first twenty-second transistor is electrically connected to the first voltage terminal, and the second terminal of the first twenty-second transistor is electrically connected to the first fourth node.

[0475] The gate of the first twenty-third transistor is electrically connected to the first sixth node, the first terminal of the first twenty-third transistor is electrically connected to the first fourth node, and the second terminal of the first twenty-third transistor is electrically connected to the second clock signal terminal.

[0476] The gate of the first twenty-fourth transistor is electrically connected to the second voltage terminal, the first terminal of the first twenty-fourth transistor is electrically connected to the first ninth node, and the second terminal of the first twenty-fourth transistor is electrically connected to the first second control node.

[0477] Optionally, the first first drive output circuit includes a first twenty-fifth transistor and a first sixth capacitor, and the first second drive output circuit includes a first twenty-sixth transistor and a first seventh capacitor;

[0478] The gate of the first twenty-fifth transistor is electrically connected to the first first control node, the first terminal of the first twenty-fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the first twenty-fifth transistor is electrically connected to the Nth stage drive signal output terminal.

[0479] The first terminal of the first sixth capacitor is electrically connected to the first first control node, and the second terminal of the first sixth capacitor is electrically connected to the first voltage terminal.

[0480] The gate of the first twenty-sixth transistor is electrically connected to the first second control node, the first terminal of the first twenty-sixth transistor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the first twenty-sixth transistor is electrically connected to the second voltage terminal.

[0481] The first terminal of the first seventh capacitor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the first seventh capacitor is electrically connected to the second voltage terminal.

[0482] The driving circuit described in at least one embodiment of this disclosure further includes a first output pull-down circuit;

[0483] The first output pull-down circuit is electrically connected to the first control node, the Nth stage drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the first control node.

[0484] In a specific implementation, the driving circuit may further include a first output pull-down circuit. Under the control of the potential of the first control node, the first output pull-down circuit can control the connection between the Nth stage driving signal output terminal and the second voltage terminal to enhance the second voltage signal output capability of the Nth stage driving signal output terminal.

[0485] like Figure 22A As shown, in Figure 21A Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a first output pull-down circuit 1220;

[0486] The first output pull-down circuit 1220 is electrically connected to the first first control node NC1-1, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the first first control node NC1-1.

[0487] like Figure 22B As shown, in Figure 21B Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a first output pull-down circuit 1220;

[0488] The first output pull-down circuit 1220 is electrically connected to the first first control node NC1-1, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS and the second voltage terminal V2 under the control of the potential of the first first control node NC1-1.

[0489] like Figure 22C As shown, in Figure 21C Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a first output pull-down circuit 1220;

[0490] The first output pull-down circuit 1220 is electrically connected to the first first control node NC1-1, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS and the second voltage terminal V2 under the control of the potential of the first first control node NC1-1.

[0491] like Figure 22D As shown, in Figure 21D Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a first output pull-down circuit 1220;

[0492] The first output pull-down circuit 1220 is electrically connected to the first first control node NC1-1, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS and the second voltage terminal V2 under the control of the potential of the first first control node NC1-1.

[0493] like Figure 23 As shown, in Figure 21A Based on at least one embodiment of the driving circuit shown,

[0494] The first gating circuit includes a first transistor T1-1 and a first transistor T1-2;

[0495] The gate of the first transistor T1-1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2.

[0496] The gate of the first second transistor T1-2 is electrically connected to the first third node N1-3 (N-1) of the (N-1)th stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT.

[0497] The first output control circuit includes a first third transistor T1-3;

[0498] The gate of the first third transistor T1-3 is electrically connected to the first first node N1-1, the source of the first third transistor T1-3 is electrically connected to the first first control node NC1-1, and the drain of the first third transistor T1-3 is electrically connected to the first second node N1-2.

[0499] The first energy storage circuit includes a first capacitor C1-1;

[0500] The first terminal of the first capacitor C1-1 is electrically connected to the first node N1-1, and the second terminal of the first capacitor C1-1 is electrically connected to the first node N1-2.

[0501] The first second energy storage circuit includes a first second capacitor C1-2;

[0502] The first terminal of the first second capacitor C1-2 is electrically connected to the first third control node NC1-3, and the second terminal of the first second capacitor C1-2 is electrically connected to the Nth stage output drive terminal NO(N).

[0503] The first second node control circuit includes a first fourth transistor T1-4;

[0504] The gate of the first fourth transistor T1-4 is electrically connected to the first third control node NC1-3, the source of the first fourth transistor T1-4 is electrically connected to the first second node N1-2, and the drain of the first fourth transistor T1-4 is electrically connected to the high voltage terminal VGH.

[0505] The first output circuit includes a first fifth transistor T1-5, a first sixth transistor, and a first third capacitor C1-3;

[0506] The gate of the first fifth transistor T1-5 is electrically connected to the first second node N1-2, the source of the first fifth transistor T1-5 is electrically connected to the high voltage terminal VGH, and the drain of the first fifth transistor T1-5 is electrically connected to the output drive terminal NO(N).

[0507] The gate of the first sixth transistor T1-6 is electrically connected to the first third control node NC1-3, the source of the first sixth transistor T1-6 is electrically connected to the output drive terminal NO(N), and the drain of the first sixth transistor T1-6 is electrically connected to the low voltage terminal VGL.

[0508] The first terminal of the first third capacitor C1-3 is electrically connected to the first second node N1-2, and the second terminal of the first third capacitor C1-3 is electrically connected to the high voltage terminal VGH.

[0509] The first node control circuit includes the first eighth transistor T1-8;

[0510] The gate of the first eighth transistor T1-8 is electrically connected to the first fourth node N1-4, the source of the first eighth transistor T1-8 is electrically connected to the first first node N1-1, and the drain of the first eighth transistor T8 is electrically connected to the low voltage terminal VGL.

[0511] The first third control node control circuit includes a first ninth transistor T1-9, a first tenth transistor T1-10, and an eleventh transistor T1-11;

[0512] The gate of the first ninth transistor T1-9 is electrically connected to the first first node N1-1, the drain of the first ninth transistor T1-9 is electrically connected to the first fifth node N1-5, and the source of the first ninth transistor T1-9 is electrically connected to the first third control node NC1-3.

[0513] The gate and source of the first tenth transistor T1-10 are both electrically connected to the first sixth node N1-6, and the drain of the first tenth transistor T1-10 is electrically connected to the first second control node NC1-2.

[0514] The gate and source of the first eleventh transistor T1-11 are both electrically connected to the first sixth node N1-6, and the drain of the first eleventh transistor T1-11 is electrically connected to the first third control node NC1-3.

[0515] The first seventh node control circuit includes the first twelfth transistor T1-12 and the first thirteenth transistor T1-13; the first eighth node control circuit includes the first fourteenth transistor T1-14; the first third node control circuit includes the first fifteenth transistor T1-15 and the first fourth capacitor C1-4; and the first first control circuit includes the first sixteenth transistor T1-16 and the first seventeenth transistor T1-17.

[0516] The gate of the first twelfth transistor T1-12 is electrically connected to the first clock signal terminal GCK, the source of the first twelfth transistor T1-12 is electrically connected to the low voltage terminal VGL, and the drain of the first twelfth transistor T1-12 is electrically connected to the first seventh node N1-7.

[0517] The gate of the first thirteenth transistor T1-13 is electrically connected to the first fifth node N1-5, the source of the first thirteenth transistor T1-13 is electrically connected to the first seventh node N1-7, and the drain of the first thirteenth transistor T1-13 is electrically connected to the first clock signal terminal GCK.

[0518] The gate of the first fourteenth transistor T1-14 is electrically connected to the low voltage terminal VGL, the source of the first fourteenth transistor T1-14 is electrically connected to the first seventh node N1-7, and the drain of the first fourteenth transistor T1-14 is electrically connected to the first eighth node N1-8.

[0519] The gate of the first fifteenth transistor T1-15 is electrically connected to the first eighth node N1-8, the source of the first fifteenth transistor T1-15 is electrically connected to the second clock signal terminal GCB, and the drain of the first fifteenth transistor T1-15 is electrically connected to the first third node N1-3.

[0520] The first terminal of the first fourth capacitor C1-4 is electrically connected to the first eighth node N1-8, and the second terminal of the first fourth capacitor C1-4 is electrically connected to the first third node N1-3.

[0521] The gate of the first sixteenth transistor T1-16 is electrically connected to the second clock signal terminal GCB, the source of the first sixteenth transistor T1-16 is electrically connected to the first third node N1-3, and the drain of the first sixteenth transistor T1-16 is electrically connected to the first first control node NC1-1.

[0522] The gate of the first seventeenth transistor T1-17 is electrically connected to the first fifth node N1-5, the source of the first seventeenth transistor T1-17 is electrically connected to the first first control node NC1-1, and the drain of the first seventeenth transistor T1-17 is electrically connected to the high voltage terminal VGH.

[0523] The first sixth node control circuit includes the first eighteenth transistor T1-18 and the first fifth capacitor C1-5; the first fifth node control circuit includes the first nineteenth transistor T1-19 and the first twentieth transistor T1-20; the first ninth node control circuit includes the first twenty-first transistor T1-21; the first fourth node control circuit includes the first twenty-second transistor T1-22 and the twenty-third transistor T1-23; and the first second control circuit includes the first twenty-fourth transistor T1-24.

[0524] The gate of the first eighteenth transistor T1-18 is electrically connected to the low voltage terminal VGL, the source of the first eighteenth transistor T1-18 is electrically connected to the first ninth node N1-9, and the drain of the first eighteenth transistor T1-18 is electrically connected to the first sixth node N1-6.

[0525] The first terminal of the first fifth capacitor C1-5 is electrically connected to the first fourth node N1-4, and the second terminal of the first fifth capacitor C1-5 is electrically connected to the first sixth node N1-6;

[0526] The gate of the first nineteenth transistor T1-19 is electrically connected to the first clock signal terminal GCK, the source of the first nineteenth transistor T1-19 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first nineteenth transistor T1-19 is electrically connected to the first fifth node N1-5.

[0527] The gate of the first twentieth transistor T1-20 is electrically connected to the initial control terminal NCX, the source of the first twentieth transistor T1-20 is electrically connected to the high voltage terminal VGH, and the drain of the first twentieth transistor T1-20 is electrically connected to the first fifth node N1-5.

[0528] The gate of the first twenty-first transistor T1-21 is electrically connected to the first clock signal terminal GCK, the source of the first twenty-first transistor T1-21 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first twenty-first transistor T1-21 is electrically connected to the first ninth node N1-9.

[0529] The gate of the first twenty-second transistor T1-22 is electrically connected to the first seventh node N1-7, the source of the first twenty-second transistor T1-22 is electrically connected to the high voltage terminal VGH, and the drain of the first twenty-second transistor T1-22 is electrically connected to the first fourth node N1-4.

[0530] The gate of the first twenty-third transistor T1-23 is electrically connected to the first sixth node N1-6, the source of the first twenty-third transistor T1-23 is electrically connected to the first fourth node N1-4, and the drain of the first twenty-third transistor T1-23 is electrically connected to the second clock signal terminal GCB.

[0531] The gate of the first twenty-fourth transistor T1-24 is electrically connected to the low voltage terminal VGL, the source of the first twenty-fourth transistor T1-24 is electrically connected to the first ninth node N1-9, and the drain of the first twenty-fourth transistor T1-24 is electrically connected to the first second control node NC1-2.

[0532] The first first drive output circuit includes a first twenty-fifth transistor T1-25 and a first sixth capacitor C1-6, and the first second drive output circuit includes a first twenty-sixth transistor T1-26 and a first seventh capacitor C1-7.

[0533] The gate of the first twenty-fifth transistor T1-25 is electrically connected to the first first control node NC1-1, the source of the first twenty-fifth transistor T1-25 is electrically connected to the high voltage terminal VGH, and the drain of the first twenty-fifth transistor T1-25 is electrically connected to the Nth stage drive signal output terminal NS(N).

[0534] The first terminal of the first sixth capacitor C1-6 is electrically connected to the first first control node NC1-1, and the second terminal of the first sixth capacitor C1-6 is electrically connected to the high voltage terminal VGH.

[0535] The gate of the first twenty-sixth transistor T1-26 is electrically connected to the first second control node NC1-2, the source of the first twenty-sixth transistor T1-26 is electrically connected to the Nth stage drive signal output terminal NS(N), and the drain of the first twenty-sixth transistor T1-26 is electrically connected to the low voltage terminal VGL.

[0536] The first terminal of the first seventh capacitor C1-7 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the first seventh capacitor C1-7 is electrically connected to the low voltage terminal VGL.

[0537] exist Figure 23 In at least one embodiment of the driving circuit shown, T1-3 is a dual-gate transistor, but is not limited thereto; in specific implementations, T1-3 may also be replaced with a single-gate transistor.

[0538] exist Figure 23 In the diagram, the nodes numbered N1-10 are the first tenth nodes.

[0539] exist Figure 23 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0540] exist Figure 23 In at least one embodiment of the driving circuit shown, the first voltage terminal is a high voltage terminal and the second voltage terminal is a low voltage terminal, but this is not a limitation.

[0541] exist Figure 23 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0542] exist Figure 23 In at least one embodiment of the driving circuit shown, N1-10 is the first tenth node.

[0543] In at least one embodiment of this disclosure, the structure of the first drive signal generation circuit is not limited to that shown in FIG22. The first drive signal generation circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0544] This disclosure Figure 23 In at least one embodiment of the driving circuit shown, when the potential of the Nth stage driving output signal provided by NO(N) decreases from a high voltage to a low voltage, the potential of the first third control node NC1-3 can be pulled down, so that T1-6 can be turned on better and the potential of the Nth stage driving output signal is maintained at a low voltage.

[0545] This disclosure Figure 23 At least one embodiment of the driving circuit shown, when in operation,

[0546] In the first stage, when NS(N-1) outputs a low voltage signal, GCK outputs a low voltage signal, and GCB outputs a high voltage signal, T1-19 and T1-21 are turned on to pull down the potentials of N1-5 and N1-9, T1-24 and T1-18 are turned on to pull down the potentials of NC1-2 and N1-6, and T1-26 is turned on; the potential of N1-6 is low, ensuring that T1-23 is turned on and the potential of N1-5 is low. When T1-13 is turned on, GCK provides a low voltage signal, turning on T1-12 and T1-14, setting the potentials of N1-7 and N1-8 to low voltage. When T1-15 is turned on, it controls the potential of N1-3 to high voltage, and the potential of N1-5 to low voltage. When T1-17 is turned on, the potential of NC1-1 is high voltage. When T1-10 and T1-11 are turned on, the potentials of NC1-2 and NC1-3 are both low voltage.

[0547] In the second stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output by GCK jumps from low to high, GCB outputs a low voltage signal, T1-19 and T1-21 are turned off, the potential of N1-5 is low, T1-12 is turned off, the potential of N1-5 remains low, T1-13 and T1-14 are turned on, the potentials of N1-7 and N1-8 are high, T1-15 is turned off, the potential of N1-3 remains high as in the previous stage, T1-16 is turned on to maintain the potential of NC1-1 high, and T1-25 is turned off; simultaneously, the potential of N1-6 is low, T1-23 is turned on, GCB writes a low voltage signal to N1-4, and through C1-4 pulls the potential of N1-6 down to an even lower voltage (5V lower than the low voltage signal value provided by GCB). ~10V), T1-10 and T1-11 are turned on, writing a low voltage signal to NC1-2 and N1-6 (the potential of NC1-2 is 3~8V lower than the low voltage signal provided by GCB), T1-26 is fully turned on, NS(N) outputs a low voltage signal; the potential of NC1-3 is low voltage, T1-6 is turned on, NO(N) outputs a low voltage signal; the potential of N1-4 is low voltage, T1-8 is turned on to pull the potential of N1-1 low; T1-9 is turned on to control the potential of NC1-3 to be low voltage, T1-6 is turned on, NO(N) outputs a low voltage signal; since the potential of N1-4 is low voltage, T1-8 is turned on to control the potential of N1-1 to be low voltage, T1-3 is turned on to control the connection between NC1-1 and N1-2, the potential of N1-2 is high voltage, and T1-5 is turned off;

[0548] In the third stage, NS(N-1) outputs a high voltage signal, GCK outputs a low voltage signal, GCB outputs a high voltage signal, T1-19 and T1-21 are turned on to pull the potentials of N1-5 and N1-9 high, T1-24 and T1-18 are turned on, the potentials of NC1-2 and N1-6 are high voltage, and T1-26 is turned off; the potential of N1-6 is high voltage, T1-23 is turned off, the potential of N1-5 is high voltage, T1-13 is turned off, GCK outputs a low voltage signal to turn on T1-12, T... Turning 1-14 on pulls the potentials of N1-7 and N1-8 low, turning on T1-15, GCB writes a high-voltage signal to N1-3, turning off T1-16, making the potential of N1-5 high, turning off T1-17, and making the potential of NC1-1 high; ensuring T1-25 is off; turning on T1-22, making the potential of N1-4 high, turning off T1-8; both the potentials of NC1-1 and NC1-2 are high, NS(N) continuously outputs a low-voltage signal; turning off T1-10 and T1-11.

[0549] In the third stage, N1-3 (N-1) and NS (N) output low voltage signals, T1-1 and T1-2 are turned on, and VCT is connected to N1-1;

[0550] In the third stage, when VCT provides a high voltage signal, the potential of N1-1 is high, T1-9 is off, T1-3 is off, and the potential of N1-2 remains high; when T1-9 is off, the connection between NC1-3 and N1-5 is broken, the potential of N1-6 is high, T1-10 and T1-11 are off, the potential of NC1-3 remains low, T1-6 is on, and NO(N) outputs a low voltage signal;

[0551] In the third stage, when VCT provides a low voltage signal, the potential of N1-1 is low, T1-9 is open, T1-3 is open, NC1-1 and N1-2 are connected, the potential of N1-2 is high, T1-5 is closed, T1-9 is open to control the connection between NC1-3 and N1-5, the potential of NC1-3 is high, and NO(N) continuously outputs a low voltage signal;

[0552] In the fourth stage, NS(N-1) outputs a high-voltage signal, the potential of the first clock signal output by GCK jumps from low voltage to high voltage, GCB outputs a low-voltage signal, T1-19 and T1-21 are turned off, the potential of N1-7 remains low voltage, T1-14 is turned on, the potential of N1-8 is low voltage, T1-15 and T1-16 are turned on to write the low-voltage signal to N1-3 and NC1-1, T1-25 is turned on, and NS(N) outputs a high-voltage signal; simultaneously, the potential of N1-6 is high voltage, T1-23 is turned off, the potential of N1-4 remains high voltage, the potential of N1-6 remains high voltage; T1-10 and T1-11 are turned off.

[0553] In the fourth stage, N1-3 (N-1) outputs a high voltage signal, T1-2 is turned off, and T1-8 is turned off;

[0554] When the potential of N1-1 is low, T1-9 is turned on to control the connection between N1-5 and NC1-3. When the potential of N1-5 is high, the potential of NC1-3 is high, and T1-6 is turned off. When T1-3 is turned on, it controls the connection between NC1-1 and N1-2. When the potential of N1-2 is low, T1-5 is turned on, T1-6 is turned off, and NO(N) outputs a high voltage signal.

[0555] When the potential of N1-1 is high, T1-9 is turned off to disconnect N1-5 and NC1-3, and the potential of NC1-3 remains high. The potential of NC1-3 remains low in the third stage, and T1-6 remains on. When T1-3 is turned off, it disconnects NC1-1 and N1-2, and the potential of N1-2 remains high. T1-5 is turned off, and NO(N) continuously outputs a low voltage signal.

[0556] In the fifth stage, the potential of the N-1th stage drive signal output by NS(N-1) jumps from high voltage to low voltage, GCK outputs a high voltage signal, GCB outputs a low voltage signal, T1-19 and T1-21 are turned off, the potentials of N1-5 and N1-9 are maintained at high voltage, and the potentials of the remaining nodes remain unchanged, ensuring that NS(N) outputs a high voltage signal.

[0557] In the sixth stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output by GCK jumps from high voltage to low voltage, GCB outputs a high voltage signal, T1-19 and T1-21 are turned on, controlling the potentials of N1-5 and N1-9 to be low voltage, T1-24 and T1-18 are turned on, the potentials of NC1-2 and N1-6 are low voltage, T1-26 is turned on, the potential of N1-6 is low voltage, ensuring that T1-23 is turned on, the potential of N1-5 is low voltage, so that T1-13 is turned on, T1-12 is turned on, so that the potentials of N1-7 and N1-8 are pulled low, T1-15 is turned on, GCB writes a high voltage signal to N1-3, the potential of N1-5 is low voltage, so that T1-17 is turned on, pulling the potential of NC1-1 high voltage, ensuring that T1-25 is turned off.

[0558] Figure 24A At least one embodiment of the driving circuit shown is Figure 23 The difference in at least one embodiment of the driving circuit shown is that:

[0559] The first second node control circuit includes a first fourth transistor T1-4 and a first control transistor TC1;

[0560] The gate of the first fourth transistor T1-4 is electrically connected to the first third control node NC1-3, the source of the first fourth transistor T1-4 is electrically connected to the drain of the first control transistor TC1, and the drain of the first fourth transistor T1-4 is electrically connected to the high voltage terminal VGH.

[0561] The gate of the first control transistor TC1 is electrically connected to the Nth stage output drive terminal NO(N), and the source of the first control transistor TC1 is electrically connected to the first second node N1-2.

[0562] This disclosure Figure 24A In at least one embodiment of the driving circuit shown, when NO(N) outputs a low voltage signal and the potential of NC1-3 is low, T1-4 and TC1 are turned on to connect N1-2 to VGH, making the potential of N1-2 high, ensuring that T1-5 is turned off, and ensuring that NO(N) outputs a low voltage signal.

[0563] exist Figure 24A In the diagram, the nodes labeled N1-11 are the first eleventh nodes.

[0564] Figure 24B This is a public announcement Figure 24A Simulation timing diagram of at least one embodiment of the driving circuit shown.

[0565] Figure 25The difference between at least one embodiment of the driving circuit shown and at least one embodiment of the driving circuit shown in FIG. 24 is that:

[0566] This disclosure Figure 25 At least one embodiment of the driving circuit shown further includes a first initialization circuit;

[0567] The first initialization circuit includes a first seventh transistor T1-7;

[0568] The gate of the first seventh transistor T1-7 is electrically connected to the initial control terminal NCX, the source of the first seventh transistor T1-7 is electrically connected to the first first node N1-1, and the drain of the first seventh transistor T1-7 is electrically connected to the low voltage terminal VGL.

[0569] exist Figure 25 In at least one embodiment of the driving circuit shown, T1-7 are p-type transistors.

[0570] This disclosure Figure 25 At least one embodiment of the driving circuit shown, when in operation,

[0571] When the display starts (i.e., when the display device is powered on), during the reset phase before the first stage, NCX outputs a low voltage signal, T1-7 turns on to control the potential of N1-1 to be low, T1-3 turns on to control the connection between NC1-1 and N1-2; T1-9 turns on to control the connection between NC1-3 and N1-5; T1-20 turns on to control the potential of N1-5 and NC1-3 to be high. At this time, NC1-1 and N1-2 are at low potential, T1-25 turns on, T1-5 turns on, and NS(N) and NO(N) both output high voltage signals. This can turn on all pixel circuits in the effective display area, including the second display control transistor M2, clear the residual charge in the storage capacitor Cst, and improve the poor screen flicker at startup.

[0572] Subsequently, when both NS(N) and N1-3(N-1) output low voltage signals, T1-1 and T1-2 are turned on to control the connection between VCT and N1-1;

[0573] When VCT provides a low voltage signal, the potential of N1-1 is low, and C1-1 maintains the potential of N1-1; T1-3 is turned on to control the connection between NC1-1 and N1-2. At this time, the potential of NC1-1 is high, the potential of N1-2 is high, T1-5 is turned off, and T1-9 is turned on to control the connection between NC1-3 and N1-5. The potential of NC1-3 is high, and NO(N) continuously outputs a low voltage signal.

[0574] When VCT provides a high voltage signal, the potential of N1-1 is high, T1-3 is off, NC1-1 and N1-2 are disconnected, C1-1 controls the potential of N1-2 to be high, T1-9 is off, NC1-3 and N1-5 are disconnected, the potential of N1-6 is high, T1-10 and T1-11 are off, the potential of NC1-3 is maintained at low voltage, T1-6 is on, and NO(N) outputs a low voltage signal;

[0575] Subsequently, during the Nth stage drive signal provision phase, NS(N) outputs a high-voltage signal. At this time, the potential of NC1-1 is low, and the potential of NC1-2 is high. When the potential of N1-1 is low, T1-3 is turned on, connecting NC1-1 and N1-2. When the potential of N1-2 is low, T1-9 is turned on to control the connection between N1-5 and NC1-3. When the potential of N1-5 is high, the potential of NC1-3 is high, and T1-6 is turned off. When T1-5 is turned on and T1-6 is turned off, NO(N) outputs a high-voltage signal.

[0576] When the potential of N1-1 is high, T1-3 is turned off, disconnecting NC1-1 from N1-2. The potential of N1-2 remains high, and T1-9 is turned off to disconnect N1-5 from NC1-3. The potential of NC1-3 remains low, and T1-6 is turned on. When T1-5 is turned off, NO(N) continuously outputs a low voltage signal.

[0577] After the Nth stage drive signal provision phase, when the potential of N1-4 is low, T1-8 opens to control the connection between N1-1 and VGL. When the potential of N1-1 is low, T1-3 opens to control the connection between NC1-1 and N1-2. At this time, the potential of NC1-1 is high, the potential of NC1-2 is low, the potential of N1-2 is high, and T1-9 opens to control the connection between NC1-3 and N1-5. When the potentials of N1-5 and N1-6 are both low, T1-10 and T1-11 open, the potential of NC1-3 is low, and NO(N) outputs a low voltage signal.

[0578] This disclosure Figure 25 In at least one embodiment of the driving circuit shown, when N1-3 (N-1) outputs a low voltage signal and NS (N) outputs a low voltage signal, T1-1 and T1-2 are turned on. By simultaneously selecting the two signals, the state of the gating input signal within a high-low frequency switching cycle can be obtained and written to N1-1. T1-1 and T1-2 will not be turned on at other times to prevent the potential of N1-1 from being affected by the gating input signal provided by VCT.

[0579] This disclosure Figure 25In at least one embodiment of the driving circuit shown, when both NS(N) and N3(N-1) output low voltage signals, and VCT outputs a low voltage signal, the potential of N1-1 is low, T1-3 is turned on, the potential of N1-2 is the same as the potential of NC1-1, NC1-3 is turned off, T1-6 is turned off, and T1-5 is turned on for N1-2, which can ensure that NO(N) is output normally.

[0580] If NS(N) and N1-3(N-1) both output low voltage signals, and VCT outputs a high voltage signal, then N1-1's potential is high, T1-3 is off, T1-9 is off, N1-2's potential is high, T1-5 is off, N1-6's potential is high, T1-11 is in reverse cutoff state, NC1-3's potential is maintained at low voltage, and T1-6 is turned on to ensure that NO(N) always outputs a low voltage signal; NC1-3's potential is low, so T1-4 is turned on to maintain N1-2's potential at high voltage and prevent T1-5 from leaking current. After NO(N) finishes outputting, N1-4's ​​potential is low, so T1-8 is turned on to pull N1-1's potential down to low voltage.

[0581] This disclosure Figure 26 The difference between at least one embodiment of the driving circuit shown and at least one embodiment of the driving circuit shown in FIG. 24 is that:

[0582] This disclosure Figure 26 At least one embodiment of the driving circuit shown further includes a first output pull-down circuit;

[0583] The first output pull-down circuit includes the first twenty-seventh transistor T1-27;

[0584] The gate of the first twenty-seventh transistor T1-27 is electrically connected to the first first control node NC1-1, the source of the first twenty-seventh transistor T1-27 is electrically connected to the Nth stage drive signal output terminal NS(N), and the drain of the first twenty-seventh transistor T1-27 is electrically connected to the low voltage terminal VGL.

[0585] exist Figure 26 In at least one embodiment of the driving circuit shown, T1-27 is an n-type transistor.

[0586] Figure 26 In at least one embodiment of the driving circuit shown, when the potential of NC1-1 is high, T1-27 is turned on, NS(N) is connected to VGL, and NS(N) outputs a low voltage signal.

[0587] Figure 27 At least one embodiment of the driving circuit shown is Figure 23The difference in at least one embodiment of the driving circuit shown is that it does not include a first fourth transistor T1-4.

[0588] Figure 28 At least one embodiment of the driving circuit shown is Figure 23 The difference in at least one embodiment of the driving circuit shown is that it does not include the first eighth transistor T1-8.

[0589] Figure 29 The difference between at least one embodiment of the driving circuit shown and at least one embodiment of the driving circuit shown in FIG24 is that the latter does not include the first eighth transistor T1-8.

[0590] Figure 30 At least one embodiment of the driving circuit shown is Figure 23 The difference in at least one embodiment of the driving circuit shown is that T1-3 is a single-gate transistor.

[0591] like Figure 31 As shown, the driving circuit described in this embodiment includes a second driving signal generation circuit 210, a second gating circuit 211, a second output control circuit 212, and a second output circuit 213.

[0592] The second drive signal generation circuit 210 is electrically connected to the Nth stage drive signal output terminal NS(N) and is used to generate and output the Nth stage drive signal through the Nth stage drive signal output terminal NS(N).

[0593] The second gating circuit 211 is electrically connected to the second first node N2-1, the gating input terminal VCT, and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the second first node N2-1 under the control of the gating control signal provided by the gating control terminal CX;

[0594] The first terminal of the second output control circuit 212 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the second output control circuit 212 is electrically connected to the second first node N2-1. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the second output control circuit 212 to obtain the first output signal.

[0595] The second output circuit 213 is electrically connected to the second output control circuit 212 and the output drive terminal NO(N) respectively, and is used to invert the first output signal to obtain an output drive signal provided through the output drive terminal NO(N);

[0596] N is a positive integer.

[0597] This disclosure Figure 31In the embodiment of the driving circuit shown, during operation, the second driving signal generation circuit 210 generates and outputs the Nth-level driving signal through the Nth-level driving signal output terminal NS(N). Under the control of the gating control signal, the second gating circuit 211 writes the gating input signal into the second first node N2-1. The second output control circuit 212 performs a NAND operation on the potential of the Nth-level driving signal and the second terminal of the second output control circuit 212 to obtain the first output signal. The second output circuit 213 inverts the first output signal to obtain the output driving signal provided through the output driving terminal NO(N).

[0598] This disclosure Figure 31 The embodiment of the driving circuit shown can be the Nth stage driving circuit.

[0599] This disclosure Figure 31 The illustrated driving circuit embodiment, when in operation, within one frame time,

[0600] Before the Nth stage of driving signal provision, the second gating circuit 211, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT into the second first node N2-1;

[0601] When the strobe input signal is a high voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first output signal output by the second output control circuit 212 is a low voltage signal. The second output circuit 213 provides a high voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit to update the pixel voltage.

[0602] When the strobe input signal is a low voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first output signal output by the second output control circuit 212 is a high voltage signal. The second output circuit 213 provides a low voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit not to update the pixel voltage.

[0603] This disclosure embodiment can update a portion of the display screen by controlling the gating input signal provided by the gating input terminal VCT, thereby reducing power consumption, or achieve ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and notebook computers by updating the display screen partially.

[0604] The driving circuit described in at least one embodiment of this disclosure may further include a second initialization circuit and a second first voltage sustaining circuit;

[0605] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the second first node, respectively, and is used to control the connection between the second first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal;

[0606] The first terminal of the second first voltage sustaining circuit is electrically connected to the second first node, and the second terminal of the second first voltage sustaining circuit is electrically connected to a DC voltage terminal or a second third node. The second first voltage sustaining circuit is used to maintain the potential of the second first node.

[0607] In a specific implementation, the driving circuit may further include a second initialization circuit and a second first voltage maintenance circuit; the second initialization circuit controls the connection between the second first node and the first voltage terminal under the control of the initial control signal, and the first potential maintenance circuit maintains the potential of the second first node.

[0608] like Figure 32 As shown, in Figure 31 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure may further include a second initialization circuit 221 and a second first voltage sustaining circuit 222;

[0609] The second initialization circuit 221 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the second first node N2-1 respectively, and is used to control the connection between the second first node N2-1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX;

[0610] The first terminal of the second first voltage sustaining circuit 222 is electrically connected to the second first node N2-1, and the second terminal of the second first voltage sustaining circuit 222 is electrically connected to the first voltage terminal V1. The second first voltage sustaining circuit 222 is used to maintain the potential of the second first node N2-1.

[0611] Figure 32 In at least one embodiment of the driving circuit shown, when in operation, at the start of a frame time, NCX provides an effective voltage signal, and the second initialization circuit 221 controls the connection between the second first node N2-1 and the first voltage terminal V1.

[0612] In at least one embodiment of this disclosure, the first voltage terminal may be a high voltage terminal, but is not limited thereto.

[0613] The driving circuit described in at least one embodiment of this disclosure may further include a second second voltage sustaining circuit, the second second voltage sustaining circuit including a second first inverter, a second second inverter, and a second sustaining control circuit;

[0614] The input terminal of the second first inverter is electrically connected to the second first node, the output terminal of the second first inverter is electrically connected to the second third node, the input terminal of the second second inverter is electrically connected to the second third node, and the output terminal of the second second inverter is electrically connected to the second fourth node.

[0615] The second first inverter is used to invert the potential of the second first node, and outputs the inverted potential of the second first node through the output terminal of the second first inverter;

[0616] The second inverter is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter.

[0617] The second maintenance control circuit is electrically connected to the maintenance control terminal, the second fourth node, and the second first node, respectively, and is used to control the connection or disconnection between the second fourth node and the second first node under the control of the maintenance control signal provided by the maintenance control terminal.

[0618] In a specific implementation, the driving circuit may further include a second second voltage sustaining circuit. The second second voltage sustaining circuit includes a second first inverter, a second second inverter, and a second sustaining control circuit. The second first inverter inverts the potential of the second first node, and the second second inverter inverts the potential of its input terminal. Under the control of the sustaining control signal, the second sustaining control circuit controls the connection or disconnection between the second fourth node and the second first node.

[0619] The second sustaining control circuit can disconnect the second fourth node from the second first node when the second gating circuit controls the gating input signal to be written to the second first node, so as not to affect the potential of the second first node.

[0620] In at least one embodiment of the driving circuit described in this disclosure, when in operation, a second second voltage sustaining circuit is added. The second second voltage sustaining circuit includes a second first inverter and a second second inverter. When the potential of the second first node is high, the output terminal of the second second inverter is connected to the high voltage terminal, which makes the potential of the output terminal of the second second inverter higher than the potential of the second first node. When the potential of the second first node is low, the output terminal of the second second inverter is connected to the low voltage terminal, which makes the potential of the output terminal of the second second inverter lower than the potential of the second first node. Furthermore, the second sustaining control circuit included in the second second voltage sustaining circuit can control the connection between the output terminal of the second second inverter and the second first node during the Nth stage of driving signal output, thereby increasing the absolute value of the potential of the second first node. This allows the second first node to better control the transistor whose gate is electrically connected to the second first node, which is included in the second output control circuit.

[0621] like Figure 33 As shown, in Figure 32 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure may further include a second second voltage sustaining circuit, the second second voltage sustaining circuit including a second first inverter F21, a second second inverter F22 and a second sustaining control circuit W21; the sustaining control terminal includes an N-1 stage driving signal output terminal NS(N-1) and a first clock signal terminal GCK;

[0622] The input terminal of the second first inverter F21 is electrically connected to the second first node N2-1, and the output terminal of the second first inverter F21 is electrically connected to the second third node N2-3;

[0623] The input terminal of the second inverter F22 is electrically connected to the second third node N2-3, and the output terminal of the second inverter F22 is electrically connected to the second fourth node N2-4.

[0624] The second first inverter F21 is used to invert the potential of the second first node N2-1, and outputs the inverted potential of the second first node through the output terminal of the second first inverter F21;

[0625] The second inverter F22 is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter F22.

[0626] The second sustaining control circuit W21 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the second fourth node N2-4, and the second first node N2-1, respectively. Under the control of the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1), it controls the connection or disconnection between the second fourth node N2-4 and the second first node N2-1. Under the control of the first clock signal provided by the first clock signal terminal GCK, it controls the connection or disconnection between the second fourth node N2-4 and the second first node N2-1.

[0627] exist Figure 33 In at least one of the embodiments shown, the N-1th stage drive signal output terminal can be replaced with a second clock signal terminal, but is not limited thereto.

[0628] In at least one embodiment of this disclosure, the driving circuit may further include a second second voltage sustaining circuit;

[0629] The second first node is electrically connected to the second terminal of the second output control circuit through the second second voltage sustaining circuit.

[0630] The second voltage sustaining circuit includes a second first inverter, a second second inverter, and a second sustaining control circuit.

[0631] The input terminal of the second first inverter is electrically connected to the second first node, the output terminal of the second first inverter is electrically connected to the second third node, the input terminal of the second second inverter is electrically connected to the second third node, and the output terminal of the second second inverter is electrically connected to the second fourth node and the second terminal of the second output control circuit.

[0632] The second first inverter is used to invert the potential of the second first node and output the inverted potential of the second first node through the output terminal of the second first inverter. The second second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second second inverter.

[0633] The second maintenance control circuit is electrically connected to the maintenance control terminal, the second fourth node, and the second first node, respectively, and is used to control the connection or disconnection between the second fourth node and the second first node under the control of the maintenance control signal provided by the maintenance control terminal.

[0634] In a specific implementation, the driving circuit may further include a second second voltage sustaining circuit. The second first node can be electrically connected to the second terminal of the second output control circuit through the second second voltage sustaining circuit. The second second voltage sustaining circuit may include a second first inverter, a second second inverter, and a second sustaining control circuit. The second first inverter inverts the potential of the second first node, and the second second inverter inverts the potential of its input terminal. Under the control of the sustaining control signal provided by the sustaining control terminal, the second sustaining control circuit controls the connection or disconnection between the second fourth node and the second first node.

[0635] The second sustaining control circuit can disconnect the second fourth node from the second first node when the second gating circuit controls the gating input signal to be written to the second first node.

[0636] When the driving circuit described in at least one embodiment of this disclosure is in operation, by adding a second second voltage sustaining circuit, the second second voltage sustaining circuit includes a second first inverter and a second second inverter. When the potential of the second first node is high, the second fourth node can be connected to the high voltage terminal, so that the potential of the second fourth node is higher than the potential of the second first node. When the potential of the second first node is low, the second fourth node can be connected to the low voltage terminal, so that the potential of the second fourth node is lower than the potential of the second first node. This allows the second fourth node to better control the transistor whose gate is electrically connected to the second fourth node in the second output control circuit.

[0637] like Figure 34 As shown, in Figure 32 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a second second voltage sustaining circuit; the sustaining control terminal includes an N-1th stage driving signal output terminal NS(N-1) and a first clock signal terminal GCK;

[0638] The second first node N2-1 is electrically connected to the second terminal of the second output control circuit 212 through the second second voltage maintenance circuit;

[0639] The second voltage sustaining circuit includes a second first inverter F21, a second second inverter F22, and a second sustaining control circuit W21;

[0640] The input terminal of the second first inverter F21 is electrically connected to the second first node N2-1, and the output terminal of the second first inverter F21 is electrically connected to the second third node N2-3;

[0641] The input terminal of the second inverter F22 is electrically connected to the second third node N2-3, and the output terminal of the second inverter F22 is electrically connected to the second fourth node N2-4 and the second terminal of the second output control circuit 12.

[0642] The second first inverter F21 is used to invert the potential of the second first node N2-1, and outputs the inverted potential of the second first node through the output terminal of the second first inverter F21;

[0643] The second inverter F22 is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter F22.

[0644] The second sustaining control circuit W21 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the second fourth node N2-4, and the second first node N2-1, respectively. Under the control of the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1), it controls the connection or disconnection between the second fourth node N2-4 and the second first node N2-1. Under the control of the first clock signal provided by the first clock signal terminal GCK, it controls the connection or disconnection between the second fourth node N2-4 and the second first node N2-1.

[0645] exist Figure 34 In at least one of the embodiments shown, the N-1th stage drive signal output terminal can be replaced with a second clock signal terminal, but is not limited thereto.

[0646] Optionally, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0647] The second sustaining control circuit includes a second third transistor and a second fourth transistor;

[0648] The gate of the second and third transistors is electrically connected to the first sustaining control terminal, the first terminal of the second and third transistors is electrically connected to the second first node, and the second terminal of the second and third transistors is electrically connected to the second fourth node.

[0649] The gate of the second fourth transistor is electrically connected to the second sustain control terminal, the first terminal of the second fourth transistor is electrically connected to the second fourth node, and the second terminal of the second fourth transistor is electrically connected to the second first node.

[0650] The second and third transistors are p-type transistors, and the second and fourth transistors are n-type transistors;

[0651] The first sustain control terminal is the (N-1)th stage drive signal terminal, and the second sustain control terminal is the first clock signal terminal; or,

[0652] The first sustain control terminal is the second clock signal terminal, and the second sustain control terminal is the first clock signal terminal.

[0653] Optionally, the second first inverter includes a second fifth transistor and a second sixth transistor, and the second second inverter includes a second seventh transistor and a second eighth transistor;

[0654] The gate of the second fifth transistor is electrically connected to the second first node, the first terminal of the second fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the second fifth transistor is electrically connected to the second third node.

[0655] The gate of the second sixth transistor is electrically connected to the second first node, the first terminal of the second sixth transistor is electrically connected to the second third node, and the second terminal of the second sixth transistor is electrically connected to the second voltage terminal.

[0656] The second fifth transistor is a p-type transistor, and the second sixth transistor is an n-type transistor;

[0657] The gate of the second seventh transistor is electrically connected to the second third node, the first terminal of the second seventh transistor is electrically connected to the first voltage terminal, and the second terminal of the second seventh transistor is electrically connected to the second fourth node.

[0658] The gate of the second eighth transistor is electrically connected to the second third node, the first terminal of the second eighth transistor is electrically connected to the second fourth node, and the second terminal of the second eighth transistor is electrically connected to the second voltage terminal.

[0659] The second seventh transistor is a p-type transistor, and the second eighth transistor is an n-type transistor.

[0660] Optionally, the second initialization circuit includes a second ninth transistor, and the second first voltage sustaining circuit includes a second first capacitor;

[0661] The gate of the second ninth transistor is electrically connected to the initial control terminal, the first terminal of the second ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the second ninth transistor is electrically connected to the second first node.

[0662] The first terminal of the second first capacitor is electrically connected to the second first node, and the second terminal of the second first capacitor is electrically connected to the DC voltage terminal or the second third node.

[0663] Optionally, the second output control circuit includes a second tenth transistor, a second eleventh transistor, a second twelfth transistor, and a second thirteenth transistor;

[0664] The gate of the second tenth transistor is electrically connected to the Nth stage drive signal output terminal, the first terminal of the second tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the second tenth transistor is electrically connected to the second fifth node.

[0665] The gate of the second eleventh transistor is electrically connected to the second first node, the first terminal of the second eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the second eleventh transistor is electrically connected to the second fifth node.

[0666] The gate of the second twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the second twelfth transistor is electrically connected to the second fifth node, and the second terminal of the second twelfth transistor is electrically connected to the second sixth node.

[0667] The gate of the second thirteenth transistor is electrically connected to the second first node, the first terminal of the second thirteenth transistor is electrically connected to the second sixth node, and the second terminal of the second thirteenth transistor is electrically connected to the second voltage terminal.

[0668] The second tenth transistor and the second eleventh transistor are p-type transistors, and the second twelfth transistor and the second thirteenth transistor are n-type transistors.

[0669] Optionally, the second output control circuit includes a second tenth transistor, a second eleventh transistor, a second twelfth transistor, and a second thirteenth transistor;

[0670] The gate of the second tenth transistor is electrically connected to the Nth stage drive signal output terminal, the first terminal of the second tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the second tenth transistor is electrically connected to the second fifth node.

[0671] The gate of the second eleventh transistor is electrically connected to the second fourth node, the first terminal of the second eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the second eleventh transistor is electrically connected to the second fifth node.

[0672] The gate of the second twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the second twelfth transistor is electrically connected to the second fifth node, and the second terminal of the second twelfth transistor is electrically connected to the second sixth node.

[0673] The gate of the second thirteenth transistor is electrically connected to the second fourth node, the first terminal of the second thirteenth transistor is electrically connected to the second sixth node, and the second terminal of the second thirteenth transistor is electrically connected to the second voltage terminal.

[0674] The second tenth transistor and the second eleventh transistor are p-type transistors, and the second twelfth transistor and the second thirteenth transistor are n-type transistors.

[0675] Optionally, the second output circuit includes a second fourteenth transistor and a second fifteenth transistor;

[0676] The gate of the second fourteenth transistor is electrically connected to the second fifth node, the first terminal of the second fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the second fourteenth transistor is electrically connected to the output drive terminal.

[0677] The gate of the second fifteenth transistor is electrically connected to the second fifth node, the first terminal of the second fifteenth transistor is electrically connected to the output drive terminal, and the second terminal of the second fifteenth transistor is electrically connected to the second voltage terminal.

[0678] In at least one embodiment of this disclosure, the second drive signal generation circuit may include a second first control node control circuit, a second second control node control circuit, a second first drive output circuit, and a second second drive output circuit.

[0679] The second first control node control circuit is used to control the potential of the first control node;

[0680] The second control node control circuit is used to control the potential of the second control node;

[0681] The second first drive output circuit is electrically connected to the first control node, the first voltage terminal and the Nth stage drive signal output terminal respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the potential of the first control node.

[0682] The second second drive output circuit is electrically connected to the second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the second control node.

[0683] In a specific implementation, the second drive signal generation circuit may include a second first control node control circuit, a second second control node control circuit, a second first drive output circuit, and a second second drive output circuit. The second first control node control circuit is used to control the potential of the first control node; the second second control node control circuit controls the potential of the second control node; the second first drive output circuit, under the control of the potential of the first control node, controls the connection between the Nth stage drive signal output terminal and the first voltage terminal; the second second drive output circuit, under the control of the potential of the second control node, controls the connection between the Nth stage drive signal output terminal and the second voltage terminal.

[0684] Optionally, the first voltage terminal can be a high voltage terminal and the second voltage terminal can be a low voltage terminal, but this is not a limitation.

[0685] like Figure 35 As shown, in Figure 33 Based on at least one embodiment of the driving circuit shown, the second driving signal generation circuit may include a second first control node control circuit 231, a second second control node control circuit 232, a second first driving output circuit 233, and a second second driving output circuit 234.

[0686] The second first control node control circuit 231 is electrically connected to the first control node NC2-1 and is used to control the potential of the first control node NC2-1;

[0687] The second control node control circuit 232 is electrically connected to the second control node NC2-2 and is used to control the potential of the second control node NC2-2.

[0688] The second first drive output circuit 233 is electrically connected to the first control node NC2-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N) respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V12 under the control of the potential of the first control node NC2-1.

[0689] The second second drive output circuit 234 is electrically connected to the second control node NC2-2, the second voltage terminal V2 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the second control node NC2-2.

[0690] like Figure 36 As shown, in Figure 34Based on at least one embodiment of the driving circuit shown, the second driving signal generation circuit may include a second first control node control circuit 231, a second second control node control circuit 232, a second first driving output circuit 233, and a second second driving output circuit 234.

[0691] The second first control node control circuit 231 is electrically connected to the first control node NC2-1 and is used to control the potential of the first control node NC2-1;

[0692] The second control node control circuit 232 is electrically connected to the second control node NC2-2 and is used to control the potential of the second control node NC2-2.

[0693] The second first drive output circuit 233 is electrically connected to the first control node NC2-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N) respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V12 under the control of the potential of the first control node NC2-1.

[0694] The second second drive output circuit 234 is electrically connected to the second control node NC2-2, the second voltage terminal V2 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the second control node NC2-2.

[0695] In at least one embodiment of this disclosure, the second first control node control circuit includes a second seventh node control circuit, a second eighth node control circuit, and a second first control circuit;

[0696] The second seventh node control circuit is electrically connected to the first clock signal terminal, the first voltage terminal, the second seventh node, and the second ninth node, respectively. It is used to control the connection between the second seventh node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the second seventh node and the first clock signal terminal under the control of the potential of the second ninth node.

[0697] The second eighth node control circuit is electrically connected to the second voltage terminal, the second seventh node, and the second eighth node, respectively, and is used to control the connection between the second seventh node and the second eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0698] The second first control circuit is electrically connected to the second eighth node, the second second node, the second clock signal terminal, the second ninth node, the first voltage terminal, and the first control node, respectively. It is used to control the connection between the second second node and the second clock signal terminal under the control of the potential of the second eighth node, control the potential of the second second node according to the potential of the second eighth node, control the connection between the second second node and the first control node under the control of the second clock signal provided by the second clock signal terminal, and control the connection between the first control node and the first voltage terminal under the control of the potential of the second ninth node.

[0699] In a specific implementation, the second first control node control circuit may include a second seventh node control circuit, a second eighth node control circuit, and a second first control circuit. The second seventh node control circuit controls the potential of the second seventh node, the second eighth node control circuit controls the potential of the second eighth node, and the second first control circuit controls the potential of the first control node.

[0700] In at least one embodiment of this disclosure, the second second control node control circuit includes a second ninth node control circuit, a second tenth node control circuit, a second eleventh node control circuit, and a second second control circuit.

[0701] The second ninth node control circuit is electrically connected to the first clock signal terminal, the (N-1)th stage drive signal output terminal, the initial control terminal, the first voltage terminal, and the second ninth node, respectively. It is used to control the connection between the (N-1)th stage drive signal output terminal and the second ninth node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the second ninth node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0702] The second tenth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal and the second tenth node respectively, and is used to control the connection between the N-1th stage drive signal output terminal and the second tenth node under the control of the first clock signal.

[0703] The second eleventh node control circuit is electrically connected to the second voltage terminal, the second tenth node, the second eleventh node, the second seventh node, the first voltage terminal, the second twelfth node, and the second clock signal terminal, respectively. It is used to control the connection between the second tenth node and the second eleventh node under the control of the second voltage signal provided by the second voltage terminal, to control the connection between the second twelfth node and the first voltage terminal under the control of the potential of the second seventh node, and to control the connection between the second twelfth node and the second clock signal terminal under the control of the potential of the second eleventh node. It is also used to control the potential of the second eleventh node according to the potential of the second twelfth node.

[0704] The second control circuit is electrically connected to the second control node, the second eleventh node, the second voltage terminal, and the second ninth node, respectively. It is used to control the potential of the second control node under the control of the potential of the second eleventh node, and to control the connection between the second ninth node and the second control node under the control of the second voltage signal provided by the second voltage terminal.

[0705] In a specific implementation, the second control node control circuit may include a second ninth node control circuit, a second tenth node control circuit, a second eleventh node control circuit, and a second second control circuit. The second ninth node control circuit controls the potential of the second ninth node, the second tenth node control circuit controls the potential of the second tenth node, the second eleventh node control circuit controls the potential of the second eleventh node, and the second second control circuit controls the potential of the second control node.

[0706] like Figure 37 As shown, in Figure 35 Based on at least one embodiment of the driving circuit shown, the second first control node control circuit includes a second seventh node control circuit 241, a second eighth node control circuit 242, and a second first control circuit 243;

[0707] The second seventh node control circuit 241 is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the second seventh node N2-7, and the second ninth node N2-9, respectively. It is used to control the connection between the second seventh node N2-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the second seventh node N2-7 and the first clock signal terminal GCK under the control of the potential of the second ninth node N2-9.

[0708] The second eighth node control circuit 242 is electrically connected to the second voltage terminal V2, the second seventh node N2-7 and the second eighth node N2-8 respectively, and is used to control the connection between the second seventh node N2-7 and the second eighth node N2-8 under the control of the second voltage signal provided by the second voltage terminal V2;

[0709] The second first control circuit 243 is electrically connected to the second eighth node N2-8, the second second node N2-2, the second clock signal terminal GCB, the second ninth node N2-9, the first voltage terminal V1, and the first control node NC2-1, respectively. It is used to control the connection between the second second node N2-2 and the second clock signal terminal GCB under the control of the potential of the second eighth node N2-8; to control the potential of the second second node N2-2 according to the potential of the second eighth node N2-8; to control the connection between the second second node N2-2 and the first control node NC2-1 under the control of the second clock signal provided by the second clock signal terminal GCB; and to control the connection between the first control node NC2-1 and the first voltage terminal V1 under the control of the potential of the second ninth node N2-9.

[0710] The second second control node control circuit includes a second ninth node control circuit 251, a second tenth node control circuit 252, a second eleventh node control circuit 253, and a second second control circuit 254.

[0711] The second ninth node control circuit 251 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), the initial control terminal NCX, the first voltage terminal V1, and the second ninth node N2-9, respectively. It is used to control the connection between the N-1th stage drive signal output terminal NS(N-1) and the second ninth node N2-9 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the second ninth node N2-9 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0712] The second tenth node control circuit 252 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the second tenth node N2-10, respectively, and is used to control the connection between the N-1th stage drive signal output terminal NS(N-1) and the second tenth node N2-10 under the control of the first clock signal.

[0713] The second eleventh node control circuit 253 is electrically connected to the second voltage terminal V2, the second tenth node N2-10, the second eleventh node N2-11, the second seventh node N2-7, the first voltage terminal V1, the second twelfth node N2-12, and the second clock signal terminal GCB, respectively. It is used to control the connection between the second tenth node N2-10 and the second eleventh node N2-11 under the control of the second voltage signal provided by the second voltage terminal V2; to control the connection between the second twelfth node N2-12 and the first voltage terminal V1 under the control of the potential of the second seventh node N2-7; and to control the connection between the second twelfth node N2-12 and the second clock signal terminal GCB under the control of the potential of the second eleventh node N2-11. It is also used to control the potential of the second eleventh node N2-11 according to the potential of the second twelfth node N2-12.

[0714] The second control circuit 254 is electrically connected to the second control node NC2-2, the second eleventh node N2-11, the second voltage terminal V2, and the second ninth node N2-9, respectively. It is used to control the potential of the second control node NC2-2 under the control of the potential of the second eleventh node N2-11, and to control the connection between the second ninth node N2-9 and the second control node NC2-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0715] like Figure 38 As shown, in Figure 36 Based on at least one embodiment of the driving circuit shown, the second first control node control circuit includes a second seventh node control circuit 241, a second eighth node control circuit 242, and a second first control circuit 243;

[0716] The second seventh node control circuit 241 is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the second seventh node N2-7, and the second ninth node N2-9, respectively. It is used to control the connection between the second seventh node N2-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the second seventh node N2-7 and the first clock signal terminal GCK under the control of the potential of the second ninth node N2-9.

[0717] The second eighth node control circuit 242 is electrically connected to the second voltage terminal V2, the second seventh node N2-7 and the second eighth node N2-8 respectively, and is used to control the connection between the second seventh node N2-7 and the second eighth node N2-8 under the control of the second voltage signal provided by the second voltage terminal V2;

[0718] The second first control circuit 243 is electrically connected to the second eighth node N2-8, the second second node N2-2, the second clock signal terminal GCB, the second ninth node N2-9, the first voltage terminal V1, and the first control node NC2-1, respectively. It is used to control the connection between the second second node N2-2 and the second clock signal terminal GCB under the control of the potential of the second eighth node N2-8; to control the potential of the second second node N2-2 according to the potential of the second eighth node N2-8; to control the connection between the second second node N2-2 and the first control node NC2-1 under the control of the second clock signal provided by the second clock signal terminal GCB; and to control the connection between the first control node NC2-1 and the first voltage terminal V1 under the control of the potential of the second ninth node N2-9.

[0719] The second second control node control circuit includes a second ninth node control circuit 251, a second tenth node control circuit 252, a second eleventh node control circuit 253, and a second second control circuit 254.

[0720] The second ninth node control circuit 251 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), the initial control terminal NCX, the first voltage terminal V1, and the second ninth node N2-9, respectively. It is used to control the connection between the N-1th stage drive signal output terminal NS(N-1) and the second ninth node N2-9 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the second ninth node N2-9 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0721] The second tenth node control circuit 252 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the second tenth node N2-10, respectively, and is used to control the connection between the N-1th stage drive signal output terminal NS(N-1) and the second tenth node N2-10 under the control of the first clock signal.

[0722] The second eleventh node control circuit 253 is electrically connected to the second voltage terminal V2, the second tenth node N2-10, the second eleventh node N2-11, the second seventh node N2-7, the first voltage terminal V1, the second twelfth node N2-12, and the second clock signal terminal GCB, respectively. It is used to control the connection between the second tenth node N2-10 and the second eleventh node N2-11 under the control of the second voltage signal provided by the second voltage terminal V2; to control the connection between the second twelfth node N2-12 and the first voltage terminal V1 under the control of the potential of the second seventh node N2-7; and to control the connection between the second twelfth node N2-12 and the second clock signal terminal GCB under the control of the potential of the second eleventh node N2-11. It is also used to control the potential of the second eleventh node N2-11 according to the potential of the second twelfth node N2-12.

[0723] The second control circuit 254 is electrically connected to the second control node NC2-2, the second eleventh node N2-11, the second voltage terminal V2, and the second ninth node N2-9, respectively. It is used to control the potential of the second control node NC2-2 under the control of the potential of the second eleventh node N2-11, and to control the connection between the second ninth node N2-9 and the second control node NC2-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0724] Optionally, the second first drive output circuit includes a second sixteenth transistor and a second second capacitor;

[0725] The gate of the second sixteenth transistor is electrically connected to the first control node, the first terminal of the second sixteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the second sixteenth transistor is electrically connected to the Nth stage drive signal output terminal.

[0726] The first terminal of the second capacitor is electrically connected to the first control node, and the second terminal of the second capacitor is electrically connected to the first voltage terminal.

[0727] The second second drive output circuit includes a second seventeenth transistor and a second third capacitor;

[0728] The gate of the second seventeenth transistor is electrically connected to the second control node, the first terminal of the second seventeenth transistor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the second seventeenth transistor is electrically connected to the second voltage terminal.

[0729] The first terminal of the second third capacitor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the second third capacitor is electrically connected to the second voltage terminal.

[0730] Optionally, the second seventh node control circuit includes a second eighteenth transistor and a second nineteenth transistor;

[0731] The gate of the second eighteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the second eighteenth transistor is electrically connected to the second voltage terminal, and the second terminal of the second eighteenth transistor is electrically connected to the second seventh node.

[0732] The gate of the second nineteenth transistor is electrically connected to the second ninth node, the first terminal of the second nineteenth transistor is electrically connected to the second seventh node, and the second terminal of the second nineteenth transistor is electrically connected to the first clock signal terminal.

[0733] The second eighth node control circuit includes a second twentieth transistor;

[0734] The gate of the second twentieth transistor is electrically connected to the second voltage terminal, the first terminal of the second twentieth transistor is electrically connected to the second seventh node, and the second terminal of the second twentieth transistor is electrically connected to the second eighth node.

[0735] The second first control circuit includes a second twenty-first transistor, a second fourth capacitor, a second twenty-second transistor, and a second twenty-third transistor;

[0736] The gate of the second twenty-first transistor is electrically connected to the second eighth node, the first terminal of the second twenty-first transistor is electrically connected to the second clock signal terminal, and the second terminal of the second twenty-first transistor is electrically connected to the second second node;

[0737] The first terminal of the second fourth capacitor is electrically connected to the second eighth node, and the second terminal of the second fourth capacitor is electrically connected to the second second node.

[0738] The gate of the second twenty-second transistor is electrically connected to the second clock signal terminal, the first terminal of the second twenty-second transistor is electrically connected to the second second node, and the second terminal of the second twenty-second transistor is electrically connected to the first control node;

[0739] The gate of the second twenty-third transistor is electrically connected to the second ninth node, the first terminal of the second twenty-third transistor is electrically connected to the first control node, and the second terminal of the second twenty-third transistor is electrically connected to the first voltage terminal.

[0740] Optionally, the second ninth node control circuit includes a second twenty-fourth transistor and a second twenty-fifth transistor;

[0741] The gate of the second twenty-fourth transistor is electrically connected to the first clock signal terminal, the first terminal of the second twenty-fourth transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the second twenty-fourth transistor is electrically connected to the second ninth node.

[0742] The gate of the second twenty-fifth transistor is electrically connected to the initial control terminal, the first terminal of the second twenty-fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the second twenty-fifth transistor is electrically connected to the second ninth node.

[0743] The second tenth node control circuit includes a second twenty-sixth transistor;

[0744] The gate of the second twenty-sixth transistor is electrically connected to the first clock signal terminal, the first terminal of the second twenty-sixth transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the second twenty-sixth transistor is electrically connected to the second tenth node.

[0745] The second eleventh node control circuit includes a second twenty-seventh transistor, a second twenty-eighth transistor, a second twenty-ninth transistor, and a second fifth capacitor;

[0746] The gate of the second twenty-seventh transistor is electrically connected to the second voltage terminal, the first terminal of the second twenty-seventh transistor is electrically connected to the second tenth node, and the second terminal of the second twenty-seventh transistor is electrically connected to the second eleventh node.

[0747] The gate of the second twenty-eighth transistor is electrically connected to the second seventh node, the first terminal of the second twenty-eighth transistor is electrically connected to the first voltage terminal, and the second terminal of the second twenty-eighth transistor is electrically connected to the second twelfth node.

[0748] The gate of the second twenty-ninth transistor is electrically connected to the second eleventh node, the first terminal of the second twenty-ninth transistor is electrically connected to the second twelfth node, and the second terminal of the second twenty-ninth transistor is electrically connected to the second clock signal terminal.

[0749] The first terminal of the second fifth capacitor is electrically connected to the second twelfth node, and the second terminal of the second fifth capacitor is electrically connected to the second eleventh node.

[0750] The second control circuit includes a second thirtieth transistor and a second thirty-first transistor;

[0751] The gate of the second thirtieth transistor and the first terminal of the second thirtieth transistor are both electrically connected to the second eleventh node, and the second terminal of the second thirtieth transistor is electrically connected to the second control node;

[0752] The gate of the second thirty-first transistor is electrically connected to the second voltage terminal, the first terminal of the second thirty-first transistor is electrically connected to the second ninth node, and the second terminal of the second thirty-first transistor is electrically connected to the second control node.

[0753] like Figure 39 As shown, in Figure 37 Based on at least one embodiment of the driving circuit shown,

[0754] The second gating circuit includes a second first transistor T2-1 and a second second transistor T2-2;

[0755] The gate of the second first transistor T2-1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the second first transistor T2-1 is electrically connected to the second first node N2-1, and the drain of the second first transistor T2-1 is electrically connected to the drain of the second second transistor T2-2.

[0756] The gate of the second transistor T2-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second transistor T2-2 is electrically connected to the gating input terminal VCT.

[0757] The second sustaining control circuit includes a second third transistor T2-3 and a second fourth transistor T2-4;

[0758] The gate of the second third transistor T2-3 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the second third transistor T2-3 is electrically connected to the second first node N2-1, and the drain of the second third transistor T2-3 is electrically connected to the second fourth node N2-4.

[0759] The gate of the second fourth transistor T2-4 is electrically connected to the first clock signal terminal GCK, the source of the second fourth transistor T2-4 is electrically connected to the second fourth node N2-4, and the drain of the second fourth transistor T2-4 is electrically connected to the second first node N2-1.

[0760] The second first inverter includes a second fifth transistor T2-5 and a second sixth transistor T2-6, and the second second inverter includes a second seventh transistor T2-7 and a second eighth transistor T2-8;

[0761] The gate of the second fifth transistor T2-5 is electrically connected to the second first node N2-1, the source of the second fifth transistor T2-5 is electrically connected to the high voltage terminal VGH, and the drain of the second fifth transistor T2-5 is electrically connected to the second third node N2-3.

[0762] The gate of the second sixth transistor T2-6 is electrically connected to the second first node N2-1, the source of the second sixth transistor T2-6 is electrically connected to the second third node N2-3, and the drain of the second sixth transistor T2-6 is electrically connected to the low voltage terminal VGL.

[0763] The gate of the second seventh transistor T2-7 is electrically connected to the second third node N2-3, the source of the second seventh transistor T2-7 is electrically connected to the high voltage terminal VGH, and the drain of the second seventh transistor T2-7 is electrically connected to the second fourth node N2-4.

[0764] The gate of the second eighth transistor T2-8 is electrically connected to the second third node N2-3, the source of the second eighth transistor T2-8 is electrically connected to the second fourth node N2-4, and the drain of the second eighth transistor T2-8 is electrically connected to the low voltage terminal VGL.

[0765] The second initialization circuit includes a second ninth transistor T2-9, and the second first voltage sustaining circuit includes a second first capacitor C2-1;

[0766] The gate of the second ninth transistor T2-9 is electrically connected to the initial control terminal NCX, the source of the second ninth transistor T2-9 is electrically connected to the high voltage terminal VGH, and the drain of the second ninth transistor T2-9 is electrically connected to the second first node N2-1.

[0767] The first terminal of the second first capacitor C2-1 is electrically connected to the second first node N2-1, and the second terminal of the second first capacitor C2-1 is electrically connected to the low voltage terminal VGL.

[0768] The second output control circuit includes a second tenth transistor T2-10, a second eleventh transistor T2-11, a second twelfth transistor T2-12, and a second thirteenth transistor T2-13;

[0769] The gate of the second tenth transistor T2-10 is electrically connected to the Nth stage drive signal output terminal NS(N), the source of the second tenth transistor T2-10 is electrically connected to the high voltage terminal VGH, and the drain of the second tenth transistor T2-10 is electrically connected to the second fifth node N2-5.

[0770] The gate of the second eleventh transistor T2-11 is electrically connected to the second first node N2-1, the source of the second eleventh transistor T2-11 is electrically connected to the high voltage terminal VGH, and the drain of the second eleventh transistor T2-11 is electrically connected to the second fifth node N2-5.

[0771] The gate of the second twelfth transistor T2-12 is electrically connected to the Nth stage drive signal output terminal NS(N), the source of the second twelfth transistor T2-12 is electrically connected to the second fifth node N2-5, and the drain of the second twelfth transistor T2-12 is electrically connected to the second sixth node N2-6.

[0772] The gate of the second thirteenth transistor T2-13 is electrically connected to the second first node N2-1, the source of the second thirteenth transistor T2-13 is electrically connected to the second sixth node N2-6, and the drain of the second thirteenth transistor T2-13 is electrically connected to the low voltage terminal VGL.

[0773] The second output circuit includes a second fourteenth transistor T2-14 and a second fifteenth transistor T2-15;

[0774] The gate of the second fourteenth transistor T2-14 is electrically connected to the second fifth node N2-5, the source of the second fourteenth transistor T2-14 is electrically connected to the high voltage terminal VGH, and the drain of the second fourteenth transistor T2-14 is electrically connected to the output drive terminal NO(N).

[0775] The gate of the second fifteenth transistor T2-15 is electrically connected to the second fifth node N2-5, the source of the second fifteenth transistor T2-15 is electrically connected to the output drive terminal NO(N), and the drain of the second fifteenth transistor T2-15 is electrically connected to the low voltage terminal VGL.

[0776] The second first drive output circuit includes a second sixteenth transistor T2-16 and a second second capacitor C2-2;

[0777] The gate of the second sixteenth transistor T2-16 is electrically connected to the first control node NC2-1, the source of the second sixteenth transistor T2-16 is electrically connected to the high voltage terminal VGH, and the drain of the second sixteenth transistor T2-16 is electrically connected to the Nth stage drive signal output terminal NS(N).

[0778] The first terminal of the second capacitor C2-2 is electrically connected to the first control node NC2-1, and the second terminal of the second capacitor C2-2 is electrically connected to the high voltage terminal VGH.

[0779] The second second drive output circuit includes a second seventeenth transistor T2-17 and a second third capacitor C2-3;

[0780] The gate of the second seventeenth transistor T2-17 is electrically connected to the second control node NC2-2, the source of the second seventeenth transistor T2-17 is electrically connected to the Nth stage drive signal output terminal NS(N), and the drain of the second seventeenth transistor T2-17 is electrically connected to the low voltage terminal VGL.

[0781] The first terminal of the second third capacitor C2-3 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the second third capacitor C2-3 is electrically connected to the low voltage terminal VGL;

[0782] The second seventh node control circuit includes a second eighteenth transistor T2-18 and a second nineteenth transistor T2-19;

[0783] The gate of the second eighteenth transistor T2-18 is electrically connected to the first clock signal terminal GCK, the source of the second eighteenth transistor T2-18 is electrically connected to the low voltage terminal VGL, and the drain of the second eighteenth transistor T2-18 is electrically connected to the second seventh node N2-7.

[0784] The gate of the second nineteenth transistor T2-19 is electrically connected to the second ninth node N2-9, the source of the second nineteenth transistor T2-19 is electrically connected to the second seventh node N2-7, and the drain of the second nineteenth transistor T2-19 is electrically connected to the first clock signal terminal GCK.

[0785] The second eighth node control circuit includes a second twentieth transistor T2-20;

[0786] The gate of the second twentieth transistor T2-20 is electrically connected to the low voltage terminal VGL, the source of the second twentieth transistor T2-20 is electrically connected to the second seventh node N2-7, and the drain of the second twentieth transistor T2-20 is electrically connected to the second eighth node N2-8.

[0787] The second first control circuit includes a second twenty-first transistor T2-21, a second fourth capacitor C2-4, a second twenty-second transistor T2-22, and a second twenty-third transistor T2-23;

[0788] The gate of the second twenty-first transistor T2-21 is electrically connected to the second eighth node N2-8, the source of the second twenty-first transistor T2-21 is electrically connected to the second clock signal terminal GCB, and the drain of the second twenty-first transistor T2-21 is electrically connected to the second second node N2-2.

[0789] The first terminal of the second fourth capacitor C2-4 is electrically connected to the second eighth node N2-8, and the second terminal of the second fourth capacitor C2-4 is electrically connected to the second second node N2-2;

[0790] The gate of the second twentieth-second transistor T2-22 is electrically connected to the second clock signal terminal GCB, the source of the second twentieth-second transistor T2-22 is electrically connected to the second second node N2-2, and the drain of the second twentieth-second transistor T2-22 is electrically connected to the first control node NC2-1.

[0791] The gate of the second twenty-third transistor T2-23 is electrically connected to the second ninth node N2-9, the source of the second twenty-third transistor T2-23 is electrically connected to the first control node NC2-1, and the drain of the second twenty-third transistor T2-23 is electrically connected to the high voltage terminal VGH.

[0792] The second ninth node control circuit includes a second twenty-fourth transistor T2-24 and a second twenty-fifth transistor T2-25;

[0793] The gate of the second twenty-fourth transistor T2-24 is electrically connected to the first clock signal terminal GCK, the source of the second twenty-fourth transistor T2-24 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second twenty-fourth transistor T2-24 is electrically connected to the second ninth node N2-9.

[0794] The gate of the second 25th transistor T2-25 is electrically connected to the initial control terminal NCX, the source of the second 25th transistor T2-25 is electrically connected to the high voltage terminal VGH, and the drain of the second 25th transistor T2-25 is electrically connected to the second 9th node N2-9.

[0795] The second tenth node control circuit includes a second twenty-sixth transistor T2-26;

[0796] The gate of the second twenty-sixth transistor T2-26 is electrically connected to the first clock signal terminal GCK, the source of the second twenty-sixth transistor T2-26 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second twenty-sixth transistor T2-26 is electrically connected to the second tenth node N2-10.

[0797] The second eleventh node control circuit includes the second twenty-seventh transistor T2-27, the second twenty-eighth transistor T2-28, the second twenty-ninth transistor T2-29, and the second fifth capacitor C2-5;

[0798] The gate of the second twenty-seventh transistor T2-27 is electrically connected to the low voltage terminal VGL, the source of the second twenty-seventh transistor T2-27 is electrically connected to the second tenth node N2-10, and the drain of the second twenty-seventh transistor T2-27 is electrically connected to the second eleventh node N2-11.

[0799] The gate of the second twenty-eighth transistor T2-28 is electrically connected to the second seventh node N2-7, the source of the second twenty-eighth transistor T2-28 is electrically connected to the high voltage terminal VGH, and the drain of the second twenty-eighth transistor T2-28 is electrically connected to the second twelfth node N2-12.

[0800] The gate of the second twenty-ninth transistor T2-29 is electrically connected to the second eleventh node N2-11, the source of the second twenty-ninth transistor T2-29 is electrically connected to the second twelfth node N2-12, and the drain of the second twenty-ninth transistor T2-29 is electrically connected to the second clock signal terminal GCB.

[0801] The first terminal of the second fifth capacitor C2-5 is electrically connected to the second twelfth node N2-12, and the second terminal of the second fifth capacitor C2-5 is electrically connected to the second eleventh node N2-11.

[0802] The second control circuit includes a second thirtieth transistor and a second thirty-first transistor;

[0803] The gate of the second thirtieth transistor T2-30 and the source of the second thirtieth transistor T2-31 are both electrically connected to the second eleventh node N2-11, and the drain of the second thirtieth transistor T2-31 is electrically connected to the second control node NC2-2.

[0804] The gate of the second thirty-first transistor T2-31 is electrically connected to the low voltage terminal VGL, the source of the second thirty-first transistor T2-31 is electrically connected to the second ninth node N2-9, and the drain of the second thirty-first transistor T2-31 is electrically connected to the second control node NC2-2.

[0805] exist Figure 39 In the diagram, the node labeled N2-13 is the second thirteenth node.

[0806] exist Figure 39 In at least one embodiment of the driving circuit shown, T2-1 is an n-type transistor, T2-2 is a p-type transistor, T2-3 is a p-type transistor, T2-4 is an n-type transistor, T2-5 is a p-type transistor, T2-6 is an n-type transistor, T2-7 is a p-type transistor, T2-8 is an n-type transistor, T2-9 is a p-type transistor, T2-10 and T2-11 are n-type transistors, T2-12 and T2-13 are n-type transistors, T2-14 is a p-type transistor, T2-15 is an n-type transistor, and T2-16-T2-31 are all p-type transistors.

[0807] In at least one embodiment of this disclosure, the structure of the second drive signal generation circuit is not limited to that shown below. Figure 39 As shown, the second drive signal generation circuit can be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0808] This disclosure Figure 39 At least one embodiment of the driving circuit shown, when in operation,

[0809] In the first stage, when NS(N-1) outputs a low voltage signal, GCK outputs a low voltage signal, and GCB provides a high voltage signal, T2-24 and T2-26 are turned on, the potentials of N2-9 and N2-10 are low, T2-27 and T2-31 are turned on, ensuring that the potentials of NC2-2 and N2-11 are low, T2-17 is turned on, and NS(N) outputs a low voltage signal; the potential of N2-11 is low to ensure that T2-29 is turned on, the potential of N2-9 is low to turn on T2-19, T2-18 is turned on, pulling the potentials of N2-7 and N2-8 low, turning on T2-21, GCB writes a high voltage signal to N2-2, the potential of N2-9 is low to turn on T2-23, pulling the potential of NC2-1 high to ensure that T2-16 is turned off;

[0810] In the second stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output by GCK jumps from low voltage to high voltage, T2-24 and T2-26 are turned off, the potential of N2-9 is low voltage, T2-19 is turned on, T2-18 is turned off, T2-20 is turned on, the potentials of N2-7 and N2-8 are high voltage, T2-21 is turned off, the potential of N2-2 remains high voltage, GCB outputs a low voltage signal, T2-22 is turned on, the potential of NC2-1 remains high voltage, T2... -16 is turned off; at the same time, the potential of N2-11 is maintained at a low voltage, T2-29 is turned on, GCB writes a low voltage signal to N2-12, and C2-5 pulls the potential of N2-11 down to an even lower voltage (5V~10V lower than the voltage value of the low voltage signal provided by GCB), T2-30 is turned on, and the low voltage signal is written to NC2-2 (the potential of NC2-2 is 3~8V lower than the voltage value of the low voltage signal provided by GCB), and T2-17 is fully turned on to ensure that NS(N) outputs a low voltage signal;

[0811] In the third stage, NS(N-1) outputs a high voltage signal, GCK outputs a low voltage signal, GCB outputs a high voltage signal, T2-24 and T2-26 are turned on, controlling the potentials of N2-9 and N2-10 to be high voltage, T2-27 and T2-31 are turned on, the potentials of NC2-2 and N2-11 are high voltage, and T2-17 is turned off; the potential of N2-11 is high voltage, T2-29 is turned off, the potential of N2-9 is high voltage, T2-19 is turned off, T2-18 is turned on, T2-20 is turned on, pulling the potentials of N2-7 and N2-8 low, T2-21 is turned on, GCB writes a high voltage signal to N2-2, T2-22 is turned off, the potential of N2-9 is high voltage, T2-23 is turned off, the potential of NC2-1 is maintained at high voltage, ensuring that T2-16 is turned off;

[0812] In the fourth stage, NS(N-1) outputs a high voltage signal, the potential of the first clock signal output by GCK jumps from low voltage to high voltage, GCB outputs a low voltage signal, T2-24 and T2-26 are turned off, the potential of N2-9 is high voltage, T2-19 is turned off, T2-18 is turned off, T2-20 is turned on, the potentials of N2-7 and N2-8 remain low voltage, T2-21 and T2-22 are turned on, the potentials of N2-2 and NC2-1 are low voltage, T2-16 is turned on, and NS(N) outputs a high voltage signal; at the same time, the potential of N2-11 is high voltage, T2-29 is turned off, and the potential of N2-12 remains unchanged to ensure that the potential of N2-11 is high voltage;

[0813] In the fifth stage, the potential of the N-1th stage drive signal output by NS(N-1) jumps from high voltage to low voltage, GCK outputs a high voltage signal, GCB outputs a low voltage signal, T2-24 and T2-26 are turned off, the potentials of N2-9 and N2-10 are maintained at high voltage, and the potentials of the remaining nodes remain unchanged, ensuring that NS(N) outputs a high voltage signal.

[0814] In the sixth stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output by GCK jumps from high voltage to low voltage, GCB outputs a high voltage signal, T2-24 and T2-26 are turned on, the potentials of N2-9 and N2-10 are low voltage, T2-27 and T2-31 are turned on, ensuring that the potentials of NC2-2 and N2-11 are low voltage, T2-17 is turned on, NS(N) outputs a low voltage signal; the potential of N2-11 is low voltage, ensuring that T2-29 is turned on, the potential of N2-9 is low voltage, T2-19, T2-18, and T2-20 are turned on, pulling the potentials of N2-7 and N2-8 low, T2-21 is turned on, GCB writes a high voltage signal to N2-2, the potential of N2-9 is low voltage, T2-23 is turned on, pulling the potential of NC2-1 high voltage, ensuring that T2-16 is turned off.

[0815] Optionally, at the start of display (i.e., when the display device is powered on), during the power-on phase before the first stage, NCX outputs a low-voltage signal, T2-9 turns on to control the potential of N2-1 to be high, T2-25 turns on, the potential of N2-9 is high, and T2-19 turns off. When GCK provides a low-voltage signal, the potential of N2-7 is low, T2-20 turns on, the potential of N2-8 is low, and T2-21 turns on to control the connection between N2-2 and GCB. When GCB provides a low voltage signal, T2-22 turns on, NC2-1 is at a low voltage, T2-16 turns on, and NS(N) outputs a high voltage signal; when T2-12 and T2-13 turn on, N2-5 is at a low voltage, T2-14 turns on, and NO(N) outputs a high voltage signal, all pixel circuits in the effective display area, including the second display control transistor M2, are turned on, clearing the residual charge in the storage capacitor Cst and improving the poor screen flickering at startup.

[0816] Subsequently, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, T2-1 and T2-2 are turned on.

[0817] When VCT provides a low voltage signal, the potential of N2-1 is a low voltage signal, and C2-1 maintains the potential of N2-1; T2-11 is turned on, T2-10 is turned on, the potential of N2-5 is a high voltage, T2-15 is turned on, and NO(N) outputs a low voltage signal.

[0818] When VCT provides a high voltage signal, the potential of N2-1 is a high voltage signal, C2-1 maintains the potential of N2-1, T2-11 is turned off, T2-10 is turned on, the potential of N2-5 is high voltage, T2-15 is turned on, and NO(N) outputs a low voltage signal.

[0819] Subsequently, during the Nth stage of drive signal provision, NS(N) outputs a high-voltage signal.

[0820] When the potential of N2-1 is low, T2-10 is turned off and T2-11 is turned on. When the potential of N2-5 is high, T2-15 is turned on, and NO(N) outputs a low voltage signal.

[0821] When the potential of N2-1 is high voltage, T2-10 is off, T2-11 is off, and T2-12 and T2-13 are on. When the potential of N2-5 is low voltage, T2-14 is on, and NO(N) outputs a high voltage signal.

[0822] After the Nth stage drive signal is provided, NS(N) outputs a low voltage signal.

[0823] When the potential of N2-1 is a low voltage signal, T2-10 and T2-11 are turned on, the potential of N2-5 is a high voltage, and NO(N) outputs a low voltage signal.

[0824] When the potential of N2-1 is a high voltage signal, T2-10 is turned on and T2-11 is turned off. When the potential of N2-5 is a high voltage, NO(N) outputs a low voltage signal.

[0825] This disclosure Figure 39 In at least one embodiment of the driving circuit shown, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, T2-1 and T2-2 are turned on. By simultaneously selecting the two signals, the state of the selected input signal within a high-low frequency switching cycle can be obtained.

[0826] This disclosure Figure 39 In at least one embodiment of the driving circuit shown, since the p-type transistor has a threshold voltage loss when transmitting low voltage and the n-type transistor has a threshold voltage loss when transmitting high voltage, the absolute value of the potential of N2-1 will be lower. The absolute value of the potential of N2-1 can be increased by controlling the second first inverter and the second second inverter, thereby better controlling the corresponding transistor in the second output circuit to turn on or off. The second holding control circuit controls the disconnection between N2-1 and N2-4 when T2-1 and T2-2 are turned on, so as not to affect the writing of the potential of N2-1.

[0827] Figure 40 yes Figure 39 The timing diagram of at least one embodiment of the driving circuit shown;

[0828] Figure 41 yes Figure 39 Simulation timing diagram of at least one embodiment of the driving circuit shown.

[0829] This disclosure Figure 42 At least one embodiment of the driving circuit shown is consistent with this disclosure. Figure 39 The difference in at least one embodiment of the driving circuit shown is as follows: a second second voltage sustaining circuit is not provided (that is, T2-3-T2-8 is not provided).

[0830] This disclosure Figure 43 At least one embodiment of the driving circuit shown is consistent with this disclosure. Figure 39 The difference in at least one embodiment of the driving circuit shown is as follows: N2-4 is electrically connected to the gate of T2-11 and the gate of T2-13.

[0831] This disclosure Figure 43In at least one embodiment of the driving circuit shown, when in operation, because the p-type transistor has a threshold voltage loss when transmitting low voltage and the n-type transistor has a threshold voltage loss when transmitting high voltage, the absolute value of the potential of N2-1 will be low. Therefore, the absolute value of the potential of N2-4 can be increased by controlling the second first inverter and the second second inverter, thereby better controlling the corresponding transistor in the second output circuit to turn on or off. The second holding control circuit controls the disconnection between N2-1 and N2-4 when T2-1 and T2-2 are turned on, so as not to affect the writing of the potential of N2-1.

[0832] like Figure 44 As shown, the driving circuit described in this embodiment includes a third driving signal generation circuit 310, a third gating circuit 311, a third output control circuit 312, a third output circuit 313, and a third voltage control circuit 314.

[0833] The third drive signal generation circuit 310 is electrically connected to the third first control node NC3-1, the third second control node NC3-2 and the Nth drive signal output terminal NS(N), respectively, and is used to generate and output the Nth drive signal through the Nth drive signal output terminal NS(N) under the control of the potential of the third first control node NC3-1 and the potential of the third second control node NC3-2.

[0834] The third gating circuit 311 is electrically connected to the third first node N3-1, the gating input terminal VCT, and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the third first node N3-1 under the control of the gating control signal provided by the gating control terminal CX.

[0835] The third output control circuit 312 is electrically connected to the third first node N3-1, the third first control node NC3-1, and the third second node N3-2, respectively, and is used to control the connection between the third first control node NC3-1 and the third second node N3-2 under the control of the potential of the third first node N3-1;

[0836] The third voltage control circuit 314 is electrically connected to the third first node N3-1 and the third second node N3-2 respectively, and is used to control the potential of the third second node N3-2 according to the potential of the third first node N3-1;

[0837] The third output circuit 313 is electrically connected to the third second node N3-2, the third third control node NC3-3, the first voltage terminal V1, the second voltage terminal V2, and the output drive terminal NO(N), respectively. It is used to control the output drive terminal NO(N) to be connected with the first voltage terminal V1 under the control of the potential of the third second node N3-2, and to control the output drive terminal NO(N) to be connected with the second voltage terminal V2 under the control of the potential of the third third control node NC3-3.

[0838] The third second control node NC3-2 and the third third control node NC3-3 are different nodes; N is a positive integer.

[0839] This disclosure Figure 44 In the embodiment of the driving circuit shown, during operation, the third driving signal generation circuit 310 generates and outputs the Nth-level driving signal through the Nth-level driving signal output terminal NS(N); the third gating circuit 311, under the control of the gating control signal, writes the gating input signal into the third first node N3-1; the third output control circuit 312, under the control of the potential of the third first node N3-1, controls the connection between the third first control node NC3-1 and the third second node N3-2; the third voltage control circuit 314 controls the potential of the third second node N3-2 according to the potential of the third first node N3-1; the third output circuit 313, under the control of the potential of the third second node N3-2, controls the connection between the output driving terminal NO(N) and the first voltage terminal V1, and under the control of the potential of the third third control node NC3-3, controls the connection between the output driving terminal NO(N) and the second voltage terminal V2.

[0840] Optionally, the first voltage terminal can be a high voltage terminal, but is not limited thereto.

[0841] This disclosure Figure 44 The embodiment of the driving circuit shown can be the Nth stage driving circuit.

[0842] This disclosure Figure 44 The illustrated driving circuit embodiment, when in operation, within one frame time,

[0843] Before the Nth stage of driving signal provision, the third gating circuit 311, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT into the third first node N3-1;

[0844] When the strobe input signal is a high voltage signal, during the Nth stage of driving signal provision, the Nth stage driving signal output terminal NS(N) outputs a high voltage signal, the potential of the third first node N3-1 is high voltage, the third output control circuit 312 controls the third first control node NC3-1 to disconnect from the third second node N3-2 under the control of the potential of the third first node N3-1, the third voltage control circuit 314 controls the potential of the third second node N3-2 to be high voltage according to the potential of the third first node N3-1, and the third output circuit controls the output driving terminal NO(N) to maintain a low voltage signal, which can control the corresponding row pixel circuit not to update the pixel voltage;

[0845] When the strobe input signal is a low voltage signal, during the Nth stage of driving signal provision, the Nth stage driving signal output terminal NS(N) outputs a high voltage signal, and the potential of the third first node N3-1 is low voltage. Under the control of the potential of the third first node N3-1, the third output control circuit 312 controls the connection between the third first control node NC3-1 and the third second node N3-2, so that the potential of the third second node N3-2 is low voltage. Under the control of the potential of the third second node N3-2, the third output circuit 313 controls the connection between the output driving terminal NO(N) and the first voltage terminal V1, so that NO(N) outputs a high voltage signal, which can control the corresponding row pixel circuit to update the pixel voltage.

[0846] This disclosure embodiment can update a portion of the display screen by controlling the gating input signal provided by the gating input terminal VCT, thereby reducing power consumption, or achieve ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and notebook computers by updating the display screen partially.

[0847] Optionally, the third output control circuit includes a third transistor;

[0848] The gate of the third transistor is electrically connected to the third first node, the first electrode of the third transistor is electrically connected to the third first control node, and the second electrode of the third transistor is electrically connected to the third second node.

[0849] Optionally, the third voltage control circuit includes a third first capacitor;

[0850] The first terminal of the third first capacitor is electrically connected to the third first node, and the second terminal of the third first capacitor is electrically connected to the third second node.

[0851] The driving circuit described in at least one embodiment of this disclosure further includes a third second node control circuit;

[0852] The third second node control circuit is electrically connected to the third third control node, the third second node and the first voltage terminal respectively, and is used to control the connection between the third second node and the first voltage terminal under the control of the potential of the third third control node.

[0853] In a specific implementation, the driving circuit may further include a third second node control circuit;

[0854] The third second node control circuit controls the connection between the third second node and the first voltage terminal under the control of the potential of the third third control node.

[0855] like Figure 45 As shown, in Figure 44 Based on the embodiment of the driving circuit shown, the driving circuit further includes a third second node control circuit 320;

[0856] The third second node control circuit 320 is electrically connected to the third third control node NC3-3, the third second node N3-2 and the first voltage terminal V1, respectively, and is used to control the connection between the third second node N3-2 and the first voltage terminal V1 under the control of the potential of the third third control node NC3-3.

[0857] Figure 45 In at least one embodiment of the driving circuit shown, when the potential of the third control node NC3-3 is an effective voltage, the potential of the third second node N3-2 can be a first voltage.

[0858] Optionally, the third second node control circuit includes a third fourth transistor;

[0859] The gate of the third fourth transistor is electrically connected to the third third control node, the first terminal of the third fourth transistor is electrically connected to the third second node, and the second terminal of the third fourth transistor is electrically connected to the first voltage terminal.

[0860] Optionally, the third output circuit includes a third fifth transistor, a third sixth transistor, and a third second capacitor;

[0861] The gate of the third fifth transistor is electrically connected to the third second node, the first terminal of the third fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the third fifth transistor is electrically connected to the output drive terminal.

[0862] The gate of the third sixth transistor is electrically connected to the third third control node, the first terminal of the third sixth transistor is electrically connected to the output drive terminal, and the second terminal of the third sixth transistor is electrically connected to the second voltage terminal.

[0863] The first terminal of the third second capacitor is electrically connected to the third second node, and the second terminal of the third second capacitor is electrically connected to the first voltage terminal.

[0864] The driving circuit described in at least one embodiment of this disclosure further includes a third initialization circuit;

[0865] The third initialization circuit is electrically connected to the initial control terminal, the second voltage terminal, and the third first node, respectively, and is used to control the connection between the third first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0866] In a specific implementation, the driving circuit may further include a third initialization circuit. When the display device is powered on, the third initialization circuit, under the control of the initial control signal, controls the connection between the third first node and the second voltage terminal to control the potential of the third first node to be the second voltage. The third output control circuit, under the control of the potential of the third first node, controls the connection between the third first control node and the third second node.

[0867] In at least one embodiment of this disclosure, the driving circuit further includes a third first node control circuit;

[0868] The third first node control circuit is electrically connected to the third fourth node, the second voltage terminal, and the third first node, respectively, and is used to control the connection between the third first node and the second voltage terminal under the control of the potential of the third fourth node.

[0869] In a specific implementation, the driving circuit may further include a third first node control circuit. Under the control of the potential of the third fourth node, the third first node control circuit controls the connection between the third first node and the second voltage terminal. After the Nth stage of driving signal provision, when the potential of the third fourth node is an effective voltage, the third first node control circuit controls the connection between the third first node and the second voltage terminal so that the potential of the third first node is the second voltage. Under the control of the potential of the third first node, the third output control circuit controls the connection between the third first control node and the third second node.

[0870] In at least one embodiment of this disclosure, when the transistor included in the third first node control circuit is a p-type transistor, the effective voltage can be a low voltage; when the transistor included in the third first node control circuit is an n-type transistor, the effective voltage can be a high voltage.

[0871] like Figure 46 As shown, in Figure 45 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a third initialization circuit 321 and a third first node control circuit 322;

[0872] The third initialization circuit 321 is electrically connected to the initial control terminal NCX, the third first node N3-1 and the second voltage terminal V2 respectively, and is used to control the connection between the third first node N3-1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX.

[0873] The third first node control circuit 322 is electrically connected to the third fourth node N3-4, the third first node N3-1, and the second voltage terminal V2, respectively, and is used to control the connection between the third first node N3-1 and the second voltage terminal V2 under the control of the potential of the third fourth node N3-4.

[0874] Optionally, the third initialization circuit includes a third seventh transistor;

[0875] The gate of the third seventh transistor is electrically connected to the initial control terminal, the first terminal of the third seventh transistor is electrically connected to the third first node, and the second terminal of the third seventh transistor is electrically connected to the second voltage terminal.

[0876] Optionally, the third first node control circuit includes a third eighth transistor;

[0877] The gate of the third eighth transistor is electrically connected to the third fourth node, the first terminal of the third eighth transistor is electrically connected to the third first node, and the second terminal of the third eighth transistor is electrically connected to the second voltage terminal.

[0878] The driving circuit described in at least one embodiment of this disclosure further includes a third control node control circuit;

[0879] The third control node control circuit is electrically connected to the third first node, the third fifth node, the third second control node, the third third control node, and the third sixth node, respectively. It is used to control the connection between the third fifth node and the third third control node under the control of the potential of the third first node, control the connection between the third second control node and the third sixth node under the control of the potential of the third sixth node, and control the connection between the third sixth node and the third third control node.

[0880] In a specific implementation, the driving circuit may include a third control node control circuit, which controls the potential of the third control node under the control of the potential of the third first node and the potential of the third sixth node.

[0881] like Figure 47 As shown, in Figure 46 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a third control node control circuit 330;

[0882] The third control node control circuit 330 is electrically connected to the third first node N3-1, the third fifth node N3-5, the third second control node NC3-2, the third third control node NC3-3, and the third sixth node N3-6, respectively. It is used to control the connection between the third fifth node N3-5 and the third third control node NC3-3 under the control of the potential of the third first node N3-1, control the connection between the third second control node NC3-2 and the third sixth node N3-6 under the control of the potential of the third sixth node N3-6, and control the connection between the third sixth node N3-6 and the third third control node NC3-3.

[0883] Optionally, the third control node control circuit includes a third ninth transistor, a third tenth transistor, and a third eleventh transistor;

[0884] The gate of the third ninth transistor is electrically connected to the third first node, the first terminal of the third ninth transistor is electrically connected to the third fifth node, and the second terminal of the third ninth transistor is electrically connected to the third third control node.

[0885] The gate and the second terminal of the third tenth transistor are both electrically connected to the third sixth node, and the first terminal of the third tenth transistor is electrically connected to the third second control node.

[0886] The gate of the third eleventh transistor and the first terminal of the third eleventh transistor are both electrically connected to the third sixth node, and the second terminal of the third eleventh transistor is electrically connected to the third third control node.

[0887] In at least one embodiment of this disclosure, the third drive signal generation circuit includes a third first drive output circuit, a third second drive output circuit, a third first control node control circuit, and a third second control node control circuit.

[0888] The third first control node control circuit is used to control the potential of the third first control node;

[0889] The third second control node control circuit is used to control the potential of the third second control node;

[0890] The third first drive output circuit is electrically connected to the third first control node, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the potential of the third first control node;

[0891] The third second drive output circuit is electrically connected to the third second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the third second control node.

[0892] like Figure 48 As shown, in Figure 47 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a third first control node control circuit 331, a third second control node control circuit 332, a third first drive output circuit 333, and a third second drive output circuit 334.

[0893] The third first control node control circuit 331 is electrically connected to the third first control node NC3-1 and is used to control the potential of the third first control node NC3-1.

[0894] The third second control node control circuit 332 is electrically connected to the third second control node NC3-2 and is used to control the potential of the third second control node NC3-2.

[0895] The third first drive output circuit 333 is electrically connected to the third first control node NC3-1, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the potential of the third first control node NC3-1.

[0896] The third second drive output circuit 334 is electrically connected to the third second control node NC3-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 under the control of the potential of the third second control node NC3-2.

[0897] In at least one embodiment of this disclosure, the third first control node control circuit includes a third seventh node control circuit, a third eighth node control circuit, a third third node control circuit, and a third first control circuit.

[0898] The third seventh node control circuit is electrically connected to the third seventh node, the second voltage terminal, the first clock signal terminal, and the third fifth node, respectively. It is used to control the connection between the third seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third seventh node and the first clock signal terminal under the control of the potential of the third fifth node.

[0899] The third eighth node control circuit is electrically connected to the second voltage terminal, the third seventh node, and the third eighth node respectively, and is used to control the connection between the third seventh node and the third eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0900] The third third node control circuit is electrically connected to the third eighth node, the second clock signal terminal, and the third third node respectively. It is used to control the three nodes to be electrically connected to the second clock signal terminal under the control of the potential of the third eighth node, and to control the potential of the third third node according to the potential of the third eighth node.

[0901] The third first control circuit is electrically connected to the second clock signal terminal, the third third node, the third first control node, the third fifth node, and the first voltage terminal, respectively. It is used to control the connection between the third third node and the third first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the third first control node and the first voltage terminal under the control of the potential of the third fifth node.

[0902] In a specific implementation, the third first control node control circuit may include a third seventh node control circuit, a third eighth node control circuit, a third third node control circuit, and a third first control circuit. The third seventh node control circuit controls the potential of the third seventh node under the control of the first clock signal and the potential of the third fifth node. The third eighth node control circuit controls the connection between the third seventh node and the third eighth node under the control of the second voltage signal. The third third node control circuit controls the electrical connection between the third third node and the second clock signal terminal under the control of the potential of the third eighth node, and controls the potential of the third third node according to the potential of the third eighth node. The third first control circuit controls the connection between the third third node and the third first control node under the control of the second clock signal, and controls the connection between the third first control node and the first voltage terminal under the control of the potential of the third fifth node.

[0903] In at least one embodiment of this disclosure, the third second control node control circuit includes a third sixth node control circuit, a third fifth node control circuit, a third ninth node control circuit, a third fourth node control circuit, and a third second control circuit;

[0904] The third sixth node control circuit is electrically connected to the second voltage terminal, the third ninth node, the third sixth node, and the third fourth node, respectively, and is used to control the connection between the third ninth node and the third sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the third sixth node according to the potential of the third fourth node.

[0905] The third fifth node control circuit is electrically connected to the N-1 level drive signal output terminal, the first clock signal terminal, the third fifth node, the initial control terminal, and the first voltage terminal, respectively. It is used to control the connection between the third fifth node and the N-1 level drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third fifth node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0906] The third ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal and the third ninth node respectively, and is used to control the connection between the third ninth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal.

[0907] The third fourth node control circuit is electrically connected to the third seventh node, the first voltage terminal, the third fourth node, the second clock signal terminal, and the third sixth node, respectively. It is used to control the connection between the third fourth node and the first voltage terminal under the control of the potential of the third seventh node, and to control the connection between the third fourth node and the second clock signal terminal under the control of the potential of the third sixth node.

[0908] The third second control circuit is electrically connected to the second voltage terminal, the third fifth node, and the third second control node, respectively, and is used to control the connection between the third fifth node and the third second control node under the control of the second voltage signal provided by the second voltage terminal.

[0909] In specific implementation, the third second control node control circuit may include a third sixth node control circuit, a third fifth node control circuit, a third ninth node control circuit, a third fourth node control circuit, and a third second control circuit; the third fourth node control circuit controls the potential of the third fourth node under the control of the potential of the third seventh node and the potential of the third sixth node; the third sixth node control circuit controls the connection between the third ninth node and the third sixth node under the control of the second voltage signal, and controls the potential of the third sixth node according to the potential of the third fourth node; the third fifth node control circuit controls the third... The fifth node is connected to the output terminal of the (N-1)th stage drive signal. Under the control of the initial control signal, the third fifth node is connected to the first voltage terminal. The third ninth node control circuit, under the control of the first clock signal, controls the third ninth node to be connected to the output terminal of the (N-1)th stage drive signal. The third fourth node control circuit, under the control of the potential of the third seventh node, controls the third fourth node to be connected to the first voltage terminal, and under the control of the potential of the third sixth node, controls the third fourth node to be connected to the second clock signal terminal. The third second control circuit, under the control of the second voltage signal, controls the third fifth node to be connected to the third second control node.

[0910] like Figure 49 As shown, in Figure 48 Based on at least one embodiment of the driving circuit shown, the third first control node control circuit includes a third seventh node control circuit 341, a third eighth node control circuit 342, a third third node control circuit 343, and a third first control circuit 344.

[0911] The third seventh node control circuit 341 is electrically connected to the third seventh node N3-7, the second voltage terminal V2, the first clock signal terminal GCK, and the third fifth node N3-5, respectively. It is used to control the connection between the third seventh node N3-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the third seventh node N3-7 and the first clock signal terminal GCK under the control of the potential of the third fifth node N3-5.

[0912] The third eighth node control circuit 342 is electrically connected to the second voltage terminal V2, the third seventh node N3-7 and the third eighth node N3-8 respectively, and is used to control the connection between the third seventh node N3-7 and the third eighth node N3-8 under the control of the second voltage signal provided by the second voltage terminal V2;

[0913] The third third node control circuit 343 is electrically connected to the third eighth node N3-8, the second clock signal terminal GCB, and the third third node N3-3, respectively. It is used to control the third third node N3-3 to be electrically connected to the second clock signal terminal GCB under the control of the potential of the third eighth node N3-8, and to control the potential of the third third node N3-3 according to the potential of the third eighth node N3-8.

[0914] The third first control circuit 344 is electrically connected to the second clock signal terminal GCB, the third third node N3-3, the third first control node NC3-1, the third fifth node N3-5, and the first voltage terminal V1, respectively. It is used to control the connection between the third third node N3-3 and the third first control node NC3-1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the third first control node NC3-1 and the first voltage terminal V1 under the control of the potential of the third fifth node N3-5.

[0915] The third second control node control circuit includes a third sixth node control circuit 351, a third fifth node control circuit 352, a third ninth node control circuit 353, a third fourth node control circuit 354, and a third second control circuit 355.

[0916] The third sixth node control circuit 351 is electrically connected to the second voltage terminal V2, the third ninth node N3-9, the third sixth node N3-6, and the third fourth node N3-4, respectively. It is used to control the connection between the third ninth node N3-9 and the third sixth node N3-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the third sixth node N3-6 according to the potential of the third fourth node N3-4.

[0917] The third fifth node control circuit 352 is electrically connected to the N-1 stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the third fifth node N3-5, the initial control terminal NCX, and the first voltage terminal V1, respectively. It is used to control the connection between the third fifth node N3-5 and the N-1 stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the third fifth node N3-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0918] The third ninth node control circuit 353 is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1) and the third ninth node N3-9 respectively, and is used to control the connection between the third ninth node N3-9 and the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK.

[0919] The third fourth node control circuit 354 is electrically connected to the third seventh node N3-7, the first voltage terminal V1, the third sixth node N3-6, the third fourth node N3-4, and the second clock signal terminal GCB, respectively. It is used to control the third fourth node N3-4 to be electrically connected to the first voltage terminal V1 under the control of the potential of the third seventh node N3-7, and to control the third fourth node N3-4 to be connected to the second clock signal terminal GCB under the control of the potential of the third sixth node N3-6.

[0920] The third second control circuit 355 is electrically connected to the second voltage terminal V2, the third fifth node N3-5 and the third second control node NC3-2 respectively, and is used to control the connection between the third fifth node N3-5 and the third second control node NC3-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0921] Optionally, the third seventh node control circuit includes a third twelfth transistor and a third thirteenth transistor, the third eighth node control circuit includes a third fourteenth transistor, the third third node control circuit includes a third fifteenth transistor and a third third capacitor, and the third first control circuit includes a third sixteenth transistor and a third seventeenth transistor.

[0922] The gate of the third twelfth transistor is electrically connected to the first clock signal terminal, the first terminal of the third twelfth transistor is electrically connected to the second voltage terminal, and the second terminal of the third twelfth transistor is electrically connected to the third seventh node.

[0923] The gate of the third thirteenth transistor is electrically connected to the third fifth node, the first terminal of the third thirteenth transistor is electrically connected to the third seventh node, and the second terminal of the third thirteenth transistor is electrically connected to the first clock signal terminal.

[0924] The gate of the third fourteenth transistor is electrically connected to the second voltage terminal, the first terminal of the third fourteenth transistor is electrically connected to the third seventh node, and the second terminal of the third fourteenth transistor is electrically connected to the third eighth node.

[0925] The gate of the third fifteenth transistor is electrically connected to the third eighth node, the first terminal of the third fifteenth transistor is electrically connected to the second clock signal terminal, and the second terminal of the third fifteenth transistor is electrically connected to the third third node.

[0926] The gate of the third sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the third sixteenth transistor is electrically connected to the third third node, and the second terminal of the third sixteenth transistor is electrically connected to the third first control node.

[0927] The gate of the third seventeenth transistor is electrically connected to the third fifth node, the first terminal of the third seventeenth transistor is electrically connected to the third first control node, and the second terminal of the third seventeenth transistor is electrically connected to the first voltage terminal.

[0928] Optionally, the third sixth node control circuit includes a third eighteenth transistor and a third fourth capacitor, the third fifth node control circuit includes a third nineteenth transistor and a twentyth transistor, the third ninth node control circuit includes a third twenty-first transistor, the third fourth node control circuit includes a third twenty-second transistor and a third twenty-third transistor, and the third second control circuit includes a third twenty-fourth transistor.

[0929] The gate of the third eighteenth transistor is electrically connected to the second voltage terminal, the first terminal of the third eighteenth transistor is electrically connected to the third ninth node, and the second terminal of the third eighteenth transistor is electrically connected to the third sixth node.

[0930] The first terminal of the third fourth capacitor is electrically connected to the third fourth node, and the second terminal of the third fourth capacitor is electrically connected to the third sixth node.

[0931] The gate of the third nineteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the third nineteenth transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the third nineteenth transistor is electrically connected to the third fifth node.

[0932] The gate of the twentieth transistor is electrically connected to the initial control terminal, the first terminal of the twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the third fifth node.

[0933] The gate of the third twenty-first transistor is electrically connected to the first clock signal terminal, the first terminal of the third twenty-first transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the third twenty-first transistor is electrically connected to the third ninth node.

[0934] The gate of the third twenty-second transistor is electrically connected to the third seventh node, the first terminal of the third twenty-second transistor is electrically connected to the first voltage terminal, and the second terminal of the third twenty-second transistor is electrically connected to the third fourth node.

[0935] The gate of the third twenty-third transistor is electrically connected to the third sixth node, the first terminal of the third twenty-third transistor is electrically connected to the third fourth node, and the second terminal of the third twenty-third transistor is electrically connected to the second clock signal terminal.

[0936] The gate of the third twenty-fourth transistor is electrically connected to the second voltage terminal, the first terminal of the third twenty-fourth transistor is electrically connected to the third ninth node, and the second terminal of the third twenty-fourth transistor is electrically connected to the third second control node.

[0937] Optionally, the third first drive output circuit includes a twenty-fifth transistor and a third fifth capacitor, and the third second drive output circuit includes a third twenty-sixth transistor and a third sixth capacitor;

[0938] The gate of the 25th transistor is electrically connected to the third first control node, the first terminal of the 25th transistor is electrically connected to the first voltage terminal, and the second terminal of the 25th transistor is electrically connected to the Nth stage drive signal output terminal.

[0939] The first terminal of the third fifth capacitor is electrically connected to the third first control node, and the second terminal of the third fifth capacitor is electrically connected to the first voltage terminal.

[0940] The gate of the third 26th transistor is electrically connected to the third second control node, the first terminal of the third 26th transistor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the third 26th transistor is electrically connected to the second voltage terminal.

[0941] The first terminal of the third sixth capacitor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the third sixth capacitor is electrically connected to the second voltage terminal.

[0942] like Figure 50 As shown, in Figure 49 Based on at least one embodiment of the driving circuit shown,

[0943] The third gating circuit includes a third first transistor T3-1 and a third second transistor T3-2;

[0944] The gate of the third first transistor T3-1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the third first transistor T3-1 is electrically connected to the third first node N3-1, and the source of the third first transistor T3-1 is electrically connected to the drain of the third second transistor T3-2.

[0945] The gate of the third second transistor T3-2 is electrically connected to the third node N3(N-1) of the N-1th stage, and the source of the third second transistor T3-2 is electrically connected to the gating input terminal VCT.

[0946] The third output control circuit includes a third transistor T3-3;

[0947] The gate of the third transistor T3-3 is electrically connected to the third first node N3-1, the source of the third transistor T3-3 is electrically connected to the third first control node NC3-1, and the drain of the third transistor T3-3 is electrically connected to the third second node N3-2.

[0948] The third voltage control circuit includes a third first capacitor C3-1;

[0949] The first terminal of the third first capacitor C3-1 is electrically connected to the third first node N3-1, and the second terminal of the third first capacitor C3-1 is electrically connected to the third second node N3-2;

[0950] The third second node control circuit includes a third fourth transistor T3-4;

[0951] The gate of the third fourth transistor T3-4 is electrically connected to the third third control node NC3-3, the source of the third fourth transistor T3-4 is electrically connected to the third second node N3-2, and the drain of the third fourth transistor T3-4 is electrically connected to the high voltage terminal VGH.

[0952] The third output circuit includes a third fifth transistor T3-5, a third sixth transistor, and a third second capacitor C3-2;

[0953] The gate of the third fifth transistor T3-5 is electrically connected to the third second node N2, the source of the third fifth transistor T3-5 is electrically connected to the high voltage terminal VGH, and the drain of the third fifth transistor T3-5 is electrically connected to the output drive terminal NO(N).

[0954] The gate of the third sixth transistor T3-6 is electrically connected to the third third control node NC3-3, the source of the third sixth transistor T3-6 is electrically connected to the output drive terminal NO(N), and the drain of the third sixth transistor T3-6 is electrically connected to the low voltage terminal VGL.

[0955] The first terminal of the third second capacitor C3-2 is electrically connected to the third second node N3-2, and the second terminal of the third second capacitor C3-2 is electrically connected to the high voltage terminal VGH;

[0956] The third initialization circuit includes a third seventh transistor T3-7;

[0957] The gate of the third seventh transistor T3-7 is electrically connected to the initial control terminal NCX, the source of the third seventh transistor T3-7 is electrically connected to the third first node N3-1, and the drain of the third seventh transistor T3-7 is electrically connected to the low voltage terminal VGL.

[0958] The third first node control circuit includes a third eighth transistor T3-8;

[0959] The gate of the third eighth transistor T3-8 is electrically connected to the third fourth node N3-4, the source of the third eighth transistor T3-8 is electrically connected to the third first node N3-1, and the drain of the third eighth transistor T3-8 is electrically connected to the low voltage terminal VGL.

[0960] The third control node control circuit includes a third ninth transistor T3-9, a third tenth transistor T3-10, and a third eleventh transistor T3-11;

[0961] The gate of the third ninth transistor T3-9 is electrically connected to the third first node N3-1, the drain of the third ninth transistor T3-9 is electrically connected to the third fifth node N3-5, and the source of the third ninth transistor T3-9 is electrically connected to the third third control node NC3-3.

[0962] The gate and source of the third tenth transistor T3-10 are both electrically connected to the third sixth node N3-6, and the drain of the third tenth transistor T3-10 is electrically connected to the third second control node NC3-2.

[0963] The gate and source of the third eleventh transistor T3-11 are both electrically connected to the third sixth node N3-6, and the drain of the third eleventh transistor T3-11 is electrically connected to the third third control node NC3-3.

[0964] The third seventh node control circuit includes the third twelfth transistor T3-12 and the third thirteenth transistor T3-13; the third eighth node control circuit includes the third fourteenth transistor T3-14; the third third node control circuit includes the third fifteenth transistor T3-15 and the third third capacitor C3-3; and the third first control circuit includes the third sixteenth transistor T3-16 and the third seventeenth transistor T3-17.

[0965] The gate of the third twelfth transistor T3-12 is electrically connected to the first clock signal terminal GCK, the source of the third twelfth transistor T3-12 is electrically connected to the low voltage terminal VGL, and the drain of the third twelfth transistor T3-12 is electrically connected to the third seventh node N3-7.

[0966] The gate of the third thirteenth transistor T3-13 is electrically connected to the third fifth node N3-5, the source of the third thirteenth transistor T3-13 is electrically connected to the third seventh node N3-7, and the drain of the third thirteenth transistor T3-13 is electrically connected to the first clock signal terminal GCK.

[0967] The gate of the third fourteenth transistor T3-14 is electrically connected to the low voltage terminal VGL, the source of the third fourteenth transistor T3-14 is electrically connected to the third seventh node N3-7, and the drain of the third fourteenth transistor T3-14 is electrically connected to the third eighth node N3-8.

[0968] The gate of the third fifteenth transistor T3-15 is electrically connected to the third eighth node N3-8, the source of the third fifteenth transistor T3-15 is electrically connected to the second clock signal terminal GCB, and the drain of the third fifteenth transistor T3-15 is electrically connected to the third third node N3-3.

[0969] The gate of the third sixteenth transistor T3-16 is electrically connected to the second clock signal terminal GCB, the source of the third sixteenth transistor T3-16 is electrically connected to the third third node N3-3, and the drain of the third sixteenth transistor T3-16 is electrically connected ...

Claims

1. A driving circuit, characterized in that, It includes a first drive signal generation circuit, a first output control circuit, a first gating circuit, and a first output circuit; N is a positive integer; The first drive signal generation circuit is electrically connected to the first first control node, the first second control node and the Nth stage drive signal output terminal, respectively, and is used to generate and output the Nth stage drive signal through the Nth stage drive signal output terminal under the control of the potential of the first first control node and the potential of the first second control node. The first output control circuit is electrically connected to the first first node, the first first control node, and the first second node, respectively, and is used to control the connection between the first first control node and the first second node under the control of the potential of the first first node; The first gating circuit is electrically connected to the first first node, the gating input terminal and the gating control terminal respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first first node under the control of the gating control signal provided by the gating control terminal; The first output circuit is electrically connected to the first second node, the control electrode, the first voltage terminal, the second voltage terminal, and the Nth stage output drive terminal, respectively. It is used to control the Nth stage output drive terminal to connect with the first voltage terminal under the control of the potential of the first second node, and to control the Nth stage output drive terminal to connect with the second voltage terminal under the control of the potential of the control electrode.

2. The driving circuit as described in claim 1, characterized in that, The first gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

3. The driving circuit as described in claim 1 or 2, characterized in that, The first output control circuit includes a first third transistor; The gate of the first third transistor is electrically connected to the first first node, the first electrode of the first third transistor is electrically connected to the first first control node, and the second electrode of the first third transistor is electrically connected to the first second node.

4. The driving circuit as described in claim 1 or 2, characterized in that, It also includes the first second node control circuit; The first second node control circuit is electrically connected to the control electrode, the first second node and the first voltage terminal respectively, and is used to control the connection between the first second node and the first voltage terminal under the control of the potential of the control electrode.

5. The driving circuit as described in claim 4, characterized in that, The first second node control circuit includes a first fourth transistor; The first terminal of the first fourth transistor is electrically connected to the first second node, and the second terminal of the first fourth transistor is electrically connected to the first voltage terminal.

6. The driving circuit as described in claim 1 or 2, characterized in that, The first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor; The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the first fifth transistor is electrically connected to the Nth stage output drive terminal. The gate of the first sixth transistor is electrically connected to the control electrode, the first electrode of the first sixth transistor is electrically connected to the Nth stage output drive terminal, and the second electrode of the first sixth transistor is electrically connected to the second voltage terminal. The first terminal of the first third capacitor is electrically connected to the first second node, and the second terminal of the first third capacitor is electrically connected to the first voltage terminal.

7. The driving circuit as described in claim 1 or 2, characterized in that, The first drive signal generation circuit includes a first first drive output circuit, a first second drive output circuit, a first first control node control circuit, and a first second control node control circuit; The first control node control circuit is used to control the potential of the first control node; The first second control node control circuit is used to control the potential of the first second control node; The first first drive output circuit is electrically connected to the first first control node, the first voltage terminal and the Nth stage drive signal output terminal respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the potential of the first first control node; The first second drive output circuit is electrically connected to the first second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the second voltage terminal under the control of the potential of the first second control node.

8. The driving circuit as described in claim 7, characterized in that, The first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit. The first seventh node control circuit is electrically connected to the first seventh node, the second voltage terminal, the first clock signal terminal, and the first fifth node, respectively. It is used to control the connection between the first seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of the potential of the first fifth node. The first eighth node control circuit is electrically connected to the second voltage terminal, the first seventh node, and the first eighth node, respectively, and is used to control the connection between the first seventh node and the first eighth node under the control of the second voltage signal provided by the second voltage terminal; The first third node control circuit is electrically connected to the first eighth node, the second clock signal terminal, and the first third node, respectively. It is used to control the first third node to be electrically connected to the second clock signal terminal under the control of the potential of the first eighth node, and to control the potential of the first third node according to the potential of the first eighth node. The first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node, and the first voltage terminal, respectively. It is used to control the connection between the first third node and the first first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node.

9. The driving circuit as described in claim 7, characterized in that, The first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit. The first sixth node control circuit is electrically connected to the second voltage terminal, the first ninth node, the first sixth node, and the first fourth node, respectively, and is used to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the first sixth node according to the potential of the first fourth node. The first fifth node control circuit is electrically connected to the N-1 level drive signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, respectively. It is used to control the connection between the first fifth node and the N-1 level drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first fifth node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal. The first ninth node control circuit is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal and the first ninth node respectively, and is used to control the connection between the first ninth node and the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal. The first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively. It is used to control the connection between the first fourth node and the first voltage terminal under the control of the potential of the first seventh node, and to control the connection between the first fourth node and the second clock signal terminal under the control of the potential of the first sixth node. The first second control circuit is electrically connected to the second voltage terminal, the first fifth node, and the first second control node, respectively, and is used to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal.

10. The driving circuit as described in claim 8, characterized in that, The first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor; the first eighth node control circuit includes a first fourteenth transistor; the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor; and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor. The gate of the first twelfth transistor is electrically connected to the first clock signal terminal, the first terminal of the first twelfth transistor is electrically connected to the second voltage terminal, and the second terminal of the first twelfth transistor is electrically connected to the first seventh node. The gate of the first thirteenth transistor is electrically connected to the first fifth node, the first terminal of the first thirteenth transistor is electrically connected to the first seventh node, and the second terminal of the first thirteenth transistor is electrically connected to the first clock signal terminal. The gate of the first fourteenth transistor is electrically connected to the second voltage terminal, the first terminal of the first fourteenth transistor is electrically connected to the first seventh node, and the second terminal of the first fourteenth transistor is electrically connected to the first eighth node. The gate of the first fifteenth transistor is electrically connected to the first eighth node, the first terminal of the first fifteenth transistor is electrically connected to the second clock signal terminal, and the second terminal of the first fifteenth transistor is electrically connected to the first third node; The first terminal of the first fourth capacitor is electrically connected to the first eighth node, and the second terminal of the first fourth capacitor is electrically connected to the first third node. The gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the first sixteenth transistor is electrically connected to the first third node, and the second terminal of the first sixteenth transistor is electrically connected to the first first control node. The gate of the first seventeenth transistor is electrically connected to the first fifth node, the first terminal of the first seventeenth transistor is electrically connected to the first first control node, and the second terminal of the first seventeenth transistor is electrically connected to the first voltage terminal.

11. The driving circuit as described in claim 9, characterized in that, The first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor; the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor; the first ninth node control circuit includes a first twenty-first transistor; the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor; and the first second control circuit includes a first twenty-fourth transistor. The gate of the first eighteenth transistor is electrically connected to the second voltage terminal, the first terminal of the first eighteenth transistor is electrically connected to the first ninth node, and the second terminal of the first eighteenth transistor is electrically connected to the first sixth node. The first terminal of the first fifth capacitor is electrically connected to the first fourth node, and the second terminal of the first fifth capacitor is electrically connected to the first sixth node; The gate of the first nineteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the first nineteenth transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the first nineteenth transistor is electrically connected to the first fifth node. The gate of the first twentieth transistor is electrically connected to the initial control terminal, the first terminal of the first twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the first twentieth transistor is electrically connected to the first fifth node. The gate of the first twenty-first transistor is electrically connected to the first clock signal terminal, the first terminal of the first twenty-first transistor is electrically connected to the N-1th stage drive signal output terminal, and the second terminal of the first twenty-first transistor is electrically connected to the first ninth node. The gate of the first twenty-second transistor is electrically connected to the first seventh node, the first terminal of the first twenty-second transistor is electrically connected to the first voltage terminal, and the second terminal of the first twenty-second transistor is electrically connected to the first fourth node. The gate of the first twenty-third transistor is electrically connected to the first sixth node, the first terminal of the first twenty-third transistor is electrically connected to the first fourth node, and the second terminal of the first twenty-third transistor is electrically connected to the second clock signal terminal. The gate of the first twenty-fourth transistor is electrically connected to the second voltage terminal, the first terminal of the first twenty-fourth transistor is electrically connected to the first ninth node, and the second terminal of the first twenty-fourth transistor is electrically connected to the first second control node.

12. The driving circuit as described in claim 7, characterized in that, The first first drive output circuit includes a first twenty-fifth transistor and a first sixth capacitor, and the first second drive output circuit includes a first twenty-sixth transistor and a first seventh capacitor; The gate of the first twenty-fifth transistor is electrically connected to the first first control node, the first terminal of the first twenty-fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the first twenty-fifth transistor is electrically connected to the Nth stage drive signal output terminal. The first terminal of the first sixth capacitor is electrically connected to the first first control node, and the second terminal of the first sixth capacitor is electrically connected to the first voltage terminal. The gate of the first twenty-sixth transistor is electrically connected to the first second control node, the first terminal of the first twenty-sixth transistor is electrically connected to the Nth stage drive signal output terminal, and the second terminal of the first twenty-sixth transistor is electrically connected to the second voltage terminal.

13. A driving method applied to a driving circuit as described in any one of claims 1 to 12, the driving method comprising: The first drive signal generation circuit generates and outputs the Nth-level drive signal through the Nth-level drive signal output terminal under the control of the potential of the first first control node and the potential of the first second control node. The first output control circuit controls the connection between the first first control node and the first second node under the control of the potential of the first first node; Under the control of the gating control signal, the first gating circuit controls the gating input signal to be written into the first node; Under the control of the potential of the first second node, the first output circuit controls the connection between the Nth stage output drive terminal and the first voltage terminal. Under the control of the potential of the first output circuit, the first output circuit controls the connection between the Nth stage output drive terminal and the second voltage terminal. N is a positive integer.

14. A drive module, characterized in that, Includes multiple levels of drive circuitry as described in any one of claims 1 to 12; The Nth stage drive circuit is electrically connected to the drive signal output terminals of the (N-1)th stage drive circuit; N is a positive integer.

15. A display device, characterized in that, Includes the drive module as described in claim 14.

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