Memory control method and storage device

Abstract

The application provides a memory control method and a memory device. The method comprises the following steps: reading first data from a first physical unit in a memory module; after the first data is obtained from the memory module, performing data quality analysis on the first data to obtain a quality analysis result without performing a decoding operation on the first data by a decoding circuit; if the quality analysis result is a first result, directly starting a re-reading operation on the first physical unit to re-read the first physical unit by a re-reading voltage to obtain second data. Therefore, the data reading efficiency of the memory device can be improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory control method and storage device. Background Technology

[0002] NAND flash memory is a type of non-volatile memory widely used in electronic devices such as memory cards, solid-state drives (SSDs), and portable multimedia players. Solid-state drives (SSDs), as a new type of storage medium, use NAND flash memory for data storage and are widely used in PCs, laptops, servers, and other fields, gradually replacing hard disk drives (HDDs) as the mainstream storage product.

[0003] As NAND flash memory cell manufacturing processes have entered the stacked architecture of more than 300 layers, the problem of threshold voltage distribution distortion caused by multi-bit storage technology (QLC / PLC), device durability decay, and read / write crosstalk in solid-state drives (SSDs) has become increasingly prominent, resulting in an exponential increase in raw bit error rate (RBER). The current mainstream solution adopts the read retry mechanism, which compensates for voltage distribution offset by dynamically adjusting the read reference voltage (Vref). Its core implementation methods include: (1) off-chip ECC dependent mode: data pages need to be transferred to the off-chip ECC engine through the DMA channel for complete decoding, and the reread process is only triggered after decoding failure. Experimental data shows that this process leads to a 32%-47% decrease in effective bandwidth utilization (Micron ZNS SSD measured data); (2) traversal voltage adjustment: based on the manufacturer's preset Vref search sequence, multiple voltage points are traversed, which introduces additional latency; (3) passive triggering mechanism: the reread operation depends entirely on the ECC decoding result and cannot predict the page quality before the data physical layer is transmitted. According to the JEDEC JESD219A standard test, invalid transmissions of unrecoverable data pages account for 19.7%-34.6% of the total channel bandwidth.

[0004] Therefore, there is an urgent need to develop a reread optimization scheme with data quality prediction capabilities, which can overcome the systemic limitations of existing technologies in bandwidth efficiency and response speed by implementing real-time quality assessment that is not dependent on decoding within the flash memory controller. Summary of the Invention

[0005] The present invention provides a memory control method and a storage device, which can improve the above-mentioned problems and thereby improve the data reading efficiency of the storage device.

[0006] Embodiments of the present invention provide a memory control method for a storage device, wherein the storage device includes a memory module, and the memory control method includes: reading first data from a first physical unit in the memory module; after obtaining the first data from the memory module, performing data quality analysis on the first data to obtain a quality analysis result without performing a decoding operation on the first data through a decoding circuit; if the quality analysis result is a first result, directly initiating a rereading operation on the first physical unit to reread the first physical unit through a rereading voltage to obtain second data; and if the quality analysis result is a second result, performing the decoding operation on the first data through the decoding circuit.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: read first data from a first physical unit in the memory module; after obtaining the first data from the memory module, perform data quality analysis on the first data without performing a decoding operation on the first data through a decoding circuit to obtain a quality analysis result; if the quality analysis result is a first result, directly initiate a reread operation on the first physical unit to reread the first physical unit through a reread voltage to obtain second data; and if the quality analysis result is a second result, perform the decoding operation on the first data through the decoding circuit. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating the comparison of target data and reference data according to an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram illustrating parity checking according to an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram illustrating the adjustment of the rereading voltage according to an embodiment of the present invention;

[0014] Figure 7 This is a schematic diagram of a memory control circuit according to an embodiment of the present invention;

[0015] Figure 8 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0017] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0018] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0019] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0020] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0021] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0022] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0026] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0027] In one embodiment, an entity unit may include one or more entity programming units. An entity erase unit may include multiple entity programming units.

[0028] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be considered as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0030] In one embodiment, multiple programmed units within a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to the multiple programmed units within that physical erase unit to change the threshold voltage of at least a portion of the memory cells in those programmed units. By performing an erase operation on a physical erase unit, the data stored in that physical erase unit can be erased. In one embodiment, a physical erase unit can be considered as a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1) to 301(A) and 301(A+1) to 301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1) to 301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1) to 301(B) in the idle area 32 do not store any data (e.g., valid data).

[0032] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0033] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may be configured with a plurality of logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 may send a read instruction sequence to the memory module 122. This read instruction sequence instructs the reading of data (also referred to as first data) from a physical unit (also referred to as a first physical unit) in the memory module 122. For example, according to this read instruction sequence, the memory module 122 may read the first data from the first physical unit based on a read voltage (also referred to as a preset read voltage) and transmit the first data to the memory control circuit 23. For example, the first physical unit may include… Figure 3 At least one of the entity units 301(1) to 301(A) in the text.

[0038] In one embodiment, after obtaining first data from memory module 122, without performing a decoding operation on the first data through decoding circuit 25, memory control circuit 23 may perform data quality analysis on the first data to obtain a quality analysis result. For example, without performing a decoding operation on the first data through decoding circuit 25, this quality analysis result may (approximately) reflect the error rate and / or reliability of the first data. Subsequently, memory control circuit 23 may dynamically determine, based on this quality analysis result, whether to directly initiate a reread operation on the first physical unit, or to perform a decoding operation on the first data through decoding circuit 25. For example, the reread operation is used to reread the data on the first physical unit based on a reread voltage different from the aforementioned preset read voltage. In addition, the decoding operation is used to decode the first data to attempt to correct errors (e.g., erroneous bits) in the first data.

[0039] In one embodiment, if the quality analysis result is a certain result (also referred to as the first result), the memory control circuit 23 can directly initiate a reread operation for the first entity cell to reread the first entity cell using the reread voltage to obtain another data (also referred to as the second data). For example, if the error rate of the first data is predicted to be relatively high (e.g., above the error rate threshold) and / or the reliability is relatively low (e.g., below the reliability threshold) based on the quality analysis result (i.e., the quality analysis result is the first result), the memory control circuit 23 can directly initiate a reread operation for the first entity cell to resend the read instruction sequence to reread the data from the first entity cell in an attempt to obtain second data with a relatively low error rate (e.g., below the error rate threshold) and / or relatively high reliability (e.g., above the reliability threshold).

[0040] In one embodiment, directly initiating a reread operation for the first entity unit in response to the aforementioned first result allows for skipping the decoding operation on the first data and rereading the data if the error rate of the first data is relatively high (e.g., above an error rate threshold), the reliability is relatively low (e.g., below a reliability threshold), and / or the current decoding success rate is relatively low (e.g., below a preset decoding success rate). This improves the data reading efficiency of the storage device.

[0041] In one embodiment, if the quality analysis result is a different result (also referred to as a second result), the memory control circuit 23 can perform a decoding operation on the first data via the decoding circuit 25. For example, if the error rate of the first data is predicted to be relatively low (e.g., below the error rate threshold) and / or the reliability is relatively high (e.g., above the reliability threshold) based on the quality analysis result (i.e., the quality analysis result is the second result), the memory control circuit 23 can instruct the decoding circuit 25 to perform a decoding operation on the first data to attempt to obtain decoded data by decoding the first data. For example, compared to the original data (i.e., the original first data), the errors in the decoded data (i.e., the decoded first data) have been corrected.

[0042] In one embodiment, by directly performing a decoding operation on the first data in response to the aforementioned second result, errors in the first data can be quickly corrected by decisively performing a decoding operation when the error rate of the first data is relatively low (e.g., below an error rate threshold), the reliability is relatively high (e.g., above a reliability threshold), and / or the current decoding success rate is relatively high (e.g., above a preset decoding success rate). This also improves the data reading efficiency of the storage device.

[0043] In other words, in one embodiment, after obtaining the first data from the memory module 122, the first data will not be directly input to the decoding circuit 25 for decoding (i.e., performing a decoding operation). Instead, after obtaining the first data from the memory module 122, before inputting the first data to the decoding circuit 25 (i.e., without performing a decoding operation on the first data through the decoding circuit 25), the memory control circuit 23 can first perform data quality analysis on the first data to obtain the quality analysis result. In particular, the data quality analysis of the first data does not involve the operation of the decoding circuit 25. Then, based on the current situation (e.g., the quality analysis result), it is dynamically determined whether to directly initiate a reread operation for the first physical unit, or to perform a decoding operation on the first data through the decoding circuit 25. As a result, the data reading efficiency of the storage device 12 can be significantly improved.

[0044] In one embodiment, after obtaining first data from memory module 122, memory control circuit 23 can read reference data from a management table according to the logical unit (also referred to as the first logical unit) to which the first data belongs. For example, the first logical unit is mapped to a first physical unit. For example, the first logical unit may include... Figure 3 At least one of the logic units 302(1) to 302(C) in the system.

[0045] In one embodiment, the reference data includes feature data corresponding to the first data. This feature data is obtained by performing feature extraction on the first data during storage. For example, during the previous storage of data belonging to the first logic unit (i.e., the first data) into the memory module 122, the memory control circuit 23 may perform the feature extraction (i.e., extract data features from the first data) on the first data to obtain the reference data corresponding to the first data. For example, the reference data (or feature data) may reflect the data features of at least a portion of the data in the first data. After obtaining the reference data, the memory control circuit 23 may record the reference data in the management table by binding or matching it with the first logic unit.

[0046] Subsequently, during the data quality analysis of the first data, the memory control circuit 23 may retrieve the reference data from a management table. For example, the memory control circuit 23 may query the management table based on the identification information of the first logic unit (e.g., the logic unit's number or address information) to read the reference data bound to or matching the first logic unit from the management table. Then, the memory control circuit 23 may perform the data quality analysis on the first data based on the reference data.

[0047] In one embodiment, after obtaining the reference data, the memory control circuit 23 can compare the first data with the reference data to obtain the quality resolution result. For example, without involving the decoding circuit 25 processing the first data, the memory control circuit 23 can compare the first data with the reference data to obtain an evaluation value (also referred to as a first evaluation value). For example, without involving the decoding circuit 25 processing the first data, the memory control circuit 23 can compare each bit in the first data with each bit in the reference data one by one to confirm whether they are the same. Then, the memory control circuit 23 can obtain the first evaluation value based on the comparison result.

[0048] In one embodiment, the first evaluation value may reflect the degree of difference between the first data and the reference data. For example, the first evaluation value may be positively correlated with the degree of difference between the first data and the reference data. That is, the larger the first evaluation value, the greater the degree of difference between the first data and the reference data (i.e., the fewer the total number of identical bits in the first data and the reference data).

[0049] In one embodiment, the memory control circuit 23 can determine the numerical relative relationship between the first evaluation value and a threshold value (also referred to as the first threshold value) based on the first evaluation value. Then, the memory control circuit 23 can obtain the quality analysis result based on this numerical relative relationship. For example, based on different numerical relative relationships between the first evaluation value and the first threshold value (e.g., the first evaluation value is greater than the first threshold value, the first evaluation value is less than the first threshold value, or the first evaluation value is equal to the first threshold value), the memory control circuit 23 can obtain the corresponding quality analysis result.

[0050] In one embodiment, if the numerical relative relationship reflects that the first evaluation value is greater than the first threshold value, the memory control circuit 23 can determine that the difference between the first data and the reference data is relatively large (e.g., greater than the threshold). If the numerical relative relationship reflects that the first evaluation value is less than the first threshold value, the memory control circuit 23 can determine that the difference between the first data and the reference data is relatively small (e.g., less than the threshold). Furthermore, if the numerical relative relationship reflects that the first evaluation value is equal to the first threshold value, the memory control circuit 23 can determine that the difference between the first data and the reference data is neither too large nor too small (e.g., close to the threshold). Subsequently, the memory control circuit 23 can determine the quality analysis result based on the numerical relative relationship (or the difference between the first data and the reference data). In other words, the quality analysis result can reflect the difference between the first data and the reference data.

[0051] In one embodiment, the degree of difference (or first evaluation value) between the first data and the reference data may be positively correlated with the error rate of the first data and / or negatively correlated with the reliability of the first data. That is, if the degree of difference (or first evaluation value) between the first data and the reference data is relatively large (e.g., the first evaluation value is greater than a first threshold), the memory control circuit 23 may determine that the error rate of the first data is relatively high (e.g., higher than the error rate threshold) and / or the reliability of the first data is relatively low (e.g., lower than the reliability threshold). Conversely, if the degree of difference (or first evaluation value) between the first data and the reference data is relatively small (e.g., the first evaluation value is less than the first threshold), the memory control circuit 23 may determine that the error rate of the first data is relatively low (e.g., lower than the error rate threshold) and / or the reliability of the first data is relatively high (e.g., higher than the reliability threshold).

[0052] In one embodiment, the memory control circuit 23 can determine a sampling window (also known as a dynamic sampling window) based on the first logic unit. For example, the management table may record configuration information of the dynamic sampling window corresponding to or matching the first logic unit. Then, the memory control circuit 23 can query the management table based on the first logic unit to determine the dynamic sampling window. Then, the memory control circuit 23 can determine at least a portion of the data (also known as target data) from the first data based on the dynamic sampling window.

[0053] In one embodiment, after determining the target data, the memory control circuit 23 can compare the target data with the reference data to obtain the quality analysis result. For example, the quality analysis result (or first evaluation value) can reflect the degree of difference between the target data and the reference data.

[0054] Figure 4 This is a schematic diagram illustrating the comparison of target data and reference data according to an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, it is assumed that the first data includes data 41. After reading data 41 from memory module 122, memory control circuit 23 may query a management table to determine a sampling window W (i.e., a dynamic sampling window). For example, sampling window W is used to define a bit range R (also known as a target bit range) in data 41.

[0055] In one embodiment, after determining the sampling window W, the memory control circuit 23 can determine or identify all data in data 41 located within the bit range R as target data 401 according to the sampling window W. Simultaneously, the memory control circuit 23 can determine or identify all data in data 41 not located within the bit range R as non-target data 402 according to the sampling window W. Then, the memory control circuit 23 can compare the target data 401 located within the bit range R in data 41 with reference data 42 to obtain a comparison result (or a first evaluation value). For example, this comparison result (or first evaluation value) can reflect the degree of difference between the target data 401 and the reference data 42. Then, the memory control circuit 23 can obtain the quality analysis result based on this comparison result. In other words, in Figure 4 In one embodiment, the quality analysis result can reflect the degree of difference between the target data 401 and the reference data 42.

[0056] It should be noted that, in Figure 4 In this embodiment, the overall error rate and / or reliability of data 41 are evaluated based on the degree of difference between target data 401 and reference data 42. However, depending on the type of data 41, the relative position of the sampling window W (or bit range R) in data 41 and / or the total number of sampling windows W (or bit range R) can be adjusted according to practical needs.

[0057] In one embodiment, after obtaining the first data from the memory module 122, the memory control circuit 23 may also perform a parity check on the first data to obtain another evaluation value (also referred to as a second evaluation value). The second evaluation value may reflect the error rate and / or reliability of the first data. For example, the second evaluation value may be positively correlated with the error rate of the first data and / or negatively correlated with the reliability of the first data. That is, the larger the second evaluation value, the higher the error rate of the first data and / or the lower the reliability of the first data. Then, the memory control circuit 23 may obtain the quality resolution result based on the second evaluation value. It should be noted that the parity check may be performed by the memory control circuit 23, but not by the decoding circuit 25.

[0058] Figure 5 This is a schematic diagram illustrating parity checking according to an embodiment of the present invention. Please refer to... Figure 5 In one embodiment, the memory control circuit 23 may obtain matrix 51 (also referred to as parity check matrix H) and assume that the first data includes data vector 52. For example, matrix 51 may be a (j+1)×(i+1) matrix, and i and j may be set as needed. Each element in matrix 51 may be "1" or "0". In addition, data vector 52 includes bits V(0) to V(j).

[0059] In one embodiment, during the parity check, the memory control circuit 23 may perform matrix multiplication on matrix 51 and data vector 52 to obtain a check vector 53. For example, the check vector 53 may reflect the result of performing matrix multiplication on matrix 51 and data vector 52. For example, the check vector 53 may include multiple elements S(0) to S(j). Elements S(0) to S(j) may also be referred to as check elements. For example, each element in elements S(0) to S(j) may be "1" or "0".

[0060] In one embodiment, the memory control circuit 23 can obtain the quality analysis result based on the verification vector 53. For example, the memory control circuit 23 can extract elements S(0) to S(j) from the verification vector 53 and obtain the sum of elements S(0) to S(j). For example, the sum of elements S(0) to S(j) can reflect (or be the same as) the total number of "1"s in elements S(0) to S(j). In particular, the sum of elements S(0) to S(j) can reflect the error rate and / or reliability of the first data. For example, the larger the sum of elements S(0) to S(j), the higher the error rate of the first data and / or the lower the reliability of the first data.

[0061] In one embodiment, the memory control circuit 23 can obtain the quality analysis result based on the sum of elements S(0) to S(j). In another embodiment, the memory control circuit 23 can obtain a second evaluation value based on the sum of elements S(0) to S(j). For example, the second evaluation value may be the same as or positively correlated with the sum of elements S(0) to S(j). Then, the memory control circuit 23 can obtain the quality analysis result based on the second evaluation value.

[0062] In one embodiment, the memory control circuit 23 can determine the numerical relative relationship between the second evaluation value and a threshold value (also referred to as the second threshold value) based on the second evaluation value. Then, the memory control circuit 23 can obtain the quality analysis result based on this numerical relative relationship. For example, based on different numerical relative relationships between the second evaluation value and the second threshold value (e.g., the second evaluation value is greater than the second threshold value, the second evaluation value is less than the second threshold value, or the second evaluation value is equal to the second threshold value), the memory control circuit 23 can obtain corresponding quality analysis results.

[0063] In one embodiment, if the numerical relationship reflects that the second evaluation value is greater than the second threshold value, the memory control circuit 23 can determine that the error rate of the first data is relatively high (e.g., higher than the error rate threshold value) and / or the reliability of the first data is relatively low (e.g., lower than the reliability threshold value). If the numerical relationship reflects that the second evaluation value is less than the second threshold value, the memory control circuit 23 can determine that the error rate of the first data is relatively low (e.g., lower than the error rate threshold value) and / or the reliability of the first data is relatively high (e.g., higher than the reliability threshold value). Subsequently, without involving the decoding circuit 25 to process the first data, the memory control circuit 23 can determine, based on the quality analysis result, whether to directly initiate a reread operation for the first entity unit, or to perform a decoding operation on the first data through the decoding circuit 25. This significantly improves the data reading efficiency of the storage device 12.

[0064] In one embodiment, after acquiring the second data, the memory control circuit 23 can further compare the first data and the second data to obtain a comparison result. This comparison result reflects the difference between the first data and the second data. Then, the memory control circuit 23 can adjust the reread voltage used for the reread operation based on this comparison result. Therefore, in the reread operation that skips decoding the first data and is performed directly, errors in the read data can be further reduced, thereby improving the data read efficiency of the storage device 12.

[0065] In one embodiment, if the comparison result reflects a decrease in the data difference between the first data and the second data, it indicates that the first data and the second data are converging. In this case, the memory control circuit 23 can maintain the current voltage adjustment direction for the reread voltage. For example, suppose the current voltage adjustment direction for the reread voltage is to gradually increase the reread voltage value. If the comparison result reflects a decrease in the data difference between the first data and the second data, the memory control circuit 23 may not change the current voltage adjustment direction for the reread voltage (i.e., gradually increasing the reread voltage value).

[0066] In one embodiment, if the comparison result reflects an increase in the data difference between the first data and the second data, it indicates that the difference between the first data and the second data is amplifying. In this case, the memory control circuit 23 can change the current voltage adjustment direction for the reread voltage. For example, suppose the current voltage adjustment direction for the reread voltage is to gradually increase the reread voltage value. If the comparison result reflects an increase in the data difference between the first data and the second data, the memory control circuit 23 can switch to gradually decreasing the reread voltage value. Alternatively, suppose the current voltage adjustment direction for the reread voltage is to gradually decrease the reread voltage value. If the comparison result reflects an increase in the data difference between the first data and the second data, the memory control circuit 23 can switch to gradually increasing the reread voltage value.

[0067] Figure 6 This is a schematic diagram illustrating the adjustment of the rereading voltage according to an embodiment of the present invention. Please refer to... Figure 6 Assume that the critical voltage distribution of multiple memory cells in the first entity cell includes states 61 and 62. States 61 and 62 correspond to different bits (or combinations of bits).

[0068] In one embodiment, it is assumed that the first data is read from the first physical cell based on a read voltage 601, while in a reread operation for the first physical cell, the second data is read from the first physical cell based on a read voltage 602. After comparing the first data and the second data, if the comparison result shows that the data difference between the first data and the second data gradually increases, it indicates that the current voltage adjustment direction of adding the voltage difference ΔV to the read voltage 601 to obtain the read voltage 602 is incorrect. In this case, the memory control circuit 23 can change the current voltage adjustment direction for the reread voltage, for example, by subtracting the voltage difference ΔV from the read voltage 601 to obtain the read voltage 603. In subsequent reread operations for the first physical cell, the error rate of the data read from the first physical cell based on the read voltage 603 is more likely to be less than the error rate of the data read from the first physical cell based on the read voltage 602 (and / or 601). Alternatively, in a subsequent reread operation on the first physical unit, the reliability of the data read from the first physical unit based on read voltage 603 is more likely to be higher than the reliability of the data read from the first physical unit based on read voltage 602 (and / or 601). Therefore, in reread operations that skip decoding the first data and are performed directly, errors in the read data can be further reduced, thereby improving the data read efficiency of the storage device 12.

[0069] In one embodiment, after obtaining the second data, without performing a decoding operation on the second data through the decoding circuit 25, the memory control circuit 23 may perform the data quality analysis on the second data to update the quality analysis result. It should be noted that the operational details regarding how to perform the data quality analysis on specific data (e.g., the first data and / or the second data) to obtain or update the quality analysis result have been described above and will not be repeated here.

[0070] In one embodiment, after updating the quality analysis result, if the updated quality analysis result is the aforementioned first result (e.g., the predicted error rate of the second data is relatively high (e.g., above the error rate threshold) and the reliability is relatively low (e.g., below the reliability threshold)), and / or the current decoding success rate is assessed to be relatively low (e.g., below the preset decoding success rate), the memory control circuit 23 can restart the reread operation for the first physical unit to attempt to reread the data (also referred to as the third data) with a lower error rate and / or higher reliability directly based on different reread voltages before decoding the second data through the decoding circuit 25. This improves the data reading efficiency of the storage device 12.

[0071] On the other hand, if the updated quality analysis result is the aforementioned second result (e.g., the error rate of the second data is predicted to be relatively low (e.g., below the error rate threshold) and / or the reliability is relatively high (e.g., above the reliability threshold)), the memory control circuit 23 can perform a decoding operation on the first data through the decoding circuit 25. Thus, while ensuring a relatively high decoding success rate (e.g., above the reliability threshold), errors in the second data can be quickly corrected by decisively performing a decoding operation. This also improves the data reading efficiency of the storage device 12.

[0072] In one embodiment, the first data and the second data mentioned above may also refer to any two data read sequentially from the first physical unit (or memory module 122) based on different reread voltages during the reread operation. Other operational details have been described above and will not be repeated here.

[0073] Figure 7 This is a schematic diagram of a memory control circuit according to an embodiment of the present invention. Please refer to... Figure 7In one embodiment, the memory control circuit 23 may include at least two of an XOR gate array 71, a bit-to-toe counter 72, and a threshold comparator 73 to support the aforementioned data quality parsing. For example, the XOR gate array 71 is used to perform bit-by-bit comparisons between two data sets and output the comparison results. The bit-to-toe counter 72 is used to count the total number of different bits at the same position between two data sets. The threshold comparator 73 is used to compare the total number with a threshold value to obtain a comparison result.

[0074] In one embodiment, the XOR logic gate array 71, the bit-to-flip counter 72, and / or the threshold comparator 73 may also provide corresponding operational behaviors based on their own performance. In one embodiment, the memory control circuit 23 may also include other types of circuit modules (e.g., matrix multiplication circuit modules). Thus, the aforementioned data quality parsing can be performed by the memory control circuit 23 itself without needing to go through the decoding circuit 25.

[0075] Figure 8 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Please refer to... Figure 8 In step S801, first data is read from the first physical unit in the memory module. After obtaining the first data from the memory module, in step S802, without performing a decoding operation on the first data through the decoding circuit, data quality analysis is performed on the first data to obtain a quality analysis result. In step S803, it is determined whether the quality analysis result is the first result (or the second result). If the quality analysis result is the first result, in step S804, a rereading operation is directly initiated for the first physical unit to reread the first physical unit through a rereading voltage to obtain the second data. However, if the quality analysis result is not the first result (i.e., the second result), in step S805, a decoding operation is performed on the first data through the decoding circuit.

[0076] However, Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 8 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0077] In summary, the control method and storage device proposed in the embodiments of the present invention can improve the technical problems caused by the indiscriminate transmission of data read from the memory module to the decoding circuit for decoding, resulting in poor decoding efficiency and / or bandwidth occupation between the decoding circuit and the memory control circuit, thereby improving the overall data reading efficiency of the storage device.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that, For a storage device, wherein the storage device includes a memory module, and the memory control method includes: Read the first data from the first physical unit of the memory module; After obtaining the first data from the memory module, without performing a decoding operation on the first data through the decoding circuit, data quality analysis is performed on the first data to obtain a quality analysis result. The step of performing the data quality analysis on the first data to obtain the quality analysis result includes: According to a first logical unit, reference data is read from a management table, wherein the first logical unit is mapped to a first entity unit, the reference data includes feature data corresponding to the first data, and the feature data is obtained by performing feature extraction on the first data during storage; and The first data is compared with the reference data to obtain the quality analysis result; If the quality analysis result is the first result, a reread operation is directly initiated for the first physical unit to reread the first physical unit using a reread voltage to obtain the second data; and If the quality analysis result is the second result, the decoding operation is performed on the first data through the decoding circuit.

2. The memory control method according to claim 1, wherein the step of comparing the first data with the reference data to obtain the quality analysis result includes: The first data is compared with reference data to obtain a first evaluation value, wherein the first evaluation value reflects the degree of difference between the first data and the reference data; as well as The quality analysis result is obtained based on the numerical relative relationship between the first evaluation value and the critical value.

3. The memory control method according to claim 1, wherein the step of comparing the first data with the reference data to obtain the quality analysis result includes: Based on the first logic unit, determine the dynamic sampling window; Target data is determined from the first data based on the dynamic sampling window; as well as The target data is compared with the reference data to obtain the quality analysis result.

4. The memory control method according to claim 1, wherein the step of performing the data quality parsing on the first data to obtain the quality parsing result includes: A parity check is performed on the first data to obtain a second evaluation value, wherein the parity check is not performed by the decoding circuit. as well as The quality analysis results are obtained based on the second evaluation value.

5. The memory control method according to claim 1, further comprising: After obtaining the second data, compare the first data with the second data to obtain a comparison result; as well as Based on the comparison results, the rereading voltage is adjusted.

6. The memory control method according to claim 5, wherein the step of adjusting the reread voltage based on the comparison result includes: If the comparison result reflects an increase in the data difference between the first data and the second data, the voltage adjustment direction of the reread voltage is changed.

7. The memory control method according to claim 1, further comprising: After obtaining the second data, without performing the decoding operation on the second data through the decoding circuit, the data quality analysis is performed on the second data to update the quality analysis result; If the updated quality analysis result is the first result, the reread operation for the first entity unit is restarted. as well as If the updated quality analysis result is the second result, the decoding operation is performed on the second data through the decoding circuit.

8. The memory control method according to claim 1, wherein the step of performing the data quality analysis on the first data to obtain the quality analysis result is performed by the memory control circuit inside the storage device.

9. The memory control method according to claim 8, wherein the memory control circuit includes at least two of an XOR logic gate array, a bit flip counter, and a threshold comparator to support the data quality parsing.

10. A storage device, characterized in that, include: Connection interface, used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to: Read the first data from the first physical unit of the memory module; After obtaining the first data from the memory module, without performing a decoding operation on the first data through the decoding circuit, data quality analysis is performed on the first data to obtain a quality analysis result. The operation of the memory controller performing the data quality analysis on the first data to obtain the quality analysis result includes: According to a first logical unit, reference data is read from a management table, wherein the first logical unit is mapped to a first entity unit, the reference data includes feature data corresponding to the first data, and the feature data is obtained by performing feature extraction on the first data during storage; and The first data is compared with the reference data to obtain the quality analysis result; If the quality analysis result is the first result, a reread operation is directly initiated for the first physical unit to reread the first physical unit using a reread voltage to obtain the second data; and If the quality analysis result is the second result, the decoding operation is performed on the first data through the decoding circuit.

11. The storage device of claim 10, wherein the operation of the memory controller comparing the first data with the reference data to obtain the quality resolution result includes: The first data is compared with reference data to obtain a first evaluation value, wherein the first evaluation value reflects the degree of difference between the first data and the reference data; as well as The quality analysis result is obtained based on the numerical relative relationship between the first evaluation value and the critical value.

12. The storage device of claim 10, wherein the operation of the memory controller comparing the first data with the reference data to obtain the quality resolution result includes: Based on the first logic unit, determine the dynamic sampling window; Target data is determined from the first data based on the dynamic sampling window; as well as The target data is compared with the reference data to obtain the quality analysis result.

13. The storage device of claim 10, wherein the operation of the memory controller performing the data quality analysis on the first data to obtain the quality analysis result includes: A parity check is performed on the first data to obtain a second evaluation value, wherein the parity check is not performed by the decoding circuit. as well as The quality analysis results are obtained based on the second evaluation value.

14. The storage device of claim 10, wherein the memory controller is further configured to: After obtaining the second data, the first data and the second data are compared to obtain a comparison result; and Based on the comparison results, the rereading voltage is adjusted.

15. The storage device of claim 14, wherein the operation of the memory controller adjusting the reread voltage based on the comparison result includes: If the comparison result reflects an increase in the data difference between the first data and the second data, the voltage adjustment direction of the reread voltage is changed.

16. The storage device of claim 10, wherein the memory controller is further configured to: After obtaining the second data, without performing the decoding operation on the second data through the decoding circuit, the data quality analysis is performed on the second data to update the quality analysis result; If the updated quality analysis result is the first result, the reread operation for the first entity unit is restarted. as well as If the updated quality analysis result is the second result, the decoding operation is performed on the second data through the decoding circuit.

17. The storage device of claim 10, wherein the operation of the memory controller performing the data quality analysis on the first data to obtain the quality analysis result is performed by a memory control circuit inside the memory controller.

18. The storage device of claim 17, wherein the memory control circuitry includes at least two of an XOR gate array, a bit-flip counter, and a threshold comparator to support the data quality parsing.

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