A level shift circuit for sub-nanosecond transmission delay of GaN gate drive chip

Abstract

The application discloses a sub-nanosecond transmission delay level shift circuit for a GaN gate driving chip, and relates to the technical field of gallium nitride half-bridge gate driving chip. The application is based on a traditional level shift circuit, two auxiliary capacitors are additionally added in two pulse control branch nodes of a level shift main circuit, and charging and discharging logic control is realized through a capacitor control circuit; the timing characteristics of a narrow pulse signal are utilized to actively charge the capacitor in a signal transmission stage to accelerate node voltage establishment, and the capacitor is rapidly discharged in a noise interference stage to compensate for the voltage drop caused by common-mode noise, so that the anti-noise capability and signal transmission efficiency are synergistically optimized. The efficient and stable operation of a GaN power device under high-frequency working conditions is ensured.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride half-bridge gate driver chip technology, and in particular to a level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips. Background Technology

[0002] Compared to traditional silicon-based devices, gallium nitride high electron mobility transistors (GaN HEMTs) have superior performance and are better suited for operation at high power supply voltages, high switching speeds, and high operating frequencies.

[0003] In a half-bridge topology, the power transistor's switching causes the output voltage to float. Since the high-side drive circuit's power supply voltage relies on a bootstrap capacitor, this also causes the high-side drive circuit's power supply voltage to fluctuate. However, when the high-side drive circuit's floating power supply voltage changes, the laterally diffused metal-oxide-semiconductor (LDMOS) has a large drain-to-ground parasitic capacitance, preventing its drain potential from responding promptly to the floating voltage change. This results in a voltage drop and the formation of a floating power rail dV / dt, which can severely damage the drive circuit by causing false triggering. GaN devices, with switching frequencies reaching MHz, have rapid turn-on and turn-off, resulting in even more severe floating power rail dV / dt noise. In high-frequency switching scenarios, significant signal transmission delays can cause the drive signal and the power transistor's switching action to become asynchronous. This prevents the power transistor from turning on and off at the optimal time, increasing switching losses and reducing circuit efficiency. Furthermore, the signal lag caused by the delay can lead to erratic power transistor operation, generating voltage and current spikes that threaten device safety.

[0004] Currently, level shifting circuits adapted for GaN devices mainly face the problems of insufficient common-mode noise suppression and large signal transmission delays. Traditional level shifting circuits typically rely solely on transistor switching logic to achieve level conversion (as shown in Figure 1), without designing a specific suppression mechanism for common-mode noise caused by sudden voltage changes on the floating power rail. When the potential response at the drain of the LDMOS lags due to parasitic capacitance, the voltage change between the power rail VDDH and ground will generate a significant voltage drop at the circuit node. Existing solutions cannot quickly compensate for this voltage drop, which can easily lead to distortion of the drive signal or false triggering, especially under high-frequency conditions where the noise impact is further amplified. In addition, the signal transmission path relies on the timing control of transistor cascaded conduction, lacking a means to actively accelerate signal transmission. In high-frequency switching scenarios, the interaction between transistor switching speed and parasitic parameters of the signal transmission path (such as resistance and capacitance) leads to increased signal rise / fall delay, making it difficult to meet the nanosecond-level drive signal synchronization requirements of GaN devices. For example, when a wide input pulse signal is converted into a high-frequency narrow pulse by a narrow pulse generation circuit, the node voltage of a traditional circuit is slow to build up and cannot complete the level conversion in time, resulting in a mismatch between the drive signal and the switching action of the power transistor.

[0005] Therefore, the level shifting circuit adapted to GaN devices must have noise immunity and low latency characteristics to ensure that the drive signal can be transmitted quickly and accurately, so that the power transistor can operate efficiently and stably. Summary of the Invention

[0006] This invention provides a level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips, to solve the problem that existing level shifting circuits cannot meet the noise immunity and low delay characteristics requirements of GaN devices.

[0007] This invention is achieved through the following technical solution: This invention provides a level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips, comprising: A narrow pulse generation circuit is used to generate a first low-voltage narrowband pulse signal and a second low-voltage narrowband pulse signal. The level shifting main circuit is used to receive the first low-voltage narrowband pulse signal and the second low-voltage narrowband pulse signal, and to control the switching transistor in the level shifting circuit based on the first low-voltage narrowband pulse signal and the second low-voltage narrowband pulse signal to convert the low-voltage signal into a high-voltage signal. The level shifting main circuit includes a first auxiliary capacitor and a second auxiliary capacitor. The first auxiliary capacitor is connected across the nodes in the level shifting main circuit that are related to the capacitor control circuit, and the second auxiliary capacitor is connected across the nodes in the level shifting main circuit that are related to the capacitor control circuit. A capacitor control circuit is used to control the first auxiliary capacitor to charge when the first low-voltage narrowband pulse signal is valid and to discharge when common-mode noise is generated; and to control the second auxiliary capacitor to charge when the second low-voltage narrowband pulse signal is valid and to discharge when common-mode noise is generated.

[0008] The level shifting circuit proposed in this invention adds two auxiliary capacitors to the two pulse control branch nodes of the level shifting main circuit, and implements charging and discharging logic control through a capacitor control circuit. By utilizing the timing characteristics of narrow pulse signals, the auxiliary capacitors are actively charged during the signal transmission stage to accelerate the establishment of node voltage, and rapidly discharged during the noise interference stage to compensate for the voltage drop caused by common-mode noise. This achieves synergistic optimization of noise immunity and signal transmission efficiency, ensuring the efficient and stable operation of GaN power devices under high-frequency conditions.

[0009] In some embodiments, the first low-voltage narrowband pulse signal is the rising edge of the narrow pulse signal output by the narrow pulse generation circuit, and the second low-voltage narrowband pulse signal is the falling edge of the narrow pulse signal output by the narrow pulse generation circuit.

[0010] In some embodiments, the level shifting main circuit includes an input gate drive circuit and an output gate drive circuit. The input gate drive circuit includes NMOS transistors MN1~MN4, Zener diodes Z1~Z4, resistors R1~R4, a first auxiliary capacitor C1, and a second auxiliary capacitor C2. The output gate drive circuit includes NMOS transistors MN5~MN8, PMOS transistors MP1~MP4, and inverters INV1 and INV2.

[0011] In some embodiments, in the input area gate drive circuit, the gate of MN1 is connected to the first low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the gate of MN2 is connected to the second low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the drain of MN1 is connected to the source of LD1, the drain of MN2 is connected to the source of LD2, and the sources of MN1 and MN2 are grounded. The drain of LD1 is connected to the source of MN3, the gate of MN4, the anode of Z3 and one end of resistor R3, respectively. The drain of LD2 is connected to the source of MN4, the gate of MN3, the anode of Z4 and one end of resistor R4, respectively. The gates of LD1 and LD2 are connected to the low-voltage power supply VDD. The drain of MN3 is connected to one end of resistor R1 and the anode of Z1, respectively. The drain of MN4 is connected to one end of resistor R2 and the anode of Z2, respectively. The cathodes of Z1, Z2, Z3, and Z4, the other ends of resistors R1, R2, R3, and R4 are connected to the floating power rail VDDH. The first terminal of the first auxiliary capacitor C1 is connected to the drain of MN3, the first terminal of the second auxiliary capacitor C2 is connected to the drain of MN4, and the second terminals of the first auxiliary capacitor C1 and the second auxiliary capacitor C2 are respectively connected to the capacitor control circuit.

[0012] In some embodiments, in the output area gate drive circuit, the gate of MP1 and the gate of MP2 are connected to the first terminal of the first auxiliary capacitor C1, the drain of MP1 is connected to the gate and drain of MN5 and the gate of MN6, respectively, and the drain of MP2 is connected to the drain of MN7, the gate and drain of MN8, the anode of INV1 and the cathode of INV2, respectively. The gates of MP3 and MP4 are connected to the first terminal of the second auxiliary capacitor C2. The drain of MP3 is connected to the drain of MN6, the cathode of INV1 and the anode of INV2, respectively. The drain of MP4 is connected to the gate and drain of MN8, respectively. The sources of MP3, MP4, MP5 and MP6 are connected to the floating power rail VDDH, and the sources of MN5, MN6, MN7 and MN8 are connected to the floating ground VSW.

[0013] In some embodiments, the level shifting circuit further includes a floating power rail to ground path; the floating power rail to ground path is connected to the narrow pulse generation circuit and the capacitor control circuit respectively, and is used to receive and simulate the signal transmission process of the first low-voltage narrowband pulse signal and the second low-voltage narrowband pulse signal in the level shifting main circuit, as well as the effect of common-mode noise caused by sudden changes in the floating power rail voltage on the level shifting main circuit; and apply the simulation results to the charging and discharging control logic of the capacitor control circuit.

[0014] In some embodiments, the floating power rail to ground path includes NMOS transistors MN9-MN12, NLDMOS transistors LD3 and LD4, Zener diodes Z5 and Z6, and resistors R5-R8; wherein, The gate of MN9 is connected to the first low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the gate of MN10 is connected to the second low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the drain of MN9 is connected to the source of LD3, the drain of MN10 is connected to the source of LD4, and the sources of MN9 and MN10 are grounded. The drain of LD3 is connected to the source of MN11, the gate of MN12, the anode of Z5 and one end of resistor R7, respectively. The drain of LD4 is connected to the source of MN12, the gate of MN11, the anode of Z6 and one end of resistor R8, respectively. The gates of LD3 and LD4 are connected to the low-voltage power supply VDD. The drain of MN11 is connected to one end of resistor R5, and the drain of MN13 is connected to one end of resistor R6; the cathodes of Z5 and Z6, the other ends of resistors R5, R6, R7, and R8 are connected to the floating power rail VDDH.

[0015] In some implementations, the aspect ratio of MN9 is greater than that of MN1; the aspect ratio of MN10 is greater than that of MN2.

[0016] In some embodiments, the capacitor control circuit includes NMOS transistors MN13~MN20, PMOS transistors MP5~MP10, and resistors R9 and R10; wherein, The gates of MN13 and MP5 are connected to the gate of MN12. The drain of MN13 is connected to one end of resistor R9. The drain of MP5 is connected to the other end of resistor R9, the gate of MN14, and the gate of MN18. The source of MN13 is connected to the floating ground VSW. The source of MP5 is connected to the floating power rail VDDH. The gates of MN17 and MP8 are connected to the gate of MN11. The drain of MN17 is connected to one end of resistor R10. The drain of MP8 is connected to the other end of resistor R10, the gate of MN15, and the gate of MN19. The source of MN17 is connected to the floating ground VSW, and the source of MP8 is connected to the floating power rail VDDH. The gate of MP6 is connected to the gate of MN12. The drain of MP6 is connected to the gate of MN16, the gate of MP7 and the drain of MN14 respectively. The source of MN14 is connected to the drain of MN15. The sources of MN15 and MN16 are connected to the floating ground VSW. The drain of MN16 is connected to the drain of MN7. The sources of MN6 and MN7 are connected to the floating power rail VDDH. The gate of MP9 is connected to the gate of MN11. The drain of MP9 is connected to the gate of MN20, the gate of MP10, and the drain of MN18. The source of MN18 is connected to the drain of MN19. The sources of MN19 and MN20 are connected to the floating ground VSW. The drain of MN20 is connected to the drain of MP10. The sources of MP9 and MP10 are connected to the floating power rail VDDH.

[0017] Compared with the prior art, the present invention has the following advantages and beneficial effects: By adding two auxiliary capacitors to the two pulse control branch nodes of the level shifting main circuit, and utilizing the timing characteristics of the narrow pulse signal, the auxiliary capacitors are actively charged during the signal transmission stage to accelerate the establishment of the node voltage, and rapidly discharged during the noise interference stage to compensate for the voltage drop caused by common-mode noise, thereby achieving synergistic optimization of noise immunity and signal transmission efficiency. By adding two additional floating power rails (VDDH) to ground, the signal transmission after inputting a narrow pulse signal and the impact of common-mode noise caused by sudden voltage changes in the floating power rails in the level shift circuit are simulated in advance. The simulation results are then applied to the charging and discharging control logic of the capacitor control circuit to ensure the efficient and stable operation of gallium nitride power devices. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a circuit diagram of a level shifting circuit in the prior art; Figure 2 This is a schematic diagram of a level shifting circuit applied to a GaN half-bridge driver chip; Figure 3 This is a circuit structure diagram of a level shifting circuit proposed in an embodiment of the present invention; Figure 4 This is a circuit structure diagram of another level shifting circuit proposed in an embodiment of the present invention; Figure 5 This is a circuit diagram of a floating power rail to ground path proposed in an embodiment of the present invention; Figure 6 This is a circuit diagram of a level shifting main circuit proposed in an embodiment of the present invention; Figure 7 This is a simulation diagram of the rising edge propagation delay of a level shifting circuit proposed in an embodiment of the present invention; Figure 8 This is a simulation diagram of the falling edge propagation delay of a level shifting circuit proposed in an embodiment of the present invention; Figure 9 This is the output signal waveform of a level shifter circuit without an auxiliary capacitor. Figure 10 This is the output signal waveform of a level shift circuit with an added auxiliary capacitor; Figure 11 This is a schematic diagram of the voltage difference between the two plates of an auxiliary capacitor according to an embodiment of the present invention; Figure 12 This is a circuit diagram of a capacitor control circuit proposed in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0020] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims, and accompanying drawings of this invention are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to other steps or units inherent in the device.

[0021] The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments of the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. The terms (such as those defined in commonly used dictionaries) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0022] The embodiments of the present invention provide a level shifting circuit with sub-nanosecond transmission delay, which is suitable for GaN half-bridge drive systems. It helps to reduce signal transmission delay, enhances common-mode noise immunity, and can be effectively adapted to high-speed gallium nitride gate drive chips.

[0023] like Figure 1 The diagram shown is a circuit schematic of a level shifting circuit for a GaN gate driver chip, as described in the prior art. Figure 2 The diagram shows a level shifting circuit applied to a GaN half-bridge driver chip. When this circuit is applied to a GaN half-bridge driver system, because the high-voltage region of the GaN half-bridge driver chip is powered by the bootstrap capacitor CDDH, the voltage of the floating power rail VDDH will also be raised. However, the parasitic capacitance of the NLDMOS drain to ground is very large, causing its drain voltage to fail to keep up with the changes in the floating power rail in a timely manner. This results in a voltage drop, which in turn turns on MP1, MP2, MP3, and MP4, transmitting noise to the output and causing output logic errors.

[0024] To address the above problems, this invention proposes a level shifting circuit with sub-nanosecond transmission delay. For example... Figure 3The diagram shown is a schematic diagram of a sub-nanosecond transmission delay level shifting circuit according to an embodiment of the present invention. It includes a narrow pulse generation circuit, a level shifting main circuit, and a capacitor control circuit. A first auxiliary capacitor and a second auxiliary capacitor are added to the level shifting main circuit. The charging process of the auxiliary capacitors reduces signal transmission delay, and the discharging process enhances the anti-common-mode noise capability, which is effectively adapted to high-speed gallium nitride gate driver chips.

[0025] See Figure 3 As shown, when the wide pulse signal IN passes through the narrow pulse generation circuit, it outputs two low-voltage narrow-band pulse signals. The first low-voltage narrow-band pulse signal IN1 is the rising edge of the narrow pulse signal output by the narrow pulse generation circuit, and the second low-voltage narrow-band pulse signal IN2 is the falling edge of the narrow pulse signal.

[0026] The first auxiliary capacitor C1 is connected across the nodes in the level shifting main circuit that are related to the capacitor control circuit path, and the second auxiliary capacitor C2 is connected across the nodes in the level shifting main circuit that are related to the capacitor control circuit path. The capacitor control circuit controls the first auxiliary capacitor C1 to charge when the first low-voltage narrowband pulse signal is valid, thereby reducing signal transmission delay, and to discharge when common-mode noise occurs, suppressing common-mode noise. Similarly, the second auxiliary capacitor C2 is controlled to charge when the second low-voltage narrowband pulse signal is valid, reducing signal transmission delay, and to discharge when common-mode noise occurs, suppressing common-mode noise. This achieves synergistic optimization of noise immunity and signal transmission efficiency.

[0027] In some implementations, such as Figure 4 As shown, Figure 4 The circuit diagram shows a level shifting circuit comprising two floating power rail to ground paths. The floating power rail to ground paths are connected to a narrow pulse generation circuit and a capacitor control circuit, respectively, to receive and simulate the signal transmission process of the first and second low-voltage narrowband pulse signals in the level shifting main circuit, as well as the impact of common-mode noise on the level shifting main circuit caused by sudden voltage changes in the floating power rails; and the simulation results are applied to the charging and discharging control logic of the capacitor control circuit.

[0028] See Figure 5 As shown, Figure 5 The circuit diagram of a floating power rail to ground path according to an embodiment of the present invention is shown. The floating power rail to ground path includes NMOS transistors MN9~MN12, NLDMOS transistors LD3 and LD4, Zener diodes Z5 and Z6, and resistors R5~R8.

[0029] Among them, the gate of MN9 is connected to the first low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the gate of MN10 is connected to the second low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the drain of MN9 is connected to the source of LD3, the drain of MN10 is connected to the source of LD4, and the sources of MN9 and MN10 are grounded. The drain of LD3 is connected to the source of MN11, the gate of MN12, the anode of Z5, and one end of resistor R7, respectively. The drain of LD4 is connected to the source of MN12, the gate of MN11, the anode of Z6, and one end of resistor R8, respectively. The gates of LD3 and LD4 are connected to the low-voltage power supply VDD.

[0030] The drain of MN11 is connected to one end of resistor R5, and the drain of MN13 is connected to one end of resistor R6; the cathodes of Z5 and Z6, the other ends of resistors R5, R6, R7, and R8 are connected to the floating power rail VDDH.

[0031] See Figure 6 As shown, Figure 6 The diagram illustrates a circuit schematic of a level-shifting main circuit according to an embodiment of the present invention. The level-shifting main circuit can be divided into an input gate drive circuit on the left and an output gate drive circuit on the right. The input gate drive circuit includes NMOS transistors MN1~MN4, Zener diodes Z1~Z4, resistors R1~R4, a first auxiliary capacitor C1, and a second auxiliary capacitor C2; the output gate drive circuit includes NMOS transistors MN5~MN8, PMOS transistors MP1~MP4, and inverters INV1 and INV2.

[0032] In this circuit, the gate of MN1 is connected to the first low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the gate of MN2 is connected to the second low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the drain of MN1 is connected to the source of LD1, the drain of MN2 is connected to the source of LD2, and the sources of MN1 and MN2 are grounded.

[0033] The drain of LD1 is connected to the source of MN3, the gate of MN4, the anode of Z3, and one end of resistor R3, respectively. The drain of LD2 is connected to the source of MN4, the gate of MN3, the anode of Z4, and one end of resistor R4, respectively. The gates of LD1 and LD2 are connected to the low-voltage power supply VDD.

[0034] The drain of MN3 is connected to one end of resistor R1 and the anode of Z1, respectively. The drain of MN4 is connected to one end of resistor R2 and the anode of Z2, respectively. The cathodes of Z1, Z2, Z3, and Z4, the other end of resistor R1, the other end of resistor R2, the other end of resistor R3, and the other end of resistor R4 are connected to the floating power rail VDDH.

[0035] The first terminal of the first auxiliary capacitor C1 is connected to the drain of MN3, the first terminal of the second auxiliary capacitor C2 is connected to the drain of MN4, and the second terminals of the first auxiliary capacitor C1 and the second auxiliary capacitor C2 are respectively connected to the capacitor control circuit.

[0036] In the output area gate drive circuit, the gates of MP1 and MP2 are connected to the first terminal of the first auxiliary capacitor C1. The drain of MP1 is connected to the gate and drain of MN5 and the gate of MN6, respectively. The drain of MP2 is connected to the drain of MN7, the gate and drain of MN8, the anode of INV1 and the cathode of INV2, respectively.

[0037] The gates of MP3 and MP4 are connected to the first terminal of the second auxiliary capacitor C2. The drain of MP3 is connected to the drain of MN6, the cathode of INV1 and the anode of INV2, respectively. The drain of MP4 is connected to the gate and drain of MN8, respectively.

[0038] The sources of MP3, MP4, MP5 and MP6 are connected to the floating power rail VDDH, and the sources of MN5, MN6, MN7 and MN8 are connected to the floating ground VSW.

[0039] Furthermore, the width-to-length ratio of NMOS transistor MN9 in the floating power rail to ground path is set to be greater than the width-to-length ratio of NMOS transistor MN1 in the level shifting main circuit; and the width-to-length ratio of MN10 is greater than the width-to-length ratio of MN2.

[0040] In this invention, two additional floating power rails VDDH are provided as ground paths. The aspect ratio of MN9 and MN10 is several times that of MN1 and MN2 to ensure that when the corresponding narrow input pulse signal arrives, nodes A3 and A4 decrease faster than nodes A1 and A2. This ensures that after nodes A3 and A4 pass through the capacitor charging and discharging control circuit, nodes N1 and N2 decrease synchronously with nodes A1 and A2, controlling capacitors C1 and C2 to charge and absorb the charge of nodes B1 and B2, assisting in the pull-down of nodes B1 and B2, thus reducing circuit transmission delay. The transmission delay of the level shifting circuit proposed in this invention is as follows: Figure 7 , Figure 8 As shown. Figure 7 The rise-edge propagation delay is 870ps, including a 160ps delay from the narrow pulse generation circuit. Figure 8 The falling edge propagation delay is 680ps, including an 80ps delay from the narrow pulse generation circuit; the voltage across the capacitor is then charged to VDDH-VSW.

[0041] When negative dV / dt occurs, the parasitic capacitance of the NLDMOS drain to ground discharges through Zener diodes Z3-Z6, and auxiliary capacitors C1 and C2 discharge through Zener diodes Z1-Z2. The potentials of nodes B1 and B2 are higher than VDDH by one diode voltage drop. Therefore, the PMOS in the subsequent circuit does not conduct, and the noise has little impact on the circuit. When positive dV / dt occurs, nodes A3 and A4 decrease simultaneously. The capacitor charging and discharging control circuit raises the potentials of nodes N1 and N2, controlling the auxiliary capacitors C1 and C2 to discharge the charge stored in them and charge nodes B1 and B2, reducing the impact of noise on the circuit and ensuring the stability of the output signal.

[0042] Without auxiliary capacitors C1 and C2, the circuit waveform would be as follows: Figure 9 As shown. When the positive dV / dt (200V / ns) arrives, a negative spike appears in the output, indicating a logic error. Adding auxiliary capacitors C1 and C2 results in the waveform shown below. Figure 10 As shown, the voltage difference between the two plates of auxiliary capacitors C1 and C2 is as follows: Figure 11 As shown, no logical errors were found in the output.

[0043] See Figure 12 As shown, Figure 12 The circuit diagram of a capacitor control circuit according to an embodiment of the present invention is shown. The capacitor control circuit includes NMOS transistors MN13~MN20, PMOS transistors MP5~MP10, and resistors R9 and R10.

[0044] The gates of MN13 and MP5 are connected to the gate of MN12. The drain of MN13 is connected to one end of resistor R9. The drain of MP5 is connected to the other end of resistor R9, the gate of MN14, and the gate of MN18. The source of MN13 is connected to the floating ground VSW, and the source of MP5 is connected to the floating power rail VDDH.

[0045] The gates of MN17 and MP8 are connected to the gate of MN11. The drain of MN17 is connected to one end of resistor R10. The drain of MP8 is connected to the other end of resistor R10, the gate of MN15, and the gate of MN19. The source of MN17 is connected to the floating ground VSW, and the source of MP8 is connected to the floating power rail VDDH.

[0046] The gate of MP6 is connected to the gate of MN12. The drain of MP6 is connected to the gate of MN16, the gate of MP7, and the drain of MN14. The source of MN14 is connected to the drain of MN15. The sources of MN15 and MN16 are connected to the floating ground VSW. The drain of MN16 is connected to the drain of MN7. The sources of MN6 and MN7 are connected to the floating power rail VDDH.

[0047] The gate of MP9 is connected to the gate of MN11. The drain of MP9 is connected to the gate of MN20, the gate of MP10, and the drain of MN18. The source of MN18 is connected to the drain of MN19. The sources of MN19 and MN20 are connected to the floating ground VSW. The drain of MN20 is connected to the drain of MP10. The sources of MP9 and MP10 are connected to the floating power rail VDDH.

[0048] Based on the level shifting circuit principle disclosed in this invention, its working principle is as follows.

[0049] When a wide pulse signal passes through the narrow pulse generation circuit, its rising edge generates a narrow pulse signal IN1, and its falling edge generates a narrow pulse signal IN2. When the low-voltage narrow pulse signal IN1 is active, NMOS transistors MN1, LD1, MN9, and LD3 are turned on. Because the width-to-length ratio of NMOS transistor MN9 is greater than that of NMOS transistor MN1, node A3 is pulled low before node A1. Subsequently, NMOS transistors MN3, MP6, and MN16 are turned on. Their B1 and N1 will be pulled low synchronously, and the low level of node N1 will control the charging of the first auxiliary capacitor C1 to reduce signal transmission delay. Similarly, NMOS transistor MN20 is used to pull low the voltage of node N2, controlling the charging of the second auxiliary capacitor C2 to reduce signal transmission delay.

[0050] When the low-voltage narrow pulse signal IN1 is valid, the voltage at the left end (N1) of the first auxiliary capacitor C1 is pulled down. Taking advantage of the fact that the voltage across the first auxiliary capacitor C1 cannot change abruptly, the first auxiliary capacitor C1 is charged through resistor R1, assisting in pulling down the voltage at the lower end of resistor R1 and reducing signal transmission delay. Subsequently, the voltage across the first auxiliary capacitor C1 is charged to VDDH-VSW.

[0051] When the low-voltage narrow pulse signal IN2 is valid, the voltage at the right end of the second auxiliary capacitor C2 is pulled low. Taking advantage of the fact that the voltage across the second capacitor C2 cannot change abruptly, the second capacitor C2 is charged through the second resistor R2, assisting in pulling down the lower end of the second resistor R2 and reducing signal transmission delay. Subsequently, the voltage across the second auxiliary capacitor C2 is charged to VDDH-VSW. When noise occurs, the LDMOS transistors have a large parasitic capacitance from the drain to ground, and their drain potential cannot respond to floating voltage changes in a timely manner, causing a voltage drop at nodes A1, A2, A3, and A4 relative to the high-voltage rail VDDH. PMOS transistors MP5 and MP8 are turned on, and nodes S1 and S2 are pulled high to VDDH. Subsequently, NMOS transistors MN14, MN15, MN18, MN19, PMOS transistors MP7 and MP10 are turned on, pulling nodes N1 and N2 high. The first capacitor C1 and the second capacitor C2 are controlled to discharge, and the charges stored in the first auxiliary capacitor C1 and the second auxiliary capacitor C2 are respectively input to the lower end of resistor R1 and resistor R2, thereby suppressing the voltage drop at nodes B1 and B2 caused by common-mode noise and reducing the impact of noise on the circuit.

[0052] Embodiments of the present invention also provide a GaN gate driving circuit, including a GaN gate driving chip and a level shifting circuit for sub-nanosecond propagation delay of the GaN gate driving chip according to any of the above embodiments.

[0053] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips, characterized in that, include: Narrow pulse generation circuit, used to generate a first low-voltage narrowband pulse signal and a second low-voltage narrowband pulse signal; The level shifting main circuit is used to receive the first low-voltage narrowband pulse signal and the second low-voltage narrowband pulse signal, and control the switching transistor in the level shifting circuit based on the first low-voltage narrowband pulse signal and the second low-voltage narrowband pulse signal to convert the low-voltage signal into a high-voltage signal suitable for GaN gate driver chips. The level shifting main circuit includes a first auxiliary capacitor and a second auxiliary capacitor. The first auxiliary capacitor is connected across the nodes in the level shifting main circuit that are related to the capacitor control circuit, and the second auxiliary capacitor is connected across the nodes in the level shifting main circuit that are related to the capacitor control circuit. A capacitor control circuit is used to control the first auxiliary capacitor to charge when the first low-voltage narrowband pulse signal is valid and to discharge when common-mode noise is generated. And control the second auxiliary capacitor to charge when the second low-voltage narrowband pulse signal is valid, and to discharge when common-mode noise is generated; The level shifting circuit also includes a floating power rail to ground path; The floating power rail to ground path is connected to the narrow pulse generation circuit and the capacitor control circuit respectively, and is used to receive and simulate the signal transmission process of the first low-voltage narrowband pulse signal and the second low-voltage narrowband pulse signal in the level shifting main circuit, as well as the effect of common-mode noise caused by sudden changes in the floating power rail voltage on the level shifting main circuit; and apply the simulation results to the charging and discharging control logic of the capacitor control circuit.

2. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 1, characterized in that, The first low-voltage narrowband pulse signal is the rising edge of the narrow pulse signal output by the narrow pulse generation circuit, and the second low-voltage narrowband pulse signal is the falling edge of the narrow pulse signal output by the narrow pulse generation circuit.

3. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 1, characterized in that, The level shifting main circuit includes an input gate drive circuit and an output gate drive circuit. The input gate drive circuit includes NMOS transistors MN1~MN4, Zener diodes Z1~Z4, resistors R1~R4, a first auxiliary capacitor C1, and a second auxiliary capacitor C2. The output gate drive circuit includes NMOS transistors MN5~MN8, PMOS transistors MP1~MP4, and inverters INV1 and INV2.

4. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 3, characterized in that, In the input area gate drive circuit, the gate of MN1 is connected to the first low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the gate of MN2 is connected to the second low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the drain of MN1 is connected to the source of LD1, the drain of MN2 is connected to the source of LD2, and the sources of MN1 and MN2 are grounded. The drain of LD1 is connected to the source of MN3, the gate of MN4, the anode of Z3 and one end of resistor R3, respectively. The drain of LD2 is connected to the source of MN4, the gate of MN3, the anode of Z4 and one end of resistor R4, respectively. The gates of LD1 and LD2 are connected to the low-voltage power supply VDD. The drain of MN3 is connected to one end of resistor R1 and the anode of Z1, respectively. The drain of MN4 is connected to one end of resistor R2 and the anode of Z2, respectively. The cathodes of Z1, Z2, Z3, and Z4, the other ends of resistors R1, R2, R3, and R4 are connected to the floating power rail VDDH. The first terminal of the first auxiliary capacitor C1 is connected to the drain of MN3, the first terminal of the second auxiliary capacitor C2 is connected to the drain of MN4, and the second terminals of the first auxiliary capacitor C1 and the second auxiliary capacitor C2 are respectively connected to the capacitor control circuit.

5. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 4, characterized in that, In the output area gate drive circuit, the gates of MP1 and MP2 are connected to the first terminal of the first auxiliary capacitor C1, the drain of MP1 is connected to the gate and drain of MN5 and the gate of MN6 respectively, and the drain of MP2 is connected to the drain of MN7, the gate and drain of MN8, the anode of INV1 and the cathode of INV2 respectively. The gates of MP3 and MP4 are connected to the first terminal of the second auxiliary capacitor C2. The drain of MP3 is connected to the drain of MN6, the cathode of INV1 and the anode of INV2, respectively. The drain of MP4 is connected to the gate and drain of MN8, respectively. The sources of MP3, MP4, MP5 and MP6 are connected to the floating power rail VDDH, and the sources of MN5, MN6, MN7 and MN8 are connected to the floating ground VSW.

6. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 1, characterized in that, The floating power rail to ground path includes NMOS transistors MN9~MN12, NLDMOS transistors LD3 and LD4, Zener diodes Z5 and Z6, and resistors R5~R8; wherein... The gate of MN9 is connected to the first low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the gate of MN10 is connected to the second low-voltage narrowband pulse signal output terminal of the narrow pulse generation circuit, the drain of MN9 is connected to the source of LD3, the drain of MN10 is connected to the source of LD4, and the sources of MN9 and MN10 are grounded. The drain of LD3 is connected to the source of MN11, the gate of MN12, the anode of Z5 and one end of resistor R7, respectively. The drain of LD4 is connected to the source of MN12, the gate of MN11, the anode of Z6 and one end of resistor R8, respectively. The gates of LD3 and LD4 are connected to the low-voltage power supply VDD. The drain of MN11 is connected to one end of resistor R5, and the drain of MN13 is connected to one end of resistor R6; the cathodes of Z5 and Z6, the other ends of resistors R5, R6, R7, and R8 are connected to the floating power rail VDDH.

7. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 6, characterized in that, The width-to-length ratio of MN9 is greater than that of MN1; the width-to-length ratio of MN10 is greater than that of MN2.

8. The level shifting circuit for sub-nanosecond propagation delay in GaN gate driver chips according to claim 1, characterized in that, The capacitor control circuit includes NMOS transistors MN13~MN20, PMOS transistors MP5~MP10, and resistors R9 and R10; wherein... The gates of MN13 and MP5 are connected to the gate of MN12. The drain of MN13 is connected to one end of resistor R9. The drain of MP5 is connected to the other end of resistor R9, the gate of MN14, and the gate of MN18. The source of MN13 is connected to the floating ground VSW, and the source of MP5 is connected to the floating power rail VDDH. The gates of MN17 and MP8 are connected to the gate of MN11. The drain of MN17 is connected to one end of resistor R10. The drain of MP8 is connected to the other end of resistor R10, the gate of MN15, and the gate of MN19. The source of MN17 is connected to the floating ground VSW, and the source of MP8 is connected to the floating power rail VDDH. The gate of MP6 is connected to the gate of MN12. The drain of MP6 is connected to the gate of MN16, the gate of MP7 and the drain of MN14 respectively. The source of MN14 is connected to the drain of MN15. The sources of MN15 and MN16 are connected to the floating ground VSW. The drain of MN16 is connected to the drain of MN7. The sources of MN6 and MN7 are connected to the floating power rail VDDH. The gate of MP9 is connected to the gate of MN11. The drain of MP9 is connected to the gate of MN20, the gate of MP10, and the drain of MN18. The source of MN18 is connected to the drain of MN19. The sources of MN19 and MN20 are connected to the floating ground VSW. The drain of MN20 is connected to the drain of MP10. The sources of MP9 and MP10 are connected to the floating power rail VDDH.

9. A GaN gate driving circuit, characterized in that, Includes a GaN gate driver chip and a level shifting circuit for sub-nanosecond propagation delay for a GaN gate driver chip as described in any one of claims 1-8.

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