Thermoelectric device and method for forming thermoelectric device

Abstract

Thermoelectric devices and methods for forming thermoelectric devices are disclosed. The thermoelectric device includes a plurality of first semiconductor mesas having a first conductivity type. Further, the thermoelectric device includes a plurality of second semiconductor mesas having a second conductivity type. A first semiconductor mesa structure of the plurality of first semiconductor mesa structures and a second semiconductor mesa structure of the plurality of second semiconductor mesa structures are electrically connected in series. The thermoelectric device further includes a glass structure laterally between a first semiconductor mesa structure of the plurality of first semiconductor mesa structures and a second semiconductor mesa structure of the plurality of second semiconductor mesa structures. The glass structure laterally electrically insulates a first semiconductor mesa structure of the plurality of first semiconductor mesa structures from a second semiconductor mesa structure of the plurality of second semiconductor mesa structures.

Description

Technical Field

[0001] Examples relate to concepts for semiconductor-based thermoelectric devices, and in particular to thermoelectric devices and methods for forming thermoelectric devices. Background Art

[0002] Thermoelectric devices can be used to convert temperature differences into voltage, and vice versa. When the sides of a thermoelectric device are at different temperatures, the device can generate a voltage. Conversely, when a voltage is applied to the device, a temperature difference between the sides of the device can be generated. Thermoelectric devices can be optimized for high conversion efficiency and / or low manufacturing cost. Summary of the Invention

[0003] There may be a need to provide improved concepts for thermoelectric devices.

[0004] Some embodiments relate to a thermoelectric device. The thermoelectric device includes a plurality of first semiconductor mesa structures having a first conductivity type. In addition, the thermoelectric device includes a plurality of second semiconductor mesa structures having a second conductivity type. A first semiconductor mesa structure in the plurality of first semiconductor mesa structures and a second semiconductor mesa structure in the plurality of second semiconductor mesa structures are electrically connected in series. The thermoelectric device further includes a glass structure that is laterally located between a first semiconductor mesa structure in the plurality of first semiconductor mesa structures and a second semiconductor mesa structure in the plurality of second semiconductor mesa structures. The glass structure laterally electrically insulates the first semiconductor mesa structure in the plurality of first semiconductor mesa structures from the second semiconductor mesa structure in the plurality of second semiconductor mesa structures.

[0005] Some embodiments relate to a thermoelectric device. The thermoelectric device includes a plurality of first semiconductor mesas having a first conductivity type. In addition, the thermoelectric device includes a plurality of second semiconductor mesas having a second conductivity type. The second semiconductor mesas in the plurality of second semiconductor mesas and the first semiconductor mesas in the plurality of first semiconductor mesas are arranged alternately in at least a first lateral direction. In addition, a first lateral distance between two first semiconductor mesas in the plurality of first semiconductor mesas that are located closest to each other in the first lateral direction is different from a second lateral distance between two first semiconductor mesas in the plurality of first semiconductor mesas that are located closest to each other in a second lateral direction by more than 10% of the first lateral distance.

[0006] Some embodiments relate to a method for forming a thermoelectric device. The method includes forming a plurality of first semiconductor mesas on a first semiconductor substrate. The first semiconductor substrate has a first conductivity type. The method also includes forming a plurality of second semiconductor mesas on a second semiconductor substrate. The second semiconductor substrate has a second conductivity type. The method also includes providing a glass substrate between the first semiconductor substrate and the second semiconductor substrate. The method also includes connecting the first semiconductor substrate to the second semiconductor substrate such that at least a portion of the glass substrate is laterally located between a first semiconductor mesa of the plurality of first semiconductor mesas and a second semiconductor mesa of the plurality of second semiconductor mesas.

[0007] Some embodiments relate to a method for forming a thermoelectric device. The method includes forming a plurality of first trenches extending into a first semiconductor substrate. The first trenches of the plurality of first trenches extend along a first lateral direction. In addition, the first semiconductor substrate has a first conductivity type. The method also includes forming a plurality of second trenches extending into the first semiconductor substrate. The second trenches of the plurality of second trenches extend along a second lateral direction to form a plurality of first semiconductor mesas on the first semiconductor substrate. The method also includes forming a plurality of third trenches extending into a second semiconductor substrate. The third trenches of the plurality of third trenches extend along a third lateral direction. In addition, the second semiconductor substrate has a second conductivity type. The method also includes forming a plurality of fourth trenches extending into the second semiconductor substrate. The fourth trenches of the plurality of fourth trenches extend along a fourth lateral direction to form a plurality of second semiconductor mesas on the second semiconductor substrate. The method further includes connecting the first semiconductor substrate to the second semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Some examples of apparatus and / or methods will be described below, by way of example only, and with reference to the accompanying drawings, in which

[0009] Figure 1 shows a schematic cross-section of a portion of a thermoelectric device;

[0010] Figure 2 shows a schematic top view of a portion of another thermoelectric device;

[0011] Figure 3 A flow chart illustrating a method for forming a thermoelectric device;

[0012] Figures 4a-4n shows schematic process steps for forming a thermoelectric device;

[0013] Figure 5 A flow chart illustrating another method for forming a thermoelectric device;

[0014] Figures 6a-6g shows schematic process steps for forming a thermoelectric device;

[0015] Figures 7a-7e shows schematic process steps for forming another thermoelectric device;

[0016] Figures 8a-8e shows schematic process steps for forming another thermoelectric device;

[0017] Figures 9a-9d showing different mesa geometries; and

[0018] Figures 10a-10c Shown are perspective views for different mesa structure geometries. DETAILED DESCRIPTION

[0019] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are illustrated.In the drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0020] Therefore, although additional examples can have various modifications and alternative forms, some specific examples thereof are shown in the drawings and will be described in detail later. However, this detailed description does not limit the additional examples to the specific forms described. Additional examples can cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure. The same reference numerals throughout the description of the drawings refer to the same or similar elements, which can be implemented identically or in modified form when compared to each other while providing the same or similar functions.

[0021] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled, or via one or more intermediate elements. If two elements A and B are combined using "or", this will be understood to disclose all possible combinations, i.e., only A, only B, and A and B. An alternative term for the same combination is "at least one of A and B". The same applies to combinations of more than two elements.

[0022] The terms used herein to describe specific examples are not intended to be limited to other examples. Whenever singular forms such as "a", "an" and "the" are used and the use of only a single element is neither explicitly nor implicitly defined as mandatory, other examples may also use plural elements to implement the same function. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may use a single element or processing entity to implement the same function. It will be further understood that the terms "comprise", "comprising", "include" and / or "including", when used, specify the presence of stated features, integers, steps, operations, processes, actions, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components and / or any groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have their common meaning in the art to which the examples belong.

[0024] Figure 1 A schematic cross-section of a portion of a thermoelectric device 100 is shown. The thermoelectric device 100 includes a plurality of first semiconductor mesas 110 having a first conductivity type. In addition, the thermoelectric device 100 includes a plurality of second semiconductor mesas 120 having a second conductivity type. A first semiconductor mesa 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa 120 in the plurality of second semiconductor mesas 120 are electrically connected in series. The thermoelectric device 100 further includes a glass structure 130 that is laterally located between a first semiconductor mesa 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa 120 in the plurality of second semiconductor mesas 120. The glass structure 130 laterally electrically insulates the first semiconductor mesa 110 in the plurality of first semiconductor mesas 110 from the second semiconductor mesa 120 in the plurality of second semiconductor mesas 120.

[0025] By positioning the glass structure 130 laterally between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120, the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 can be strongly connected to the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Thus, the mechanical robustness of the thermoelectric device 100 can be increased. Furthermore, because glass typically has a relatively high melting point and a low coefficient of thermal expansion (e.g., compared to plastic), the thermoelectric device 100 can withstand higher temperatures and / or higher temperature differences between different sides of the thermoelectric device 100. Thus, the lifetime of the thermoelectric device 100 can be increased. Furthermore, due to the low electrical conductivity of glass, high electrical insulation can be provided laterally between the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Therefore, the lateral distance between a first semiconductor mesa structure 110 in the plurality of adjacent first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of adjacent second semiconductor mesas 120 can be reduced. In this way, the number of first semiconductor mesas 110 per lateral unit area and the number of second semiconductor mesas 120 per lateral unit area of ​​the thermoelectric device 100 can be increased. Therefore, the efficiency of the thermoelectric device 100 for converting a temperature difference into a voltage or vice versa can be increased.

[0026] For example, the glass structure 130 can fill more than 90% (or more than 95% or more than 99%) of the lateral space between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. For example, the glass structure 130 can fill the total lateral space between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. For example, the glass structure 130 can laterally electrically insulate the first semiconductor mesa structures 110 in the plurality of first semiconductor mesas 110 from each other. For example, the glass structure 130 can laterally electrically insulate the second semiconductor mesa structures 120 in the plurality of second semiconductor mesas 120 from each other.

[0027] For example, the thermal expansion coefficient of the glass structure 130 can be greater than 50% (or greater than 75%, greater than 80%, or greater than 90%) of the thermal expansion coefficient of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110, and / or less than 200% (or less than 175%, less than 150%, less than 125%, or less than 110%) thereof.

[0028] For example, the coefficient of thermal expansion of the glass structure 130 can be greater than 50% (or greater than 75%, greater than 80%, or greater than 90%) of the coefficient of thermal expansion of the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120, and / or less than 200% (or less than 175%, less than 150%, less than 125%, or less than 110%) thereof. In this way, the thermal expansion of the glass structure 130 can be similar to the corresponding thermal expansion of the first semiconductor mesa structure 112 and / or the second semiconductor mesa structure 120. By doing so, the mechanical stress of the thermoelectric device 100 during operation of the thermoelectric device 100 can be reduced. Therefore, a more robust thermoelectric device 100 can be provided. For example, the coefficient of thermal expansion of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 may differ from the coefficient of thermal expansion of a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 by less than 25% (or less than 10%, less than 5%, or less than 1%) of the coefficient of thermal expansion of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110.

[0029] For example, the glass structure 130 may include at least one of borosilicate glass, boron zinc glass, and low transition temperature glass. -6 K -1 and / or less than 17*10 -6 K -1 A glass material having a coefficient of thermal expansion CTE of, or consisting of, such a glass material. For example, borosilicate glass includes 3.25*10 -6 K -1 CTE, and low transition temperature Tg glass includes close to 17*10 -6 K -1 Low transition temperature Tg glasses often have high CTE, while using glasses with higher transition temperatures may require more complex temperature control. For example, borosilicate glasses including Si-O2, Al-O3, B2-O3, Na2-O, and K2-O may be used. The glass pressing process may be performed between the transition temperature Tg (glas point) and the softening point (where Tg < 10 7.6 The transition temperature of the viscosity curve between 1.5 and 2.5 dPa sec is achieved at a point in the viscosity curve between 1.5 and 2.5 dPa sec. Low transition temperature Tg glass can be a good material for precision glass forming. Boron zinc glass can have good semiconductor insulating properties and good CTE and process temperature.

[0030] The glass structure 130 may include a material such that the thermal expansion coefficient of the glass structure 130 is similar to the thermal expansion coefficient of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesa structures 110 and / or similar to the thermal expansion coefficient of the second semiconductor mesa structure 120 in the plurality of second semiconductor mesa structures 120. In this way, mechanical stress on the thermoelectric device 100 during operation of the thermoelectric device 100 can be reduced. Consequently, a more robust thermoelectric device 100 can be provided. For example, the low-transition-temperature glass may be low-Tg glass or an optical material for precision molding.

[0031] For example, the thermoelectric device 100 may further include a plurality of metallization structures 140 located on first sides of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Each of the plurality of metallization structures 140 may electrically connect a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. In this manner, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 are efficiently electrically connected in pairs. For example, a first side of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 may be a side of the thermoelectric device 100 on which the corresponding bases or corresponding plateaus of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 are located. For example, the metallization structure 140 in the plurality of metallization structures 140 may include at least one of aluminum, copper, tungsten, molybdenum, titanium, and / or titanium nitride and / or an alloy of aluminum, copper, tungsten, molybdenum, and / or titanium (e.g., titanium-tungsten (TiW)).

[0032] For example, the thermoelectric device 100 may further include a plurality of metallization structures 140 located on second sides of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Each of the plurality of metallization structures 140 may electrically connect a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 to a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 (or electrically connect a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 to a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120). In this manner, the first semiconductor mesa structures 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesa structures 120 in the plurality of second semiconductor mesas 120 are efficiently electrically connected in pairs. For example, the second side and the first side may be opposite sides of the thermoelectric device 100. For example, the metallization structures 140 of the plurality of metallization structures 140 may electrically connect a first semiconductor mesa 110 of the plurality of first semiconductor mesas 110 and a second semiconductor mesa 120 of the plurality of second semiconductor mesas 120 in series and / or in parallel.

[0033] For example, the first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 may have a maximum lateral dimension greater than 25 μm (or greater than 50 μm, greater than 75 μm, or greater than 80 μm) and / or less than 250 μm (or less than 200 μm, or less than 150 μm). In this way, the power yield of the thermoelectric device 100 may be improved.

[0034] For example, the second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can have a maximum lateral dimension greater than 25 μm (or greater than 50 μm, greater than 75 μm, or greater than 80 μm) and / or less than 250 μm (or less than 200 μm, or less than 150 μm). In this way, the power yield of the thermoelectric device 100 can be improved. For example, the first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can have the same maximum lateral dimension.

[0035] For example, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 may have a vertical dimension greater than 200 μm (or greater than 250 μm or greater than 300 μm) and / or less than 1 mm (or less than 750 μm or less than 500 μm). In this way, the power yield of the thermoelectric device 100 may be improved. For example, the vertical dimension may be the largest vertical dimension of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110.

[0036] For example, a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 can have a vertical dimension that is greater than 200 μm (or greater than 250 μm or greater than 300 μm) and / or less than 1 mm (or less than 750 μm or less than 500 μm). In this way, the power yield of the thermoelectric device 100 can be improved. For example, the vertical dimension can be the maximum vertical dimension of a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. For example, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 can have the same vertical dimension or the same maximum vertical dimension.

[0037] For example, the first semiconductor mesa structures 110 among the plurality of first semiconductor mesa structures 110 and / or the second semiconductor mesa structures 120 among the plurality of second semiconductor mesa structures 120 may be in the shape of a strip, a sheet, or a column. For example, the shape of the transverse cross-section of the first semiconductor mesa structures 110 among the plurality of first semiconductor mesa structures 110 may be selected from the group consisting of a square, a rectangle, a circle, and an ellipse. For example, the shape of the transverse cross-section of the second semiconductor mesa structures 120 among the plurality of second semiconductor mesa structures 120 may be selected from the group consisting of a square, a rectangle, a circle, and an ellipse. For example, the corners and / or sides of the first semiconductor mesa structures 110 among the plurality of first semiconductor mesa structures 110 and / or the second semiconductor mesa structures 120 among the plurality of second semiconductor mesa structures 120 may be rounded.

[0038] For example, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 may be vertically tapered. For example, a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 may be vertically tapered. For example, a width of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 may be less than 90% (or less than 75%, less than 50%, or less than 25%) of a length of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110. A width of a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 may be less than 90% (or less than 75%, less than 50%, or less than 25%) of a length of the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120.

[0039] For example, the minimum lateral distance between two first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 can be less than 150% (or less than 125% or less than 110%) of the maximum lateral dimension of a first semiconductor mesa 110 in the plurality of first semiconductor mesas 110. In this way, the first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 can be more densely packed within the thermoelectric device 100. In this way, the conversion efficiency of the thermoelectric device 100 can be increased.

[0040] For example, the minimum lateral distance between two second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be less than 150% (or less than 125% or less than 110%) of the maximum lateral dimension of a second semiconductor mesa 120 in the plurality of second semiconductor mesas 120. In this way, the second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be more densely packed within the thermoelectric device 100. In this way, the conversion efficiency of the thermoelectric device 100 can be increased.

[0041] For example, the minimum lateral distance between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120 can be less than 75% (or less than 50%, less than 25%, or less than 10%) of the maximum lateral dimension of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and / or less than 75% (or less than 50%, less than 25%, or less than 10%) of the maximum lateral dimension of the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. In this way, the first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be more densely packed within the thermoelectric device 100. In this way, the conversion efficiency of the thermoelectric device 100 can be increased.

[0042] For example, the plurality of first semiconductor mesas 110 may include more than 5 (or more than 10, more than 50, more than 100, more than 500, or more than 1000) first semiconductor mesas 110. For example, the plurality of second semiconductor mesas 120 may include more than 5 (or more than 10, more than 50, more than 100, more than 500, or more than 1000) second semiconductor mesas 120. For example, the first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 may be distributed over the entire lateral area of ​​the thermoelectric device 100. For example, the thermoelectric device 100 may have a lateral dimension of more than 500 μm (or more than 1 mm, more than 2.5 mm, more than 5 mm, or more than 10 mm). For example, a first semiconductor mesa 110 among the plurality of first semiconductor mesas 110 and an adjacent second semiconductor mesa 120 among the plurality of second semiconductor mesas 120 may form a thermocell, a micro generator unit, a thermoelectric element, or a thermoelectric unit.

[0043] For example, the thermoelectric device 100 may be a thermoelectric generator, a Seebeck generator, a microgenerator, a thermoelectric cooler, a thermoelectric heater, a Peltier device, a Peltier cooler, a Peltier heater, a thermoelectric heat pump, or a solid-state refrigerator.

[0044] For example, the first side and the second side of the thermoelectric device 100 may be at different temperatures, and a voltage may be generated according to the Seebeck effect due to the different conductivity types of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. For example, the generated voltage may be used to power a sensor, an actor, or a wireless device.

[0045] For example, the first semiconductor mesa structure 110 of the plurality of first semiconductor mesas 110 and / or the second semiconductor mesa structure 120 of the plurality of second semiconductor mesas 120 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), and bismuth telluride (Bi2Te3). For example, the semiconductor mesa structure having the first conductivity type may be an n-doped semiconductor mesa structure (e.g., caused by the incorporation of nitrogen ions, phosphorus ions, or arsenic ions) or a p-doped semiconductor mesa structure (e.g., caused by the incorporation of aluminum ions or boron ions). Therefore, the second conductivity type indicates the opposite p-doped semiconductor mesa structure or n-doped semiconductor mesa structure. In other words, the first conductivity type may indicate p-doping, and the second conductivity type may indicate n-doping, or vice versa.

[0046] Figure 2 A schematic top view of a portion of another thermoelectric device 200 is shown. Thermoelectric device 200 includes a plurality of first semiconductor mesas 110 having a first conductivity type. Furthermore, thermoelectric device 200 includes a plurality of second semiconductor mesas 120 having a second conductivity type. Second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 and first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 are arranged alternately in at least a first lateral direction 210. In addition, a first lateral distance 220 between two first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 that are located closest (to each other) in the first lateral direction 210 is different from a second lateral distance 230 between two first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 that are located closest (to each other) in the second lateral direction 240 by more than 10% (or more than 25%, more than 50%, more than 100%, more than 250%, or more than 500%) of the first lateral distance 220.

[0047] Due to the difference between first lateral distance 220 and second lateral distance 230, first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 and second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be more densely packed within thermoelectric device 200. For example, first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 and second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be arranged in parallel rows in second lateral dimension 240. In this way, the conversion efficiency of thermoelectric device 200 can be increased.

[0048] For example, the minimum distance between two first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 in the first lateral direction 210 may differ from the minimum distance between two first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 in the second lateral direction 220 by more than 10% (or more than 25%, more than 50%, more than 100%, more than 250%, or more than 500%) of the minimum distance between two first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 in the first lateral direction 210. For example, a third lateral distance between two adjacent second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 in the first lateral direction 210 may differ from a fourth lateral distance between two adjacent second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 in the second lateral direction 240 by more than 10% (or more than 25%, more than 50%, more than 100%, more than 250%, or more than 500%) in the third lateral direction 210. For example, a minimum distance between two second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 in the first lateral direction 210 may differ from a minimum distance between two second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 in the second lateral direction 220 by more than 10% (or more than 25%, more than 50%, more than 100%, more than 250%, or more than 500%) of the minimum distance between two second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 in the first lateral direction 210. For example, the first lateral direction 210 may be perpendicular to the second lateral direction 240.

[0049] For example, the thermoelectric device 200 may further include an insulating structure laterally located between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. The insulating structure may laterally electrically insulate a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 from a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Due to the lateral electrical insulation provided by the insulating structure, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 may be located closer to a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. In this way, the conversion efficiency of the thermoelectric device 200 may be increased.

[0050] For example, the insulating structure may fill more than 90% (or more than 95% or more than 99%) of the lateral space between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. The insulating structure may fill the total lateral space between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. For example, the insulating structure may laterally electrically insulate the first semiconductor mesa structures 110 in the plurality of first semiconductor mesas 110 from each other, and / or the insulating structure may laterally electrically insulate the second semiconductor mesa structures 120 in the plurality of second semiconductor mesas 120 from each other. For example, the insulating structure may include at least one of glass, glue, plastic, and a thin sheet. For example, the insulating structure may form the glass structure 130.

[0051] Thermoelectric device 200 can be implemented similarly to a combination of Figure 1 Implementation of the Described Thermoelectric Device. For example, the thermoelectric device 200 can be a thermoelectric generator, a Hibeck generator, a microgenerator, a thermoelectric cooler, a thermoelectric heater, a Peltier device, a Peltier cooler, a Peltier heater, a thermoelectric heat pump, or a solid-state refrigerator.

[0052] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 2 The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1 ) or below (for example, Figure 3-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0053] Figure 3 A flow chart of a method 300 for forming a thermoelectric device is shown. Method 300 includes forming 310 a plurality of first semiconductor mesas 110 on a first semiconductor substrate. The first semiconductor substrate has a first conductivity type. Furthermore, method 300 includes forming 320 a plurality of second semiconductor mesas 120 on a second semiconductor substrate. The second semiconductor substrate has a second conductivity type. Method 300 also includes providing 330 a glass substrate between the first semiconductor substrate and the second semiconductor substrate. Furthermore, method 300 includes connecting 340 the first semiconductor substrate to the second semiconductor substrate (or connecting 340 the first semiconductor substrate to the second semiconductor substrate) such that at least a portion of the glass substrate is laterally located between a first semiconductor mesa 110 of the plurality of first semiconductor mesas 110 and a second semiconductor mesa 120 of the plurality of second semiconductor mesas 120.

[0054] By connecting the first semiconductor substrate to the second semiconductor substrate such that at least a portion of the glass substrate is laterally located between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 can be strongly connected to a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Consequently, a thermoelectric device with increased mechanical stability can be formed. Furthermore, due to the low electrical conductivity of glass, high lateral electrical insulation can be provided between a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Consequently, the lateral distance between adjacent first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 and second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be reduced. In this way, the number of first semiconductor mesas 110 per lateral unit area and the number of second semiconductor mesas 120 per lateral unit area of ​​the thermoelectric device can be increased. Thus, a thermoelectric device with increased efficiency for converting a temperature difference into a voltage or vice versa can be formed. The method 300 can be used to form a combined Figure 1 Thermoelectric devices described and / or combinations thereof Figure 2 A thermoelectric device is described.

[0055] For example, the first semiconductor substrate and / or the second semiconductor substrate may be a semiconductor wafer or a semiconductor die. The semiconductor material of the first semiconductor substrate and / or the second semiconductor substrate may be silicon (Si), germanium (Ge), silicon germanium (SiGe), or bismuth telluride (Bi2Te3). For example, a semiconductor substrate having a first conductivity type may be an n-doped semiconductor substrate (e.g., caused by the incorporation of nitrogen ions, phosphorus ions, or arsenic ions) or a p-doped semiconductor substrate (e.g., caused by the incorporation of aluminum ions or boron ions). Therefore, the second conductivity type indicates the opposite p-doped semiconductor substrate or n-doped semiconductor substrate. In other words, the first conductivity type may indicate p-doping, and the second conductivity type may indicate n-doping, or vice versa.

[0056] For example, first semiconductor mesas 110 in the plurality of first semiconductor mesas 110 can be laterally separated from each other by a plurality of first recesses. For example, at least a portion of a second semiconductor mesa 120 in the plurality of second semiconductor mesas 120 can be at least partially received in a first recess in the plurality of first recesses. For example, second semiconductor mesas 120 in the plurality of second semiconductor mesas 120 can be laterally separated from each other by a plurality of second recesses. For example, at least a portion of a first semiconductor mesa 110 in the plurality of first semiconductor mesas 110 can be at least partially received in a second recess in the plurality of second recesses.

[0057] For example, connecting the first semiconductor substrate to the second semiconductor substrate 340 may be performed at a temperature greater than 350° C. (or greater than 400° C., greater than 500° C., greater than 600° C., greater than 700° C., or greater than 750° C.). In this manner, the glass wafer may be melted during connecting 340. Thus, the material of the glass wafer may efficiently fill the gaps between the first semiconductor mesa structures 110 of the plurality of first semiconductor mesas 110 and the second semiconductor mesa structures 120 of the plurality of second semiconductor mesas 120.

[0058] For example, joining 340 the first semiconductor substrate to the second semiconductor substrate can be performed at a temperature of less than 900° C. (or less than 800° C. or less than 700° C.). For example, joining 340 the first semiconductor substrate to the second semiconductor substrate can be performed under an inert atmosphere or a vacuum. For example, joining 340 the first semiconductor substrate to the second semiconductor substrate can include pressing the first semiconductor substrate against the second semiconductor substrate with a pressure greater than 1 kN (or greater than 2 kN or greater than 5 kN) and less than 20 kN (or less than 15 kN or less than 10 kN), or with a pressure greater than 125 kPa (or greater than 300 kPa or greater than 600 kPa) and / or less than 2500 kPa (or less than 1900 kPa or less than 1200 kPa). For example, the first semiconductor substrate can be joined 340 to the second semiconductor substrate under an inert atmosphere (e.g., an argon (Ar) atmosphere or a nitrogen (N2) atmosphere) and / or under negative pressure or a vacuum to avoid or reduce oxidation.

[0059] For example, connecting the first semiconductor substrate 340 to the second semiconductor substrate can be accomplished by a glass forming process or a precision glass forming process. For example, the glass substrate can be a glass wafer or a glass foil. For example, the material of the glass substrate can be borosilicate glass (e.g., Borofloat 33 or MEMpax), boron zinc glass, or a low transition temperature glass. For example, the glass substrate includes a glass having a thickness greater than 2*10 -6 K -1 and / or less than 17*10 -6 K-1 A glass material having a coefficient of thermal expansion CTE of, or consisting of, such a glass material. For example, borosilicate glass includes 3.25*10 -6 K -1 CTE, and low transition temperature Tg glass includes close to 17*10 -6 K -1 Low transition temperature Tg glasses often have high CTE, while using glasses with higher transition temperatures may require more complex temperature control. For example, borosilicate glasses including Si-O2, Al-O3, B2-O3, Na2-O, and K2-O may be used. The glass pressing process may be performed between the transition temperature Tg (glas point) and the softening point (where Tg < 10 7.6 The transition temperature of the viscosity curve between 0.1°C and 0.1°C (dPasec) is achieved at the transition temperature. Low-transition-temperature Tg glass can be a good material for precision glass forming. Boron-zinc glass can have good semiconductor insulating properties and good CTE and process temperature.

[0060] For example, forming 310 a plurality of first semiconductor mesas 110 includes forming at least one recess or at least one trench in the first semiconductor substrate. The at least one recess or at least one trench in the first semiconductor substrate can be formed by at least one of an etching process, a sawing process, a water jet cutting process, and a laser slicing process. In this way, the plurality of first semiconductor mesas 110 can be formed cost-effectively. For example, the etching process can include a wet etching process, a dry etching process, or a plasma etching process.

[0061] For example, forming 320 of the plurality of second semiconductor mesas 120 includes forming at least one recess or at least one trench in the second semiconductor substrate. The at least one recess or at least one trench in the second semiconductor substrate can be formed by at least one of an etching process, a sawing process, a water jet cutting process, and a laser slicing process. In this way, the plurality of second semiconductor mesas 120 can be formed cost-effectively.

[0062] For example, the method 300 may further include removing a portion of the first semiconductor substrate after connecting the first semiconductor substrate to the second semiconductor substrate 340, so as to separate the first semiconductor mesas 110 from each other in the plurality of first semiconductor mesas 110. For example, removing the portion of the first semiconductor substrate may include thinning the first semiconductor substrate until it is not covered by the material of the glass substrate. For example, the portion may be removed by a grinding process.

[0063] For example, the method 300 may further include removing a portion of the second semiconductor substrate after connecting the first semiconductor substrate to the second semiconductor substrate 340, so as to separate the second semiconductor mesas 120 from each other in the plurality of second semiconductor mesas 120. For example, removing the portion of the second semiconductor substrate may include thinning the second semiconductor substrate until it is not covered by the material of the glass substrate. For example, the portion may be removed by a grinding process.

[0064] For example, the method 300 may further include forming a plurality of metallization structures 140 on a first side and / or a second side of a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. Each of the plurality of metallization structures 140 may electrically connect a first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. For example, forming the plurality of metallization structures 140 may include depositing a metallization layer on the first side and / or the second side and structuring the deposited metallization layer. For example, the deposited metallization layer may be structured using an etching process. For example, forming the plurality of metallization structures 140 may include structuring the deposited metallization structure 140 on the first side and / or the second side. For example, the plurality of metallization structures 140 may be formed after removing a portion of the first semiconductor substrate and / or after removing a portion of the second semiconductor substrate.

[0065] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 3 The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-2 ) or below (for example, Figures 4a-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0066] Figures 4a-4n Schematic process steps for forming thermoelectric device 400 are shown. The method for forming thermoelectric device 400 can be similar to that of combining Figure 3 Described method. Figure 4a A process step is shown in which a first semiconductor substrate 410 and a second semiconductor substrate 420 are provided. For example, the first semiconductor substrate 410 may be an n-doped silicon wafer and the second semiconductor substrate 420 may be a p-doped silicon wafer.

[0067] Figure 4aAn example is shown of n-doped and p-doped silicon (Si) wafers provided with thermal oxide on their surfaces. By using two differently doped silicon wafers (n- and p-Si), a basic setup for a thermoelectric device 400 or micro-generator can be achieved. Regarding further processing for producing microstructures in the silicon surface, three different variants can be used. A first variant can include masking (e.g., of the wafer) using a hard mask, anisotropic wet chemical etching (e.g., of the masked wafer), and removing the mask (e.g., from the wafer). A second variant can include masking (e.g., of the wafer) using a hard mask, plasma etching (e.g., of the masked wafer), such as by a BOSCH process, and removing the mask (e.g., from the wafer). A third variant can include mechanical sawing (e.g., of the wafer) in a checkerboard pattern.

[0068] Figures 4b to 4d Schematic process steps for forming 310 first semiconductor mesas 110 in a first semiconductor substrate 410 and for forming 320 second semiconductor mesas 120 in a second semiconductor substrate 420 using an etching process are shown. Figure 4b As shown in FIG, a patterned hard mask 430 is formed on a first semiconductor substrate 410 and a second semiconductor substrate 420. After forming the patterned hard mask 430, the first semiconductor substrate 410 and the second semiconductor substrate 420 are etched to form a plurality of first semiconductor mesas 110 in the first semiconductor substrate 410 and a plurality of second semiconductor mesas 120 in the second semiconductor substrate 420, as shown in FIG. Figure 4c As shown in FIG. The first semiconductor mesa structure 110 of the plurality of first semiconductor mesa structures 110 and the second semiconductor mesa structure 120 of the plurality of second semiconductor mesa structures 120 have a shape of a truncated pyramid. In the following process steps, the patterned hard mask 430 is removed from the first semiconductor substrate 410 and the second semiconductor substrate 420, as shown in FIG. Figure 4d As shown in the picture.

[0069] Figures 4b to 4d The process steps shown in can relate to the first variant and the second variant. Figure 4b An example of patterned masking of two wafer surfaces is shown. For example, a hard mask can be attached to the wafer. The unmasked areas can then be etched away using anisotropic etching to a specific depth. Figure 4cAn example of pyramid depth structuring of two wafers is shown. For optimal power yield per face, the pyramid diameter can be in the range of 80 to 150 μm and the height (e.g. of the pyramid) can be in the range of 300 to 500 μm. Different crystal levels in silicon can be isolated by means of anisotropic wet chemical etching. When using 100 material (e.g. silicon material), the relevant levels can be levels 110 (45°), 100 (90°) and 111 (54, 74°). When other orientations of the basic crystal (e.g. 110) are used, anisotropic etching can be optimized in terms of its selectivity and desired crystal orientation. Therefore, in the case of anisotropic wet chemical etching, vertical flanks can be generated under certain conditions. The hard mask 430 can then be removed. Figure 4d An example of a patterned wafer is shown without a hard mask 430. In a second variant, as in the first variant, masking can be used (e.g., by lacquer and / or hard mask 430, depending on the etch depth). By using a plasma etch (e.g., a BOSCH etch), vertical trench flanks with microstructures (scallops) can be formed.

[0070] Alternatively or in addition to Figures 4b to 4d The process steps shown in Figure 4e The sawing process illustrated in FIG forms a plurality of first semiconductor mesas 110 and a plurality of second semiconductor mesas 120. A first semiconductor mesa 110 of the plurality of first semiconductor mesas 110 and a second semiconductor mesa 120 of the plurality of second semiconductor mesas 120 have a rectangular (vertical) cross section.

[0071] According to a third variant, mechanical sawing in a checkerboard pattern can be performed. The third variant can be classified as the most cost-effective of the three variants. The first and third variants can be more cost-effective than the second variant. Figure 4e An example of a wafer surface patterned by means of a sawing process is shown.For optimal efficiency, a small mesa diameter may be desired, whereas the mesa length may be sufficient for the temperature gradient.

[0072] For example, the first semiconductor wafer 410 and the second semiconductor wafer 420 may be a carrier or substrate. For example, when the plurality of first semiconductor mesas 110 and the plurality of second semiconductor mesas 120 are formed by a sawing process, their sidewalls may be formed at an angle or vertically (e.g., with respect to the surface of the first semiconductor substrate 410 or the surface of the second semiconductor substrate 420). For example, when the plurality of first semiconductor mesas 110 and the plurality of second semiconductor mesas 120 are formed by a wet etching process, their sidewalls may be formed at an angle or vertically (e.g., with respect to the surface of the first semiconductor substrate 410 or the surface of the second semiconductor substrate 420). For example, when the plurality of first semiconductor mesas 110 and the plurality of second semiconductor mesas 120 are formed by a BOSCH etching process, their sidewalls may be formed vertically (e.g., with respect to the surface of the first semiconductor substrate 410 or the surface of the second semiconductor substrate 420).

[0073] like Figure 4f and 4g As shown in FIG, a glass substrate 440 may be provided between a first semiconductor wafer 410 and a second semiconductor wafer 420. Figure 4f In the example shown in FIG, the glass substrate 440 is a glass wafer 441, and Figure 4g In the example shown in , the glass substrate 440 is a glass foil 442 .

[0074] You can use Figure 4g and 4g The first semiconductor wafer 410 and the second semiconductor wafer 420 are connected by a precision glass molding process as shown in FIG. Figure 4h An example is shown in which the glass material of the glass wafer 440 may be completely received in the gap between the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120. In other examples, the glass material of the glass wafer 440 may remain on top of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesas 110 and / or the second semiconductor mesa structure 120 in the plurality of second semiconductor mesas 120.

[0075] For example, the first semiconductor wafer 410 and the second semiconductor wafer 420 can be connected by pressing the first semiconductor wafer 410 toward the second semiconductor wafer 420 with a glass wafer 441 or a glass foil 442 therebetween. A glass substrate 440, i.e., the glass wafer 441 or the glass foil 442, is placed between the first semiconductor substrate 410 and the second semiconductor substrate 420. At least one of heat and pressure is applied to the glass substrate 440 to deform the glass substrate 440, causing at least a portion of the glass substrate 440 to move between a first semiconductor mesa 110 in the plurality of first semiconductor mesas 110 and a second semiconductor mesa 120 in the plurality of second semiconductor mesas 120, thereby connecting 340 the first semiconductor substrate 410 to the second semiconductor substrate 420; for example, at a temperature greater than 350° C. and less than 900° C. and / or a pressure greater than 1 kN and less than 20 kN. In this manner, the first semiconductor mesas 110 and the second semiconductor mesas 120 can be interlocked. The combined application of heat and temperature to reduce the viscosity of the glass has been successfully used. However, applying heat with less pressure or no pressure, or applying pressure at a lower temperature, can achieve similar results. This method is known as glass pressing.

[0076] In any case, the glass substrate is deformed by applying heat and / or pressure to cause glass material from the glass substrate to move between the first semiconductor mesa structure 110 and the second semiconductor mesa structure 120. The application of heat and / or pressure reduces the viscosity of the glass, and the glass material of the glass substrate can flow between the mesa structures. In the presence of deformable and liquid glass material generated by the application of heat and / or pressure, the first semiconductor wafer 410 can be moved toward the second semiconductor wafer to engage the first semiconductor mesa structure 110 and the second semiconductor mesa structure 120.

[0077] Figure 4h An example of contacting wafers with laterally positioned glass layers or glass substrates is shown. For example, the wafers (eg, the first semiconductor wafer 410 and the second semiconductor wafer 420 ) may be connected by means of a glass pressing method.

[0078] like Figure 4i As shown in FIG, a portion of the first semiconductor wafer 410 and a portion of the second semiconductor wafer 420 are removed to separate the first semiconductor mesas 110 from each other in the plurality of first semiconductor mesas 110, and to separate the second semiconductor mesas 120 from each other in the plurality of second semiconductor mesas 120. For example, the portions can be removed by a grinding process. When the material of the glass substrate 440 is lifted off, the grinding process can be stopped.

[0079] Figure 4iAn example of an isolated micro-generator unit in a wafer format is shown. For example, after achieving stability in the wafer composite, the wafer composite can be ground down at the top and bottom to render the p-region and n-region electrically isolated. For example, an intermediate structure is formed that repeatedly includes a p-doped mesa, a glass portion, an n-doped mesa, and another glass portion in a lateral direction, so that the mesa structures are electrically isolated from each other by the glass portion.

[0080] like Figure 4j As illustrated in FIG, the metallization layer 450 is deposited on both sides of the first semiconductor mesa structure 110 of the plurality of first semiconductor mesas 110 and the second semiconductor mesa structure 120 of the plurality of second semiconductor mesas 120 .

[0081] Figure 4k An example of a metallized micro-generator unit in wafer format is shown. For example, metallization can occur on both sides of the unit complex.

[0082] like Figure 4k As shown in FIG, the deposited metallization layer 450 can be structured to form a plurality of metallization structures 140. For example, in addition to the two electrical contacts 140a, 140b (see FIG. Figure 4m ), each of the plurality of metallization structures 140 electrically connects a first semiconductor mesa structure 110 in the plurality of first semiconductor mesa structures 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesa structures 120. Therefore, a first semiconductor mesa structure 110 in the plurality of first semiconductor mesa structures 110 and a second semiconductor mesa structure 120 in the plurality of second semiconductor mesa structures 120 are electrically connected in series. In this way, as Figure 4k As indicated by the arrows in , current can flow through the plurality of first semiconductor mesa structures 110 and the plurality of second semiconductor mesa structures 120 .

[0083] Figure 4k An example of a Peltier structure manufactured with the aid of silicon technology in wafer format (e.g., a series connection of many thermoelectric elements) is shown. For example, the metal layers on the top and bottom can be structured so that in each case an electrical connection can be made from a p-doped to an n-doped cell for current flow through the cell, so that the resulting current path is as long as possible.

[0084] Figure 4l Show Figure 4k. At this perspective, only the material of the glass wafer 440 and a metallization structure 140 of the plurality of metallization structures 140 are visible. The metallization structure 140 has a rectangular shape. For example, the metallization structure 140 can electrically connect adjacent first and second semiconductor mesas 110 and 120 in series, as indicated by line 455. Figure 4l An example of a top view of a Peltier structure in wafer format with contacts is shown.

[0085] like Figure 4m As shown in FIG, a coating layer 460 is deposited to provide electrical insulation. The coating layer 460 may include at least one of a molding, a ceramic, or a thermal interface material (TIM). Figure 4m Examples of electrically isolated, packaged, thermal micro-generators (e.g., thermoelectric devices) are shown. For example, Figure 4k and 4l The device or assembly shown in can be coated (eg, by a mold, ceramic, or TIM) to electrically isolate the individual thermoelectric elements, leaving two electrical contacts 140a, 140b uncovered, which can be thin and / or thermally conductive.

[0086] Figure 4n Thermoelectric device 400 is shown in operation. Thermoelectric device 400 is in contact with a heat source 470 (e.g., a person's skin or a heater element) and a cold side 480 or cooling element. A temperature difference ΔT occurs between heat source 470 and cold side 480. Metallization structure 140a can be a plus contact, and metallization structure 140b can be a ground or minus contact.

[0087] Figure 4n An example of a functional diagram of a thermoelectric device 400 is shown. For miniaturized power generators (e.g., for thermoelectric device 400), the Peltier cells can now be sawn off the wafer composite, depending on the underlying space requirements and the desired power. The generated voltage depends on the number of pairs of cells, the temperature gradient, and the Seebeck coefficient (e.g., 440 μV / K for silicon). For a wafer of only 2.5 x 2.5 mm with approximately 1000 individual cells, the Peltier cells can be sawn off the wafer composite, depending on the underlying space requirements and the desired power. The generated voltage depends on the number of pairs of cells, the temperature gradient, and the Seebeck coefficient (e.g., 440 μV / K for silicon). 2 For a cell area of ​​1.5 Å, a temperature gradient of 3 degrees Celsius at the upper and lower contacts (e.g., at the upper and lower metallization structures 140) may result in a calculated voltage of approximately 1.3 V and an electrical power in the milliwatt range. For example, further contacting to the current dissipating contacts at the corresponding metal layer may occur via a metal bonding process (e.g., using solder, diffusion solder, or sintering process paste).

[0088] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figures 4a-4nThe embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-3 ) or below (for example, Figure 5-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0089] Figure 5 A flow chart of another method 500 for forming a thermoelectric device is shown. Method 500 includes forming 510 a plurality of first trenches extending into a first semiconductor substrate 410. A first trench of the plurality of first trenches extends along a first lateral direction. Furthermore, the first semiconductor substrate 410 has a first conductivity type. Furthermore, method 500 includes forming 520 a plurality of second trenches extending into the first semiconductor substrate 410. A second trench of the plurality of second trenches extends along a second lateral direction to form a plurality of first semiconductor mesas 110 in the first semiconductor substrate 410. Method 500 also includes forming 530 a plurality of third trenches extending into a second semiconductor substrate 420. A third trench of the plurality of third trenches extends along a third lateral direction. Furthermore, the second semiconductor substrate 420 has a second conductivity type. Furthermore, method 500 includes forming 540 a plurality of fourth trenches extending into the second semiconductor substrate 420. A fourth trench of the plurality of fourth trenches extends along a fourth lateral direction to form a plurality of second semiconductor mesas 120 in the second semiconductor substrate 420. The method 500 further includes connecting 550 the first semiconductor substrate 410 with the second semiconductor substrate 420 (or connecting 550 the first semiconductor substrate 410 to the second semiconductor substrate 420 ).

[0090] Since the plurality of first semiconductor mesas 110 and the plurality of second semiconductor mesas 120 are formed in a single processing step, the thermoelectric device can be formed more cost-effectively. Figure 1 Thermoelectric devices described, combined Figure 2 Thermoelectric devices described and / or combinations thereof Figures 4a-4n A thermoelectric device is described.

[0091] For example, forming the plurality of first trenches 510, forming the plurality of second trenches 520, forming the plurality of third trenches 530, and / or forming the plurality of fourth trenches 540 may include an etching process, a sawing process, a water jet cutting process, and / or a laser slicing process. For example, the longest dimension of each trench extends along a corresponding transverse direction. For example, the first transverse direction may be perpendicular to the second transverse direction, and / or the third transverse direction may be perpendicular to the fourth transverse direction.

[0092] For example, when the first semiconductor substrate 410 and the second semiconductor substrate 420 are equally oriented during forming more than 510 first trenches, forming more than 520 second trenches, forming more than 530 third trenches, and forming more than 540 fourth trenches, the first lateral direction can be equal to the third lateral direction, and the second lateral direction can be equal to the fourth lateral direction.

[0093] For example, the first semiconductor substrate 410 may be connected to the second semiconductor substrate 420 such that each first semiconductor mesa structure 110 of the plurality of first semiconductor mesas 110 is laterally arranged between two second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 .

[0094] For example, the width of a second trench in the plurality of second trenches may be less than 90% (or less than 75%, less than 50%, or less than 25%) of the width of a first trench in the plurality of first trenches. For example, the width of a fourth trench in the plurality of fourth trenches may be less than 90% (or less than 75%, less than 50%, or less than 25%) of the width of a third trench in the plurality of third trenches. For example, the width of a first trench in the plurality of first trenches and the width of a second trench in the plurality of second trenches may differ by more than 10% (or more than 25%, more than 50%, or more than 75%) of the width of the first trench in the plurality of first trenches. The width of a third trench in the plurality of third trenches and the width of a fourth trench in the plurality of fourth trenches may differ by more than 10% (or more than 25%, more than 50%, or more than 75%) of the width of the third trench in the plurality of third trenches.

[0095] For example, a first trench in the plurality of first trenches and a second trench in the plurality of second trenches can be formed by sawing using saw blades having different thicknesses. In this way, a thermoelectric device can be formed cost-effectively. For example, a third trench in the plurality of third trenches and a fourth trench in the plurality of fourth trenches can be formed by sawing using saw blades having different thicknesses. In this way, a thermoelectric device can be formed cost-effectively.

[0096] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 5 The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-4n ) or below (for example, Figures 6a-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0097] Figures 6a to 6g Schematic process steps for forming thermoelectric device 600 are shown. The method for forming thermoelectric device 600 can be similar to that of combining Figure 3 The method described or similar to the combination Figure 5Described method. Figure 6a A first semiconductor substrate 410 is shown. For example, the first semiconductor substrate 410 may be a p-doped semiconductor wafer. In a portion 410 a of the first semiconductor substrate 410 , a plurality of semiconductor row structures and a plurality of trenches 620 extending in a first lateral direction 630 are formed in the portion 410 a of the first semiconductor substrate 410 , as shown in FIG. Figure 6b Thereafter, a plurality of further trenches extending in the second lateral direction 640 are formed in the portion 410a of the first semiconductor substrate 410, as shown in FIG. Figure 6c As shown in , a plurality of first semiconductor mesas 110 and a plurality of recesses 650 are thus formed. Figure 6d The second semiconductor substrate 420 is shown. For example, the second semiconductor substrate 420 may be an n-doped semiconductor wafer. Figure 6e As shown in FIG, a plurality of second semiconductor mesas 120 and a plurality of recesses 650 are formed in the second semiconductor substrate 420, which is similar to the combination of Figure 6b and 6c The first semiconductor substrate 410 and the second semiconductor substrate 420 may be connected to form thermoelectric devices 600-1, 600-2, as shown in FIG. Figure 6f and 6g In the thermoelectric device 600-1, the first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 and the recesses 650 of the plurality of recesses 650 are alternately arranged in rows and columns, and the second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 and the recesses 650 of the plurality of recesses 650 are alternately arranged in rows and columns. In the thermoelectric device 600-2, the first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 are alternately arranged in rows, and the recesses 650 of the plurality of recesses 650 are arranged in rows.

[0098] Figures 6a to 6gAn example of mesa etching or mesa cutting in one step and one substrate for each of n-doping and p-doping is shown. For example, the plurality of recesses 650 can be formed by vertical and horizontal cuts of the same thickness. For example, the cuts can be formed by sawing or etching. For example, the thickness of the cuts in the first lateral direction 630 can be equal to the thickness of the cuts in the second lateral direction 640. For example, the thickness of the cuts in the first lateral direction 630 and / or the thickness of the cuts in the second lateral direction 640 can be greater than the maximum lateral dimension of the first semiconductor mesa structure 110 in the plurality of first semiconductor mesa structures 110 and the maximum lateral dimension of the second semiconductor mesa structure 120 in the plurality of second semiconductor mesa structures 120 in the first lateral direction 630 and the second lateral direction 640. For example, the first semiconductor mesa structure 110 in the plurality of first semiconductor mesa structures 110 and the second semiconductor mesa structure 120 in the plurality of second semiconductor mesa structures 120 can be quadratic mesa structures (e.g., having the same lateral dimensions in the first lateral direction 630 and the second lateral direction 640). For example, after connecting 550 the first semiconductor substrate 410 to the second semiconductor substrate 420, the first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 may be separated from each other (e.g., in the first lateral direction 630 and in the second lateral direction 640). For example, the recesses 650 of the plurality of recesses 650 may be filled with glass.

[0099] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figures 6a-6g The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-5 ) or below (for example, Figures 7a-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0100] Figures 7a to 7e Schematic process steps for forming another thermoelectric device 700 are shown. The method for forming the thermoelectric device 700 can be similar to the method for forming the thermoelectric device 700. Figure 3 The method described or similar to the combination Figure 5 Described method. Figure 7a The first semiconductor substrate 410 is shown. For example, the first semiconductor substrate 410 may be a p-doped semiconductor wafer. In a portion 410a of the first semiconductor substrate 410, a plurality of first semiconductor mesas 110 and a plurality of recesses 650 are formed, as shown in FIG. Figure 7b As shown in . Figure 7c The second semiconductor substrate 420 is shown. For example, the second semiconductor substrate 420 may be an n-doped semiconductor wafer. Figure 7d As shown in FIG, a plurality of second semiconductor mesas 120 and a plurality of recesses 650 are formed in the second semiconductor substrate 420. The first semiconductor substrate 410 and the second semiconductor substrate 420 may be connected to form a thermoelectric device 700, as shown in FIG. Figure 7e In the thermoelectric device 700, the first semiconductor mesa structures 110 of the plurality of first semiconductor mesa structures 110 and the second semiconductor mesa structures 120 of the plurality of second semiconductor mesa structures 120 are alternately arranged in rows. In addition, the first semiconductor mesa structures 110 of the plurality of first semiconductor mesa structures 110 are arranged in columns, and the second semiconductor mesa structures 120 of the plurality of second semiconductor mesa structures 120 are arranged in columns.

[0101] Figures 7a to 7e An example of mesa etching or mesa cutting in one step and one substrate for each n-doping and p-doping is shown. This allows for dense packaging. For example, multiple recesses 650 can be formed by vertical and horizontal cuts of different thicknesses. For example, the cuts can be formed by sawing or etching. For example, the thickness of the cuts in the first lateral direction 630 can be less than the thickness of the cuts in the second lateral direction 640. For example, the first semiconductor mesa structure 110 of the plurality of first semiconductor mesa structures 110 and the second semiconductor mesa structure 120 of the plurality of second semiconductor mesa structures 120 can be square mesa structures (e.g., having the same lateral dimensions in the first lateral direction 630 and the second lateral direction 640). For example, after connecting 550 the first semiconductor substrate 410 to the second semiconductor substrate 420, the first semiconductor mesa structure 110 of the plurality of first semiconductor mesa structures 110 and the second semiconductor mesa structure 120 of the plurality of second semiconductor mesa structures 120 can be separated from each other (e.g., in the first lateral direction 630 and the second lateral direction 640). For example, a recess 650 in the plurality of recesses 650 may be filled with glass.

[0102] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figures 7a-7e The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-6g ) or below (for example, Figures 8a-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0103] Figures 8a to 8e Schematic process steps for forming another thermoelectric device 800 are shown. The method for forming the thermoelectric device 800 can be similar to the method for forming the thermoelectric device 800. Figure 3 The method described or similar to the combination Figure 5 Described method. Figure 8aThe first semiconductor substrate 410 is shown. For example, the first semiconductor substrate 410 may be a p-doped semiconductor wafer. In a portion 410a of the first semiconductor substrate 410, a plurality of first semiconductor mesas 110 and a plurality of recesses 650 are formed, as shown in FIG. Figure 8b As shown in . Figure 8c The second semiconductor substrate 420 is shown. For example, the second semiconductor substrate 420 may be an n-doped semiconductor wafer. Figure 8d As shown in FIG, a plurality of second semiconductor mesas 120 and a plurality of recesses 650 are formed in the second semiconductor substrate 420. The first semiconductor substrate 410 and the second semiconductor substrate 420 may be connected to form a thermoelectric device 800, as shown in FIG. Figure 8e In the thermoelectric device 800 , the first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 are alternately arranged in rows and columns.

[0104] Figures 8a to 8e An example of a combination of mesa etching or sawing (e.g., sawing of thin lines) and etching (e.g., etching of thick recesses) in one step and one substrate using an etching mask is shown. Thus, an etching process can be used to form a dense package. For example, a plurality of recesses 650 can be formed by vertical and horizontal cuts of different thicknesses. For example, the cuts can be formed by etching. For example, the thickness of the cuts in the first lateral direction 630 can be less than the thickness of the cuts in the second lateral direction 640. For example, a first semiconductor mesa structure 110 of the plurality of first semiconductor mesa structures 110 and a second semiconductor mesa structure 120 of the plurality of second semiconductor mesa structures 120 can be square mesa structures (e.g., can have the same lateral dimensions in the first lateral direction 630 and the second lateral direction 640). For example, after connecting 550 the first semiconductor substrate 410 to the second semiconductor substrate 420, the first semiconductor mesas 110 of the plurality of first semiconductor mesas 110 and the second semiconductor mesas 120 of the plurality of second semiconductor mesas 120 may be separated from each other (e.g., in the first lateral direction 630 and in the second lateral direction 640). For example, the recesses 650 of the plurality of recesses 650 may be filled with glass.

[0105] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figures 8a-8e The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-7e ) or below (for example, Figures 9a-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0106] Figures 9a to 9dFor example, a first semiconductor mesa structure 110 of the plurality of first semiconductor mesas 110 and / or a second semiconductor mesa structure 120 of the plurality of second semiconductor mesas 120 may have Figures 9a to 9d One of the mesa geometry structures shown in . Figures 9a to 9d Examples of mesa shapes are shown in top and side views.

[0107] Figure 9a A top view of mesa structure geometries 901, 903, and 905 is shown. Arrows 907 and 909 indicate lateral directions. Mesa structure geometry 901 is square (e.g., the lateral dimension in direction 907 is equal to the lateral dimension in direction 909). The lateral dimension of the base of mesa structure geometry 901 is greater than the lateral dimension of the mesa of mesa structure geometry 901. Thus, mesa structure geometry 901 may form a pyramid or a truncated pyramid. Mesa structure geometries 903 and 905 are rectangular (e.g., the lateral dimension in direction 907 is different from the lateral dimension in direction 909).

[0108] Figure 9b A top view is shown on mesa structure geometries 911, 913, 915. The corners and edges of the mesa structure geometries 911, 913, 915 may be rounded. The mesa structure geometry 915 shows the limiting case, where the mesa structure is rounded.

[0109] Figure 9c A side view of mesa geometries 920, 930, and 940 is shown. Arrow 909 indicates the lateral direction. The lateral dimension of mesa 921 of mesa geometry 920 is equal to the lateral dimension of base 922 of mesa geometry 920. Additionally, the lateral dimension of mesa 931 of mesa geometry 930 is smaller than the lateral dimension of base 932 of mesa geometry 930. Additionally, the lateral dimension of mesa 941 of mesa geometry 940 is smaller than the lateral dimension of base 942 of mesa geometry 940. For example, for silicon, in a 100 orientation (e.g., in a surface orientation), typical values ​​for angle α in mesa geometry 940 can be 45° along the 110 plane, 54.7° along the 111 plane, and 90° along the 100 plane.

[0110] Figure 9d Shown is a side view of a mesa structure geometry 950. The mesa structure geometry 950 has rounded edges 951,952,953,954. Figure 9d An example of a substrate wafer is shown before grinding or thinning.

[0111] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figures 9a-9d The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-8e ) or below (for example, Figures 9a-10c ) One or more aspects mentioned in one or more embodiments described or concepts proposed.

[0112] Figures 10a-10c 10. The perspective views of different mesa structures 1010, 1020, 1030 are shown. For example, a first semiconductor mesa structure 110 of the plurality of first semiconductor mesas 110 and / or a second semiconductor mesa structure 120 of the plurality of second semiconductor mesas 120 may have Figures 10a to 10c One of the mesa geometries is shown in . Mesa geometry 1010 is a truncated pyramid, mesa geometry 1020 is a cube, and mesa geometry 1030 is a cylinder.

[0113] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figures 10a-10c The embodiment shown in may include one or more optional additional features, which correspond to the combination of the above (for example, Figure 1-9d ) or one or more aspects mentioned in one or more embodiments or proposed concepts described below.

[0114] Some embodiments relate to silicon-based devices for energy harvesting.

[0115] Some embodiments relate to energy harvesting using silicon-based Peltier elements.

[0116] One aspect relates to thermoelectric devices, or thermoelectric microgenerators, that can harvest heat from the environment (e.g., body heat) and convert it into a DC voltage consistent with the Seebeck effect. The small size of the components and the high efficiency of the heat-to-voltage conversion enable their use in wireless sensors and, for example, wearable electronic components. One advantage can be the reduction of weight-constrained batteries that must be maintained, or the elimination of external power supplies. Furthermore, sensors operated by the microgenerators can be used in any location and are flexible in terms of space requirements. Thermoelectric microgenerators can operate maintenance-free and have very long service lives. The voltage generation function may require only a temperature difference of a few degrees Celsius. Given a large temperature difference, each individual thermoelectric unit can generate a current of approximately 440 μV / K (temperature difference; silicon-Seebeck coefficient) and electrical power in the milliwatt range up to several watts. This can be used to operate microsensors, for example, for manual, contactless control of electrical devices. As many devices combine an increasing number of functions in an increasingly reduced area, manual, contactless control can offer significant advantages. It is also conceivable to use it in control systems consistent with Industry 4.0 concepts. For example, fingertip gesture control interfaces could be implemented. Using thermoelectric microgenerators to wirelessly operate the so-called Soli chip could offer considerable advantages for further market launches. Here, a voltage of 1.8V can deliver 54mW of power without a mains connection.

[0117] Another aspect may involve the possibility of using known processes from silicon wafer technology to manufacture efficient and cost-effective thermoelectric microgenerators (e.g., thermoelectric devices). By utilizing this technology and the associated degrees of freedom in design, more efficient thermoelectric element units (e.g., having a larger aspect ratio) can be manufactured. Due to the design and high efficiency levels, the resulting microgenerator can use a thermal differential of only a few degrees or even lower to generate the electrical power levels required for the operation of the wireless sensor. Thermoelectric devices may provide one or all of the following advantages: the use of cost-effective silicon as the thermoelectric base material; more cost-effective manufacturing due to the use of known silicon technology processes and the fact that this operation can be performed at the wafer level; higher functionality and more efficient components due to the greater design freedom (e.g., aspect ratio) when producing thermoelectric element units; and market expansion for components (e.g., wireless sensors, radar sensors, in particular).

[0118] A further aspect may relate to the provision of an electrical microgenerator with special thermoelectric cells produced by means of silicon wafer technology.

[0119] Another aspect may involve making the fingertip gesture control interface practical for mass use, since for 1x1 mm 2For a thermoelectric microgenerator of this size, one can assume process costs which may amount to less than €1.00, which may be very low compared to the sensor cost and the cost of the complete product.

[0120] The aspects and features mentioned and described in conjunction with one or more of the previously detailed examples and figures may also be combined with one or more of the other examples in order to replace the same features in another example or to additionally introduce features into another example.

[0121] The description and drawings merely illustrate the principles of the present disclosure. In addition, all examples recorded herein are expressly intended to be for teaching purposes only, in order to help the reader understand the principles of the present disclosure and the concepts contributed by the inventor(s) to advance this art. All statements herein recording principles, aspects, and examples of the present disclosure, as well as specific examples thereof, are intended to encompass their equivalents.

[0122] A block diagram may, for example, illustrate a high-level circuit diagram that implements the principles of the present disclosure. Similarly, a flow chart, a flowchart, a state transition diagram, a pseudocode, or the like may represent various processes, operations, or steps that may, for example, be generally represented in a computer-readable medium and thus executed by a computer or processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the specification or claims may be implemented by an apparatus having means for performing each of the corresponding actions of the methods.

[0123] It will be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a specific order unless otherwise expressly or implicitly stated, for example, for technical reasons. Therefore, the disclosure of multiple actions or functions is not limited to these being in a specific order unless such actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or may be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or self-steps, respectively. Such sub-actions may be included and are the disclosed part of the single action, unless expressly excluded.

[0124] In addition, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate example. Although each claim stands on its own as a separate example, it should be noted that although a dependent claim refers to a specific combination with one or more other claims in a claim, other examples may also include a combination of a dependent claim with the subject matter of each other dependent claim or independent claim. Such combinations are expressly set forth herein unless a specific combination is not intended. In addition, it is intended that features of a claim also be included in any other independent claim, even if that claim is not directly dependent on the independent claim.

Claims

1. A method (300) for forming a thermoelectric device, the method (300) comprising: forming (310) a plurality of first semiconductor mesas (110) on a first semiconductor substrate (410), wherein the first semiconductor substrate (410) has a first conductivity type; forming (320) a plurality of second semiconductor mesas (120) at a second semiconductor substrate (420), wherein the second semiconductor substrate (420) has a second conductivity type; Disposing a glass substrate (440) between the first semiconductor substrate (410) and the second semiconductor substrate (420); as well as applying at least one of heat and pressure to the glass substrate (440) to deform the glass substrate (440) so that at least a portion of the glass substrate (440) moves between a first semiconductor mesa structure (110) of the plurality of first semiconductor mesa structures (110) and a second semiconductor mesa structure (120) of the plurality of second semiconductor mesa structures (120), thereby connecting (340) the first semiconductor substrate (410) to the second semiconductor substrate (420), The thermal expansion coefficient of the glass substrate (440) is similar to the thermal expansion coefficient of a first semiconductor mesa structure (110) among the plurality of first semiconductor mesa structures (110), and / or similar to the thermal expansion coefficient of a second semiconductor mesa structure (120) among the plurality of second semiconductor mesa structures (120).

2. The method of claim 1, wherein applying heat to the glass substrate (440) comprises a temperature greater than 350°C.

3. The method of claim 2, further comprising heating the first semiconductor substrate (410), the second semiconductor substrate (420), and the glass substrate (440) to a temperature greater than 350°C and less than 900°C.

4. The method according to any one of claims 1 to 3, wherein the glass substrate (440) is a glass wafer (441) or a glass foil (442) comprising at least one of borosilicate glass, boron zinc glass and low transition temperature glass.

5. The method according to any one of claims 1 to 4, wherein the first semiconductor substrate (410) is connected (340) to the second semiconductor substrate (420).

6. The method according to any one of claims 1 to 5, wherein connecting (340) the first semiconductor substrate (410) to the second semiconductor substrate (420) comprises pressing the first semiconductor substrate (410) against the second semiconductor substrate (420) with a pressure greater than 1 kN and less than 20 kN, with the glass substrate (440) therebetween.

7. The method according to any one of claims 1 to 6, wherein forming (310) a plurality of first semiconductor mesa structures (110) includes forming at least one trench in the first semiconductor substrate (410), and wherein the at least one trench in the first semiconductor substrate (410) is formed by at least one of an etching process, a sawing process, a water jet cutting process, and a laser slicing process.

8. The method according to any one of claims 1 to 7, further comprising removing a portion of the first semiconductor substrate (410) after connecting (340) the first semiconductor substrate (410) to the second semiconductor substrate (420) so as to separate the first semiconductor mesa structures (110) of the plurality of first semiconductor mesa structures (110) from each other.

9. The method according to any one of claims 1 to 8, further comprising forming a plurality of metallization structures (140) located on one side of a first semiconductor mesa structure (110) among the plurality of first semiconductor mesa structures (110) and a second semiconductor mesa structure (120) among the plurality of second semiconductor mesa structures (120), wherein each of the plurality of metallization structures (140) electrically connects a first semiconductor mesa structure (110) among the plurality of first semiconductor mesa structures (110) and a second semiconductor mesa structure (120) among the plurality of second semiconductor mesa structures (120).

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