A broadband single-pole double-throw switch MMIC

Abstract

This invention discloses a broadband single-pole double-throw (MPD) switch MMIC, belonging to the field of radio frequency (RF) / microwave. The switch adopts a symmetrical dual-channel structure. Each channel includes a series-connected switch circuit at the input end, a series-connected switch circuit at the output end, and two parallel switch branches. Channel switching is achieved through two complementary control voltages, and impedance matching between the circuits is performed using microstrip lines. The technical solution utilizes a circuit network composed of a switch, resistors, and inductors. Through the resonant effect of the inductor and the cutoff capacitance of the switch in the parallel branches, combined with the parallel resistor structure and microstrip line matching technology, the signal transmission path is optimized. This invention achieves low insertion loss and high isolation performance over a wide bandwidth, while reducing the voltage standing wave ratio (VSWR) of the off-state output port and improving port matching capability, providing an efficient and stable solution for signal routing in RF systems.

Description

Technical Field

[0001] This invention relates to the field of radio frequency / microwave, and particularly to a broadband single-pole double-throw switch (MMIC). Background Technology

[0002] In the RF / microwave field, the performance specifications of switching chips focus on insertion loss and isolation. In the on state, the switch needs low insertion loss to minimize its impact on overall system gain and power. In the off state, the switch needs sufficient isolation to prevent signal interference between multiple paths. With technological advancements, the performance requirements for switches are becoming increasingly demanding, and conventional structures can no longer meet these higher performance needs. Summary of the Invention

[0003] The purpose of this invention is to solve the problem of the lack of a broadband single-pole double-throw switch (MMIC) that achieves low insertion loss, high isolation, and low VSWR at the off-state output port, and to provide a broadband single-pole double-throw switch (MMIC).

[0004] The objective of this invention is achieved through the following technical solution:

[0005] A broadband single-pole double-throw switch (MMIC) includes an input port RFin, a first output port RFout1, and a second output port RFout2, and adopts a symmetrical structure with two channels. Each of the two channels includes an input series switch circuit, an output series switch circuit, and two parallel switch branches. The broadband single-pole double-throw switch includes two first control voltages V1 and second control voltages V2.

[0006] Furthermore, the input series switching circuit includes a first switching transistor M1, the output series switching circuit includes a sixth switching transistor M6 and a first resistor R1, the first parallel branch includes a second switching transistor M2, a third switching transistor M3 and a first inductor L1, and the second parallel branch includes a fourth switching transistor M4, a fifth switching transistor M5 and a second inductor L2.

[0007] Furthermore, the output terminal is connected in series with a switching circuit, wherein the sixth switch M6 and the first resistor R1 are connected in parallel. When the channel is in the closed state, the sixth switch M6 is turned off. At this time, the output port is connected to the first resistor R1 through the parallel branch to the ground, which can achieve good port matching and effectively reduce the port voltage standing wave ratio in the closed state.

[0008] Furthermore, in the parallel switching circuit, the first parallel branch and the second parallel branch have the same structure.

[0009] Furthermore, taking the first parallel switching circuit as an example, the second switch M2 and the third switch M3 are connected in series, the third switch M3 is grounded, and the third switch M3 is connected in parallel with the first inductor L1. When the channel is in the open state, the cutoff capacitors of the first inductor L1 and the third switch M3 resonate, while the second switch M2 prevents DC and low-frequency signals from reaching ground through the first inductor L1. The two work together to reduce the insertion loss in the open state. When the channel is in the closed state, the low-frequency part of the signal leaked by the series switching circuit can reach ground through the first inductor L1 of the parallel switching circuit, enhancing the isolation of the low-frequency part of the signal.

[0010] Furthermore, microstrip lines are used for impedance matching between the input terminals, output terminals, series switching circuits, and parallel switching circuits.

[0011] Furthermore, the first control voltage V1 and the second control voltage V2 are complementary.

[0012] The beneficial effects of this invention are:

[0013] (1) By using a symmetrical dual-channel architecture and multi-branch collaborative design, combined with microstrip line impedance matching technology, low insertion loss and efficient signal transmission are achieved over a wide bandwidth.

[0014] (2) By using the parallel resistor structure and matching network of the series switch circuit at the output end, the port impedance matching in the off state is realized, which effectively reduces the VSWR of the off-state output voltage.

[0015] (3) By utilizing the resonant filtering characteristics of the inductor and the switching transistor in the parallel branch, and in conjunction with the complementary control voltage mechanism, the signal isolation and channel switching stability in the wide bandwidth are enhanced. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a broadband single-pole double-throw switch (MMIC).

[0017] Figure 2 A schematic diagram of the insertion loss of a broadband single-pole double-throw switch (MMIC) provided for an embodiment of the present invention;

[0018] Figure 3 A schematic diagram of the isolation of a broadband single-pole double-throw switch (MMIC) provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the off-state output voltage standing wave ratio of a broadband single-pole double-throw switch (MMIC). Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1

[0022] This invention provides a broadband single-pole double-throw (MPI) switch to address the current lack of MPIs that achieve broadband low insertion loss, high isolation, and low VSWR at the off-state output port.

[0023] See Figure 1 This invention provides a broadband single-pole double-throw switch (MMIC) including an input port RFin, a first output port RFout1, and a second output port RFout2, with a symmetrical structure and two channels. Each of the two channels includes an input series switch circuit, an output series switch circuit, and two parallel switch branches. The broadband single-pole double-throw switch includes two first control voltages V1 and a second control voltage V2.

[0024] The input series switching circuit includes a first switching transistor M1, the output series switching circuit includes a sixth switching transistor M6 and a first resistor R1, the first parallel branch includes a second switching transistor M2, a third switching transistor M3 and a first inductor L1, and the second parallel branch includes a fourth switching transistor M4, a fifth switching transistor M5 and a second inductor L2.

[0025] The output terminal uses a series switching circuit, where the sixth switch M6 and the first resistor R1 are connected in parallel. When the channel is in the off state, the sixth switch M6 is turned off. At this time, the output port is connected to ground through the parallel branch of the first resistor R1, which can achieve good port matching and effectively reduce the port voltage standing wave in the off state. Figure 2 As shown, the red line represents the insertion loss of the conventional circuit, and the blue line represents the insertion loss of the circuit in this embodiment.

[0026] The first parallel branch has the same structure as the second parallel branch.

[0027] Taking the first example, the second switch M2 and the third switch M3 are connected in series, the third switch M3 is grounded, and the third switch M3 is connected in parallel with the first inductor L1. When the channel is in the open state, the first inductor L1 and the cutoff capacitance of the third switch M3 resonate. At the same time, the second switch M2 prevents DC and low-frequency signals from reaching ground through the first inductor L1. Both work together to reduce insertion loss in the open state. When the channel is in the closed state, the low-frequency portion of the signal leaked from the series switching circuit can reach ground through the first inductor L1 of the parallel switching circuit, enhancing the isolation of the low-frequency portion of the signal. Figure 3 , Figure 4 As shown, the red lines represent the isolation and off-state output voltage standing wave ratio of the conventional circuit, while the blue lines represent the corresponding indicators of the circuit in this embodiment.

[0028] Microstrip lines are used for impedance matching between input terminals, output terminals, series switching circuits, and parallel switching circuits.

[0029] The control voltages V1 and V2 are complementary. When V1 is -5V, V2 is 0V, and when V1 is 0V, V2 is -5V.

[0030] The single-pole double-throw switch proposed in this embodiment of the invention is designed based on gallium arsenide technology.

[0031] The broadband single-pole double-throw switch MMIC described in this embodiment of the invention operates at a frequency of 0-20GHz, has a bandwidth of 20GHz, a center point of 10GHz, a relative bandwidth of 200%, an on-state insertion loss of less than 1.5dB, an off-state isolation of more than 35dB, an input voltage standing wave ratio (VSWR) of less than 1.2, an on-state output voltage VSWR of less than 1.2, and an off-state output voltage VSWR of less than 1.6.

[0032] Example 2

[0033] The broadband single-pole double-throw switch MMIC provided in this embodiment adopts a symmetrical dual-channel architecture, including an input port RFin, a first output port RFout1, and a second output port RFout2. The entire chip is symmetrical about its central axis, and the two signal channels are completely identical in circuit topology, component parameters, and layout, ensuring the symmetry and consistency of signal transmission. Each channel consists of an input series switch circuit, an output series switch circuit, and two parallel switch branches. Channel selection and shutdown are achieved through two complementary first control voltages V1 and second control voltages V2.

[0034] Core circuit composition and working principle:

[0035] (a) Input terminal series switch circuit:

[0036] An input-side series switching circuit is positioned between the input port RFin and the internal signal path, and includes a first switching transistor M1. This transistor employs a gate-controlled structure, with its source connected to the input port and its drain connected to subsequent circuitry. When the channel is on, either the first control voltage V1 or the second control voltage V2 keeps the first switching transistor M1 in a low-impedance on state, ensuring efficient transmission of the input signal. When the channel is off, the first switching transistor M1 enters a high-impedance off state, blocking signal transmission. The gate size and channel length of the first switching transistor M1 are optimized to balance on-resistance and cutoff isolation, avoiding additional losses during high-frequency signal transmission.

[0037] (ii) Output terminal series switch circuit:

[0038] The output-side series switching circuit consists of a sixth switching transistor M6 connected in parallel with a first resistor R1, positioned between the internal signal path and the output port. The source of the sixth switching transistor M6 is connected to the signal path, and its drain is connected to either the first output port RFout1 or the second output port RFout2. One end of the first resistor R1 is connected to the drain of the sixth switching transistor M6, and the other end is grounded through a parallel branch. When the channel is off, the sixth switching transistor M6 is cut off, and the output port forms a loop to ground through the first resistor R1 and the parallel branch. In this case, the resistance value of the first resistor R1 is designed to match the impedance characteristics of the parallel branch, ensuring good matching at the output port and effectively reducing the port voltage standing wave ratio (VSWR) in the off-state. This design utilizes the synergistic effect of resistor voltage division and parallel grounding to prevent signal reflection at the output port in the off-state, thus improving the port matching performance of the switch.

[0039] (III) Design of parallel switch branches:

[0040] Two parallel switch branches are symmetrically distributed on both sides of the signal path. Taking the first parallel branch as an example, it consists of a second switch M2, a third switch M3, and a first inductor L1. Specifically, the source of the second switch M2 is connected to the signal path, its drain is connected in series with the source of the third switch M3, the drain of the third switch M3 is grounded, and the first inductor L1 is connected in parallel across the third switch M3. The structure of the second parallel branch (consisting of a fourth switch M4, a fifth switch M5, and a second inductor L2) is completely identical to the first, forming a symmetrical topology.

[0041] 1. On-state operating mechanism: When the channel is on, the control voltage causes the second switch M2 and the third switch M3 to operate in different states. Specifically, the third switch M3 is off, and its junction capacitance forms a parallel resonant circuit with the first inductor L1. The resonant frequency covers the operating frequency band, thus offsetting the capacitive impedance when the third switch M3 is off and reducing the equivalent impedance of the signal path. Simultaneously, the second switch M2 is on, and its low-impedance characteristic prevents DC and low-frequency signals from grounding through the first inductor L1, avoiding power signal leakage. The combined effect of these two mechanisms significantly reduces insertion loss in the on-state.

[0042] 2. Off-state operating mechanism: When the channel is off, signal leakage may occur in the series switching circuit (such as the first switch M1). At this time, the second switch M2 in the parallel branch is cut off, and the third switch M3 is turned on. The low-frequency components in the leakage signal can be grounded through the low-impedance path formed by the turned-on third switch M3 and the first inductor L1, while the high-frequency components are suppressed by the inductive reactance of the first inductor L1, thereby enhancing the low-frequency isolation in the off state. This design achieves high isolation over a wide bandwidth through the frequency-selective filtering characteristics of the inductor and the switch.

[0043] Control voltage and channel switching mechanism:

[0044] The switching MMIC employs two complementary control voltages, a first control voltage V1 and a second control voltage V2, with their amplitudes designed to be inversely related (e.g., a combination of positive and negative voltages). When the first control voltage V1 is high, the second control voltage V2 is low, and vice versa. The specific control logic is as follows:

[0045] When the first output port RFout1 needs to be selected, the first control voltage V1 is applied at the on level and the second control voltage V2 is applied at the off level. At this time, the series switch circuit of the first channel is turned on, the parallel branch is in the resonant matching state, and the signal is output from RFin through the first output port RFout1. At the same time, the series switch circuit of the second channel is turned off, the parallel branch is grounded, and signal leakage is suppressed.

[0046] When switching to the second output port RFout2 is required, the levels of the first control voltage V1 and the second control voltage V2 are reversed, the second channel is turned on, and the first channel is turned off, thus switching the signal path. Complementary voltage control ensures that the two channels will not be turned on simultaneously, avoiding signal short circuits. At the same time, the precise switching of the level states ensures stable operation of the switch over a wide frequency band.

[0047] Complementary voltage control ensures that the two channels will not conduct simultaneously, avoiding signal short circuits, while precise switching of level states ensures stable operation of the switch over a wide frequency band.

[0048] Impedance matching design:

[0049] Impedance matching is achieved using microstrip lines between the input and output terminals and each switching circuit. The width, length, and dielectric layer thickness of the microstrip lines are designed based on the target impedance (e.g., 50Ω) and operating frequency band, and their topology is optimized through electromagnetic field simulation. Specific matching measures include:

[0050] 1. Input matching network: A tapered microstrip line is set between RFin and the series switching circuit at the input terminal to gradually adjust the impedance to the equivalent input impedance of the switching circuit, thereby reducing signal reflection.

[0051] 2. Output matching network: A λ / 4 impedance transformer is used between the series switching circuit at the output end and the first output port RFout1 / second output port RFout2. By designing the characteristic impedance and length of the microstrip line, the output impedance is matched to the standard load impedance.

[0052] 3. Internal Matching Structure: T-type or L-type microstrip line matching structures are set at the connection points of series switching circuits and parallel branches to eliminate impedance discontinuities between different circuit modules. The impedance matching design of the microstrip line is optimized in conjunction with the parasitic parameters of components such as switches and inductors to ensure that the input / output voltage standing wave ratio meets the requirements throughout the entire frequency band.

[0053] The impedance matching design of the microstrip line is optimized in conjunction with the parasitic parameters of components such as switches and inductors to ensure that the input / output voltage standing wave ratio meets the requirements throughout the entire frequency band.

[0054] In terms of process implementation and layout design: This switch MMIC is implemented based on compound semiconductor processes (such as gallium arsenide), utilizing its high electron mobility and low noise characteristics to meet the design requirements of wide bandwidth and low loss. Specific process considerations include:

[0055] 1. Switch structure: Schottky barrier field-effect transistor (MESFET) or heterojunction field-effect transistor (HEMT) is adopted, and the on-resistance and cut-off capacitance are reduced through gate process optimization.

[0056] 2. Inductor integration: The first inductor L1 and the second inductor L2 are on-chip spiral inductors. The inductance value and quality factor are improved through metal layer stacking and dielectric isolation. Their geometric dimensions are designed according to the resonant frequency and inductive reactance requirements.

[0057] 3. Resistor implementation: The first resistor R1 is made using ion implantation or thin film resistor technology to ensure resistance accuracy and temperature stability, and to meet the off-state matching requirements.

[0058] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A broadband single-pole double-throw switch (MMIC), characterized in that, It includes an input port, a first output port, and a second output port, and adopts a symmetrical structure with a total of two channels; each of the two channels includes an input-end series switch circuit, an output-end series switch circuit, and two parallel switch branches; the broadband single-pole double-throw switch includes two first control voltages and a second control voltage. The first parallel branch and the second parallel branch have the same structure. In the first parallel branch, the source of the second switch is connected to the signal path of the channel, the drain of the second switch is connected in series with the source of the third switch, and the drain of the third switch is grounded. At the same time, the first inductor is connected in parallel across the third switch. When the channel is in the open state, the first inductor and the cutoff capacitor of the third switch resonate. Meanwhile, the second switch prevents DC and low-frequency signals from being grounded through the first inductor. The two work together to reduce the insertion loss in the open state. When the channel is in the closed state, the low-frequency part of the signal leaked by the series switch circuit can be grounded through the first inductor of the parallel switch circuit, which enhances the isolation of the low-frequency part of the signal.

2. The broadband single-pole double-throw switch (MMIC) according to claim 1, characterized in that, The input series switching circuit includes a first switching transistor, the output series switching circuit includes a sixth switching transistor and a first resistor, the first parallel branch includes a second switching transistor, a third switching transistor and a first inductor, and the second parallel branch includes a fourth switching transistor, a fifth switching transistor and a second inductor.

3. A broadband single-pole double-throw switch (MMIC) according to claim 2, characterized in that, The output terminal is connected in series with a switching circuit, in which the sixth switch and the first resistor are connected in parallel. When the channel is in the closed state, the sixth switch is turned off. At this time, the output port is connected to the first resistor through the parallel branch to the ground, which can achieve good port matching and effectively reduce the port voltage standing wave ratio in the closed state.

4. A broadband single-pole double-throw switch (MMIC) according to claim 1, characterized in that, Microstrip lines are used for impedance matching between the input terminals, output terminals, series switching circuits, and parallel switching branches.

5. A broadband single-pole double-throw switch (MMIC) according to claim 1, characterized in that, The first control voltage and the second control voltage are complementary.

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