Silicon wafer, cell, photovoltaic module and method for preparing cell

Abstract

The application relates to the photovoltaic technology field, in particular to a silicon wafer, a cell wafer and a photovoltaic module. The silicon wafer comprises a silicon wafer substrate provided with a through hole penetrating through the silicon wafer substrate; and a first textured structure arranged on the inner wall of the through hole, and the first textured structure is arranged at least at one end of the axial direction of the through hole and is spaced apart from the surface of the silicon wafer substrate in the axial direction. The application arranges the first textured structure at least at one end of the axial direction of the through hole and keeps a certain interval with the surface of the silicon wafer substrate in the axial direction, forms the first textured structure on part of the through hole to change the light angle, can significantly increase the reflection times of the light in the through hole, and prolongs the propagation path of the light in the silicon. Therefore, the path length of the light in the silicon wafer is increased, more light energy is trapped and converted into electric energy due to the prolongation of the light path, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a method for preparing silicon wafers, solar cells, photovoltaic modules, and solar cells. Background Technology

[0002] In recent years, with the global emphasis on renewable energy and the popularization of green building concepts, building photovoltaic glass, as an innovative material that can both generate electricity and meet the building's lighting needs, has experienced rapid development and widespread application. This material not only requires high photoelectric conversion efficiency to generate sufficient electricity, but also good light transmission performance to ensure that the building's interior natural lighting requirements are met.

[0003] Traditional crystalline silicon solar cells have low light transmittance due to the inherent characteristics of the material, making it difficult to meet the building's demand for natural lighting. How to develop a new product that balances light transmittance with high light trapping effect is an urgent problem to be solved.

[0004] Therefore, this application is hereby submitted. Summary of the Invention

[0005] To address the aforementioned technical problems, the purpose of this application is to provide a silicon wafer that achieves better light-trapping effect while maintaining the light transmittance of the silicon substrate, as well as to provide solar cells and photovoltaic modules made from the aforementioned silicon wafer.

[0006] A silicon wafer is provided in the first aspect of this application, including a silicon wafer substrate, the silicon wafer substrate having a through hole penetrating the silicon wafer substrate; and a first textured structure, the first textured structure being disposed on the inner wall of the through hole, and at least one end of the first textured structure in the axial direction of the through hole being spaced apart from the surface of the silicon wafer substrate in the axial direction.

[0007] In a further alternative embodiment of this application, the height of the through hole along the axial direction is the first height H1, and the distance between the surface of the first velvet structure along the axial direction and the surface perpendicular to the axial direction is the second height H2, wherein 0.2H1≤H2≤0.7H1.

[0008] In a further embodiment of this application, 0.33H1≤H2≤0.45H1 is adopted.

[0009] In a further preferred embodiment of this application, the first velvet structure includes a plurality of first velvet structures arranged axially upward; wherein the shape of the first velvet structure is pyramidal; and / or the height h1 of the first velvet structure is 2 to 20 μm and the one-dimensional dimension l1 of the base is 1 to 10 μm.

[0010] In a further preferred embodiment of this application, the included angle u between the inner wall of the through hole and the axial direction is 0° to 60°.

[0011] In a further preferred embodiment of this application, the maximum size of the through hole is 10 μm to 200 μm; and / or, the distance D between the centers of two adjacent through holes is 0 to 80 μm.

[0012] In a further preferred embodiment of this application, at least one surface of the silicon wafer substrate perpendicular to the axial direction is provided with a second textured structure, and both the first textured structure and the second textured structure are pyramid structures; at least one of the pyramid height h2 of the second textured structure and the pyramid height h1 of the first textured structure, as well as the pyramid base l2 of the second textured structure and the pyramid base l1 of the first textured structure, is different.

[0013] A second aspect of this application also provides a solar cell, including the silicon wafer provided above; wherein one of the axial surfaces of the silicon wafer substrate is configured as a light-receiving surface and the other as a backlighting surface, and a first textured structure is at least spaced apart from the light-receiving surface.

[0014] In a further preferred embodiment of this application, at least one of the backlight surface and the light-receiving surface is provided with a second velvet structure.

[0015] In a further alternative embodiment of this application, the solar cell further includes a passivation layer covering the light-receiving surface, the backlight surface, and at least a portion of the inner wall of the via.

[0016] In a further optional embodiment of this application, the battery cell also includes an electrode, which includes a plurality of current collectors disposed in the region between the through holes; or, the electrode includes a current collector and a bus electrode, with the current collector disposed in the region between the through holes and the bus electrode disposed in the region between the through holes, or a portion of the bus electrode covers the surface of the through hole portion and another portion is disposed in the region between the through holes.

[0017] This application also provides a photovoltaic module comprising a plurality of the aforementioned solar cells.

[0018] Finally, this application also provides a method for fabricating a solar cell, comprising: providing a silicon wafer substrate; fabricating a plurality of through holes penetrating the silicon wafer substrate; and fabricating a first textured structure on the inner wall of the through holes, wherein at least one end of the first textured structure in the axial direction of the through holes is spaced apart from the axial surface of the silicon wafer substrate.

[0019] In one alternative, a first textured structure is prepared on the inner wall of the through hole, comprising: arranging a protective layer in a spaced region on the inner wall of the through hole; wherein the spaced region is disposed at at least one end of the through hole along the axial direction;

[0020] In one alternative, flocking is performed in the through-hole to form a first flocked structure on the inner wall of the through-hole, comprising: flocking the inner wall of the through-hole to form a through-hole flocked layer; and removing the through-hole flocked layer located in the spacer region to form the first flocked structure.

[0021] In summary, this application arranges a first textured structure within a through-hole, and sets at least one end of the first textured structure along the axial direction of the through-hole to maintain a certain distance from the silicon substrate on a surface perpendicular to the axial direction of the through-hole. In this case, high-angle light can be reflected at least once through the inner wall of the through-hole before entering the first textured structure after incident. Compared with direct incident light onto the textured structure, this application can reduce the probability that high-angle light will be directly reflected once or only slightly by the textured structure before exiting the through-hole, thereby improving the light trapping effect.

[0022] By forming a first textured structure in the via portion to alter the angle of light, the number of reflections of light within the via can be significantly increased, thereby extending the propagation path of light in silicon. In this way, incident light that might otherwise directly penetrate the via or only reflect once or a few times on the surface can now be reflected multiple times within the silicon wafer, increasing the chance of absorption. For example, this allows incident light to undergo at least one reflection on the inner wall of the via after entering it before reaching the first textured structure, reducing the probability of incident light directly passing through the via and improving light utilization. This increases the path length of light within the silicon wafer; due to the extended light path, more light energy is absorbed and converted into electrical energy, thus improving the photoelectric conversion efficiency of the battery.

[0023] Other features and advantages of the embodiments of this application will be described in the following detailed implementation section. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of this application or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A cross-sectional view of a silicon wafer at a through-hole provided in an embodiment of this application (the first textured structure is spaced at only one end);

[0026] Figure 2 A cross-sectional view of a silicon wafer at a through-hole (with the two ends of the first textured structure spaced apart) provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the propagation path of light rays within a through-hole, as shown in the embodiments of this application.

[0028] Figures 4 to 11 These are schematic diagrams of embodiments one through eight of this application, along with the corresponding test results.

[0029] Figure 12The diagram provided in this application shows two adjacent through holes;

[0030] Figure 13 A partial enlarged view of the first textured surface structure inside the through hole provided in this application;

[0031] Figure 14 Cross-sectional views of the two through-hole configurations provided in this application;

[0032] Figure 15 A partially enlarged view of the second textured surface structure of the silicon wafer substrate provided in this application;

[0033] Figure 16 A schematic diagram of a battery cell provided in this application; and

[0034] Figure 17 This is a flowchart illustrating the method for preparing the battery cell provided in this application. Detailed Implementation

[0035] Unless otherwise specified, the terms “second direction,” “first direction,” “third direction,” “inner,” and “outer” used in the following descriptions, indicating orientation or positional relationships, are understood to be based on the orientation or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0036] Furthermore, features specified with "first" or "second" for descriptive purposes only should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features specified with "first" or "second" may explicitly or implicitly include at least one of the specified features. The description of "multiple" generally means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0037] In this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can be a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0038] In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0039] Reference Figure 1 The silicon wafer 100 includes a silicon wafer substrate 10, and the silicon wafer substrate 10 is provided with a plurality of through holes A penetrating the silicon wafer substrate 10.

[0040] It should be noted that the silicon substrate 10 referred to in this application is a silicon substrate that has not undergone special treatment or has only undergone basic preparation, and is not limited to monocrystalline silicon or polycrystalline silicon. The through-hole A is a channel that completely penetrates the silicon substrate 10 to achieve the light transmission effect of the silicon substrate 10, thereby meeting the needs of specific application scenarios, such as building-integrated photovoltaics, so that the crystalline silicon solar panel can maintain a high light transmittance while generating electricity.

[0041] Since the silicon substrate 10 is usually a thin plate, the via A should refer to a hole that runs from one larger surface to the other larger surface on the silicon substrate 10. In simple terms, via A runs through the thickness direction of the silicon substrate 10.

[0042] However, when increasing the light transmittance of the silicon substrate through through-hole A, the incident angle of sunlight on the building photovoltaic glass varies greatly, and the time of vertical incidence is relatively short, with most of the time being oblique incidence. Under oblique incidence conditions, the silicon substrate with holes experiences increased direct light penetration, while the effective absorption path of light inside the cell is reduced, resulting in a significant decrease in light utilization.

[0043] Therefore, this application also provides a first textured structure 20 in the through hole A. Specifically, the first textured structure 20 is disposed on the inner wall of the through hole A, and at least one end of the first textured structure 20 in the axial direction of the through hole A is spaced apart from the surface of the silicon wafer substrate 10 in the axial direction.

[0044] Understandably, the through-hole A penetrates the surface of the silicon substrate 10, forming a connected path. The first textured structure 20 is disposed on the inner wall of the through-hole A, that is, on the side wall of the through-hole A, having a surface structure with a specific roughness or texture, which can change the reflectivity of incident light to improve light absorption efficiency.

[0045] According to the description, "the first textured structure 20 is disposed on the inner wall of the through hole A, and at least one end of the first textured structure 20 in the axial direction of the through hole A is spaced apart from the surface of the silicon substrate 10 in the axial direction", indicating that the first textured structure 20 may be spaced apart from the surface of the silicon substrate only at one end of the through hole A, or it may be spaced apart from the surface of the silicon substrate at both ends.

[0046] In an optional embodiment of this application, the first velvet structure 20 can be pyramidal, serrated, grooved, or other microstructures.

[0047] Through the above design, the first textured structure 20 is arranged within the through-hole, and at least one end of it along the axial direction of the through-hole is positioned at a certain distance from the silicon substrate on a surface perpendicular to the axial direction of the through-hole. It is understood that if the first textured structure 20 covers the entire through-hole A, high-angle incident light entering through-hole A is often easily reflected out of through-hole A upon initial contact with the textured surface, resulting in the light escaping without being fully absorbed. However, this application, by introducing the spaced-apart first textured structure, allows these high-angle light rays, after entering the through-hole, to first change their propagation direction through reflection from the inner wall of the through-hole, and then undergo multiple reflections within the textured structure. Figure 3 As shown, incident light that might have been reflected only a few times within the via A before being emitted can now be reflected multiple times inside the silicon wafer, increasing the chance of absorption. For example, it allows incident light to be reflected at least once on the inner wall of via A before reaching the first textured structure 20, reducing the probability of incident light directly passing through the via and helping to improve light utilization. This increases the path length of light inside the silicon wafer. Due to the extended light path, more light energy is trapped and converted into electrical energy, thereby improving the photoelectric conversion efficiency of the battery.

[0048] To clearly illustrate this solution, as follows: Figures 1 to 3 The silicon substrate 10 has a first surface b1 and a second surface b2 in the axial direction. The first surface b1 and the second surface b2 should be understood as two opposing surfaces with a larger area on the silicon substrate 10, namely the two surfaces mentioned above that are perpendicular to the axial direction.

[0049] In one embodiment, such as Figure 1 As shown, the first textured structure 20 is flush with the first surface b1 of the silicon substrate 10 at one end in the axial direction, and spaced apart from the second surface b2 of the silicon substrate 10 by a distance d1 at the other end.

[0050] In this embodiment, the first textured structure 20 is flush with the first surface b1, and the second surface b2 is spaced apart by a distance d1. If incident light enters from the second surface b2, it can first be reflected by the inner wall of the through-hole A, and then enter the first textured structure 20, thereby improving the light trapping rate and helping to improve the efficiency of photoelectric conversion devices such as solar cells.

[0051] In one embodiment, such as Figure 2 As shown, the first textured structure 20 is spaced apart from the first surface b1 and the second surface b2 of the silicon substrate 10 at both ends in the axial direction, wherein the first textured structure 20 and the first surface b1 are spaced apart by d2, and the second surface b2 is spaced apart by d3.

[0052] Similarly, in this embodiment, the first textured structure 20 is spaced apart from the two surfaces of the silicon wafer (i.e., the first surface b1 and the second surface b2) at its two ends along the axial direction. This ensures that regardless of which side the light enters from, it is effectively captured and reflected by the textured structure after being reflected by the area without the textured structure on the inner wall of the through-hole A, thus improving the light trapping efficiency. More importantly, traditional solar cell designs may require distinguishing between the light-receiving surface and the back-lighting surface, while this design eliminates the need for such distinction during the manufacturing process. Furthermore, this design can improve the bifaciality of the solar cell using this silicon wafer, thereby increasing the cell's power generation efficiency.

[0053] In the optional schemes of this application, distances d2 and d3 can be equal or unequal, and can be adaptively set according to the actual situation.

[0054] When the distances d2 and d3 are not equal, the distance d3 may be greater than the distance d2 to increase the probability that large-angle light rays entering the through hole A from the second surface b2 will be reflected by the inner wall of the through hole A first, rather than directly incident on the first velvet structure 20.

[0055] In a modified embodiment of this application, the first textured surface structure 20 in the through hole A can be continuous or spaced out in the axial and / or circumferential directions. For example, if the first textured surface structure 20 is spaced out in the axial direction, such as segmented, with a gap between each segment in the axial direction; or, the first textured surface structure 20 can also be segmented in the circumferential direction. Whether segmented in the axial or circumferential direction, it can improve light absorption efficiency while also achieving a passivation effect within the hole, thus overcoming the passivation difficulties caused by the textured surface structure within the through hole A, thereby improving overall performance.

[0056] In this embodiment, the axial height of the through-hole A is defined as the first height H1, and the axial height of the first textured structure 20 and the distance between its surface perpendicular to the axial direction is defined as the second height H2. The first height H1 is defined as the depth of the entire through-hole A, i.e., the distance from the first surface b1 to the second surface b2 of the silicon substrate 10, which can also be understood as the thickness of the silicon substrate 10. It should be noted that H1 refers to the silicon wafer thickness, i.e., the original thickness without considering any new fabrication layers (such as passivation layers) that may be subsequently formed on this surface. The second height H2 is defined as the axial distance between the first textured structure 20 and the second surface b2.

[0057] It should be noted that in the two cases where one end of the first textured structure 20 is spaced from the surface of the silicon substrate 10, or both ends are spaced from the surface of the silicon substrate 10, the second height H2 refers to the distance between the first textured structure 20 and the first surface b1 and the second surface b2. That is, when one end of the first textured structure 20 is spaced from the surface of the silicon substrate 10, the second height H2 refers to d1 mentioned above, and when both ends are spaced from the surface of the silicon substrate 10, the second height H2 refers to the sum of d2 and d3 mentioned above.

[0058] In the optional scheme of this application, 0.2H1≤H2≤0.7H1, that is, the pile height H3 is between 0.3H1 and 0.8H1.

[0059] Optical path calculations show that when H2 is greater than 0.7H1, the number of reflections of light in the light-trapping structure decreases. This means that due to the larger spacing, the texturing height is lower, and incident light can more easily penetrate the structure after fewer reflections, resulting in a reduced light path. This is detrimental to light absorption and leads to a low light-trapping rate. Conversely, when H2 is less than 0.2H1, the probability of incident light reflecting to the bottom of the through-hole A increases, especially for large-angle incident light. Light entering from one end of through-hole A and reflecting on the first texturing structure 20 may exit directly from the same end of through-hole A, meaning it is more likely to escape without being absorbed, thus increasing light transmittance and hindering light absorption.

[0060] As a further aspect of this application, 0.45H≤H2≤0.67H1, that is, the height H3 of the velvet surface is between 0.33H1 and 0.55H1, which can more precisely enable the light to undergo a sufficient number of reflections inside the structure, thereby further extending the path of the light in the structure and improving the light absorption efficiency.

[0061] Therefore, the preferred range proposed above balances the number of reflections of light in the light-trapping structure with the need to prevent direct light escape, aiming to optimize the light reflection path, increase the number of reflections of light in the through-hole, and enhance light utilization. Within this range, light can undergo sufficient reflections to increase light absorption, while reducing the probability of large-angle incident light escape due to excessive texturing height, further improving the light trapping rate and thus improving the photoelectric conversion efficiency of the solar cell. In this application, large-angle incident light is defined as light with an angle of 30° to 90° with the axis, and small-angle incident light is defined as light with an angle of ≤30° with the axis.

[0062] When light is incident, it is first reflected by the inner wall of the aperture, increasing the absorption of the crystalline silicon by increasing the optical path. However, when the incident light is at a large angle, the preferred range of the second height H2 allows the light to reach the inner wall and be reflected by the inner wall of the aperture onto the first textured structure. The first textured structure can reflect and trap light multiple times, and it still has the same good light-trapping effect for small-angle incident light. For silicon wafers with this proposal, in addition to being used in glass curtain walls, they can also meet the needs of other installation scenarios, greatly improving the light absorption capability of silicon wafers at all angles.

[0063] like Figures 4 to 11 Based on the aforementioned preferred range, starting from a predetermined reference date, at two fixed, pre-set locations, on dates of equal intervals (for example, starting from January 1st, taking March 22nd, June 22nd, September 22nd, and December 22nd as the calculation dates), the following structures are measured sequentially:

[0064] Table 1

[0065]

[0066] Table 2

[0067]

[0068] like Figure 4 As shown, in Example 1, a vertical through-hole with a diameter of 70 μm was used at 30° North latitude, and the texturing height was 150 μm. The test results showed that the light transmittance throughout the year was less than 6%. The average light transmittance from March to September was less than 3%. Compared with the 7% in Reference Example 1 before texturing, it can be seen that the improvement in light trapping effect is not significant.

[0069] like Figure 5As shown, in Example 2, a vertical through-hole with a diameter of 70 μm was used at 30° North latitude, and the texturing height was 100 μm. The test results showed that the annual light transmittance was less than 2.8%. The average light transmittance from March to September was less than 0.4%. Compared with the 7% before texturing in Reference Example 1, it can be seen that the light trapping effect is significantly improved.

[0070] like Figure 6 In Example 3, a vertical through-hole with a diameter of 70 μm was used at 30° North latitude, and the texturing height was 68 μm. The test results showed that the light transmittance was less than 3.5% throughout the year. The average light transmittance from March to September was less than 0.1%. Compared with the 7% before texturing in Reference Example 1, the light trapping effect was significantly improved.

[0071] like Figure 7 In Example 4, a vertical through-hole with a diameter of 70 μm was used at 40° North latitude, and the texturing height was 68 μm. The test results showed that the light transmittance was less than 10% throughout the year. The average light transmittance from March to September was less than 1%. Compared with 18.5% before texturing in Reference Example 2, the light trapping effect was significantly improved.

[0072] like Figure 8 In Example 5, a vertical through-hole with a diameter of 70 μm was used at 40° North latitude, and the texturing height was 100 μm. The test results showed that the light transmittance was less than 6% throughout the year. The average light transmittance from March to September was less than 1.5%. Compared with 18.5% before texturing in Reference Example 2, the light trapping effect was significantly improved.

[0073] like Figure 9 In Example 6, a vertical through-hole with a diameter of 50 μm was used at 40° North latitude, with a texturing height of 68 μm, resulting in an annual light transmittance of less than 4.5%. The average light transmittance from March to September was less than 0.1%. Compared to the 10% light transmittance before texturing in Reference Example 3, the light trapping effect was significantly improved.

[0074] like Figure 10 In Example 7, a vertical through-hole with a diameter of 50 μm was used at 40° North latitude, and the texturing height was 100 μm. The annual light transmittance was less than 1.3%. The average light transmittance from March to September was less than 0.5%. Compared with the 10% light transmittance before texturing in Reference Example 3, the light trapping effect was significantly improved.

[0075] like Figure 11 In Example 8, a vertical through-hole with a diameter of 50 μm was used at 30° North latitude, and the texturing height was 100 μm. The annual light transmittance was less than 1.2%. The average light transmittance from March to September was less than 0.2%. Compared with 2.5% before texturing in Reference Example 4, the light trapping effect was improved to a certain extent.

[0076] From the test results of the above embodiments and corresponding reference examples, it can be seen that:

[0077] 1) In all embodiments, the light transmittance after texturing was significantly reduced compared to the respective reference examples (i.e., before texturing), which all demonstrates that the texturing structure effectively enhances the light-trapping ability of the silicon wafer. This is because the texturing structure can increase the number of light scattering and reflections, thereby lengthening the light propagation path in the silicon wafer, increasing light absorption, and reducing transmission.

[0078] 2) Under the same texturing height and geographical location, embodiments with smaller diameters generally exhibit lower light transmittance. For example, comparing Embodiments 4 and 6 (both at 40° North latitude, texturing height 68µm), when the diameter was reduced from 70µm to 50µm, both the annual light transmittance and the average light transmittance for a specific month decreased significantly. This may be because a smaller diameter helps to guide light more concentratedly into the silicon wafer and increases the number of reflections of light in the texturing structure.

[0079] like Figure 12 Furthermore, the vias A are arranged in an array on the silicon substrate 10, with the maximum size r of a single via A ranging from 10 μm to 200 μm, and the center-to-center distance D between two adjacent vias A ranging from 0 μm to 80 μm. By setting an appropriate via size r and adjusting the center-to-center distance D between adjacent vias, it is possible to ensure sufficient structural strength of the silicon substrate while maintaining good light transmittance.

[0080] The "maximum dimension" mentioned above is defined as follows: when the projected shape of the through hole A along the axial direction is not circular, its one-dimensional dimension (i.e., the maximum dimension) is defined as the farthest distance between the boundary points of the projected shape. When the projected shape is circular, the one-dimensional dimension corresponds to the diameter of the circle.

[0081] As can be seen from the above embodiments, in the embodiments of this application, when 0.33H1≤H2≤0.55H1, the diameter of the through hole A is preferably 50um to 70um, more preferably 50um.

[0082] like Figure 13 Furthermore, the first velvet structure 20 is pyramidal in shape; the pyramidal structure, due to its sharp apex and multiple sloping surfaces, can effectively scatter incident light, causing the light to undergo multiple reflections and refractions inside the through hole A, thereby increasing the optical path and improving the light absorption rate.

[0083] It should be noted that the first textured structure 20, arranged along the axial and circumferential directions, significantly increases the surface roughness of the silicon wafer, thereby enhancing light scattering and trapping. This structure helps guide incident light into the interior of the silicon wafer, increasing the optical path and improving light absorption efficiency. Simultaneously, the pyramidal structure can also reduce direct light reflection and transmission to some extent, improving the photoelectric conversion efficiency of the solar cell.

[0084] Furthermore, the tower height h1 of the first textured structure 20 is 2 to 20 μm, and the tower base l1 is 1 to 10 μm. By setting appropriate dimensions for the first textured structure 20, while satisfying process feasibility, it is possible to ensure that the first textured structure 20 effectively receives and reflects light in the through hole A, and at the same time, the space occupied by the first textured structure 20 in the through hole A is limited, so as not to significantly block the light transmittance of the through hole A.

[0085] Wherein, the tower height h1 is the radial distance between the point of the first velvet structure 20 closest to the central axis of the through hole (i.e., the vertex of the first velvet structure 20 in the radial direction) and the inner wall of the through hole. The one-dimensional dimension l1 of the tower base is the depth of the first velvet structure 20 in the axial direction. Since the base of the pyramid may be quadrilateral (such as a square or rectangle) or a more complex shape, l1 is the maximum length of the base of the pyramid in the axial direction.

[0086] Understandably, the first textured structure 20 exists in a pyramid shape within the through-hole, and its height h1 and the one-dimensional dimension l1 of the base together determine the number, size, and shape of the pyramids. The height h1 represents the distance from the top of the pyramid to the inner wall of the through-hole, which can affect the lateral angle of the pyramid-shaped structure, thereby affecting the angle of light reflection inside the pyramid. The one-dimensional dimension l1 of the base, the distance of the pyramid's base surface in the axial direction, can also determine the number of the first textured structures 20 at the same second height H2.

[0087] Those skilled in the art will understand that, in order to obtain the best photoelectric conversion efficiency, the dimensional parameters of the pyramid structure need to be optimized according to the aperture size of the through-hole A. The optimization principle is to prevent the first textured structure 20 from overfilling the through-hole A. For example, the pyramid height h1 of the first textured structure 20 cannot completely fill the inner diameter of the through-hole A in the radial direction. This avoids reducing the light transmittance of the through-hole A and the coating quality of the subsequent solar cell fabrication.

[0088] like Figure 14 Furthermore, the shape of the through-hole A can be any of the following: cylindrical, frustum, polyhedral truncated pyramid, cuboid, or spherical. When the through-hole A is spherical, its ends are all planar. Simply put, at the junction of the spherical through-hole A and the surface of the silicon substrate 10, the ends of the spherical through-hole A and the surface of the silicon substrate 10 are also planarized to form a spherical through-hole A with planar ends.

[0089] In some embodiments, when the inner wall of the via is perpendicular to the surface of the silicon substrate 10, the via A can be cylindrical or cuboid.

[0090] In another embodiment, when the axial angle u between the inner wall of the cross section and the through hole A is greater than 0° and less than or equal to 60°, the through hole A can be either a frustum or a truncated cone.

[0091] Understandably, cylindrical and cuboid vias are relatively simple to manufacture, which helps reduce production costs and improve yield. Furthermore, the vertical inner walls make the via structure more stable, preventing a reduction in the strength of the silicon wafer structure. When using frustum or truncated cones, the via A has an inclined inner wall, which can more effectively reflect light entering the via. Through multiple reflections and refractions, the optical path length within the silicon wafer is increased, improving light absorption efficiency. In particular, using one end of the larger aperture of via A as the light-receiving surface allows via A to capture light over a wider range of angles, including light incident obliquely onto the silicon wafer surface. This helps maintain high photoelectric conversion efficiency even under poor lighting conditions.

[0092] In a preferred embodiment of this application, the included angle u is greater than 0° and less than or equal to 60°. Within this angle range, the inner wall of the via can effectively reflect the incoming light. By precisely controlling the included angle, light can undergo multiple reflections and refractions within the silicon wafer, thereby increasing the optical path and improving light absorption efficiency. Furthermore, an included angle within this range typically does not result in an overly sharp or fragile via structure, reducing fabrication difficulty and ensuring sufficient mechanical strength.

[0093] In some embodiments, the through hole A may also be a combination of multiple shapes. For example, the through hole A may include a cylindrical shape and a frustum shape that are radially interconnected; the included angle u between the inner wall of the frustum-shaped region and the axial direction is still greater than 0° and less than or equal to 60°.

[0094] On the first or second surface, the total area of ​​the through hole A accounts for 10% to 70% of the area of ​​the first or second surface.

[0095] When the area of ​​via A is small (less than 10%), while maintaining high mechanical strength, it significantly restricts light transmission. Because light cannot fully penetrate the silicon wafer, the light trapping rate decreases, thus affecting photoelectric conversion efficiency. Conversely, when the area of ​​via A is large (greater than 70%), it weakens the overall structure of the silicon wafer and reduces its mechanical strength. Under the influence of external environments, such as wind and temperature changes, the silicon wafer may be more prone to deformation, cracking, or even breakage, thus affecting the stability and lifespan of the device. Within the above range, good light transmittance can be ensured while maintaining sufficient mechanical strength of the silicon wafer.

[0096] It should be noted that the total area of ​​through hole A is the sum of the areas of holes on the first surface b1 or the second surface b2. For example, on the first surface b1, if the area of ​​a single through hole A is m1 and the number is n, then the total area of ​​through hole A is n multiplied by m1. In addition, those skilled in the art will know that when through hole A is a cuboid or a cylinder, the total area of ​​through hole A on the first surface b1 and the second surface b2 is the same; when through hole A is a frustum shape, the total area of ​​through hole A on one side is greater than the total area of ​​through hole A on the other side.

[0097] like Figure 14 The silicon substrate 10 has a second textured structure 30 on at least one surface in the axial direction. The tower height h2 of the second textured structure 30 and the tower height h1 of the first textured structure 20, as well as the tower base l2 of the second textured structure 30 and the tower base l1 of the first textured structure 20, are at least one different.

[0098] The second textured structure 30 has a textured pyramid formed by four crystal faces on its surface and bottom, namely [1,1,1], [-1,1,1], [1,-1,1], and [-1,-1,1]. This structure helps to increase the light absorption capacity of the silicon wafer surface because the pyramid structure can more effectively capture and scatter incident light.

[0099] The textured pyramid crystal planes on the inner sidewall of the hole are configured as [1,1,1], [-1,1,1], [1,1,-1], [-1,1,-1] (or another possible combination [1,1,1], [1,-1,1], [1,1,-1], [1,-1,-1]). Due to the difference in crystal orientation between the first textured structure 20 and the second textured structure 30, the second textured structure 30 on the surface of the silicon substrate 10 and the first textured structure 20 inside the hole will differ in size.

[0100] In one possible embodiment, due to the change in crystal orientation, the growth rate of the first textured structure 20 on the inner sidewall of the hole may be different from that of the second textured structure 30 on the surface, resulting in a change in the tower height. Specifically, the tower height h2 of the second textured structure 20 is higher than the tower height h1 of the first textured structure 10.

[0101] In another possible embodiment, the crystal orientation change may affect the base extension of the textured pyramid, resulting in a change in the base size. Specifically, the base l2 of the second textured structure 20 is greater than the height l1 of the first textured structure 10.

[0102] Alternatively, the crystal orientation change affects both the tower height and the tower base size. Specifically, the tower base l2 of the second textured structure 20 is greater than the tower height l1 of the first textured structure 10, while the tower height h2 of the second textured structure 20 is greater than the tower height h1 of the first textured structure 10.

[0103] Due to the change in crystal orientation, at least one of the following is different: the tower height h2 of the second textured structure 30 and the tower height h1 of the first textured structure 20, as well as the tower base l2 of the second textured structure 30 and the tower base l1 of the first textured structure 20. The specific difference depends on the material properties of crystalline silicon, the preparation conditions, and the specific influence of the change in crystal orientation on crystal growth.

[0104] Understandably, the second textured structure 30 is used for surface light trapping of the silicon substrate 10, while the first textured structure 20 is used for light trapping in the via A. Because the light paths on the silicon surface and in the via are different—surface light is directly incident, while light in the via may undergo multiple reflections and refractions—different textured structure sizes are needed to optimize the optical effects under these two different conditions. Both surface and via light trapping can reduce light loss from the silicon substrate and improve light energy utilization. Furthermore, due to the difference in tower height and base dimensions between the second textured structure 30 and the first textured structure 20, optimal light trapping performance is provided for both surface and via light trapping on the silicon substrate 10.

[0105] In an optional embodiment of this application, the silicon substrate 10 has a second textured surface structure 30 on both the first surface b1 and the second surface b2.

[0106] like Figure 16 The second aspect of this application also provides a battery cell 200, including the silicon wafer 100 as described above; wherein, one of the axial surfaces of the silicon wafer substrate 10 is configured as a light-receiving surface and the other is configured as a backlight surface, a first textured structure 20 is at least spaced from the light-receiving surface, and a second textured structure 30 is provided on at least the light-receiving surface.

[0107] Furthermore, the battery cell 200 also includes one or more passivation layers 201, which cover the light-receiving surface, the backlight surface, and at least part of the inner wall of the through hole A.

[0108] In the optional embodiments of this application, the passivation layer 201 is at least one or more of amorphous silicon, silicon oxide, silicon nitride, doped polycrystalline silicon, and aluminum oxide.

[0109] Understandably, the second textured structure 30 differs in scale from the via A. Specifically, the second textured structure 30 is typically designed as a hybrid structure of micrometer- and nanometer-scale pyramids. This tiny structure helps form more light traps on the silicon wafer surface, increasing light scattering and absorption. The via A, on the other hand, is a micrometer-scale structure, enhancing light capture and internal scattering while providing additional paths for carrier flow. Both the nanometer-scale second textured structure and the inner wall of the via A significantly increase the effective surface area of ​​the silicon wafer. This increased surface area helps capture more light and provides more locations for photogenerated carriers. Furthermore, the relatively large size of the via A facilitates the formation of a uniform passivation layer within the hole, more effectively reducing defects and dangling bonds on the silicon wafer surface, thereby lowering the surface recombination rate.

[0110] The battery cell 200 also includes an electrode 202, which includes a plurality of collector electrodes 2021 disposed in the region between the through holes A.

[0111] Understandably, the collector 2021 is typically designed as a thin metal line that tightly covers the surface of the solar cell, particularly in the area between the vias A. The collector 201 can more effectively collect the current generated by photogenerated carriers. Because the collector 201 is thin and uniformly distributed, it can significantly reduce the series resistance of the solar cell, thereby improving the fill factor and photoelectric conversion efficiency.

[0112] In an optional embodiment of the present invention, electrode 202 further includes bus electrode 2022, which is disposed in the region between the through holes A, or a portion of the bus electrode covers the surface of a portion of the through hole A, and another portion is disposed in the region between the through holes A.

[0113] The bus electrode 2022 can serve as the current collection point for the current collector. Positioning the bus electrode 2022 in the region between the vias A ensures close contact with the region where photogenerated carriers are generated, improving current collection efficiency. Alternatively, part of the bus electrode 2022 can be placed covering part of the surface of the via A, while another part is located in the region between the vias A. This improves both the connection stability of the bus electrode 2022 and ensures good current collection efficiency. The specific design depends on the overall layout and performance requirements of the solar cell 200.

[0114] It should be noted that the area between vias A represents the portion located on the surface of silicon wafer 100 that is not occupied by vias A.

[0115] Furthermore, electrodes 202 in the silicon substrate 10 are disposed on the light-receiving surface and the back-lighting surface to form, for example, PERC cells, TOPCon cells, HJT cells, and bifacial high-low temperature hybrid cells.

[0116] In an optional embodiment of this application, the silicon substrate 10 is either an N-type crystalline silicon substrate or a P-type crystalline silicon substrate, and a passivation layer 201 is provided on both its light-receiving surface and back-lighting surface. Optionally, the passivation layer 201 on the light-receiving surface is an aluminum oxide and silicon nitride film, and the passivation layer 201 on the back-lighting surface includes an ultrathin silicon oxide layer and a doped polycrystalline silicon thin film superimposed, as well as an aluminum oxide and silicon nitride film, thereby forming a TOPCon type battery.

[0117] In a further optional embodiment of this application, the electrodes 202 in the silicon substrate 10 may all be disposed on the back surface to form a back contact cell, such as a passivated contact back contact cell, a heterojunction back contact cell, and a hybrid passivated back contact cell, and are not limited to the back contact cell types mentioned in the examples.

[0118] Furthermore, those skilled in the art should understand that if all or part of the sub-modules involved in each layer of the silicon substrate 10 provided in the embodiments of this application are combined or replaced through fusion, simple changes, mutual transformations, etc., such as moving the positions of each component, any combined components can form a structure with a specific function, and using such a structure to replace the corresponding components of this application also falls within the protection scope of this application.

[0119] This application also provides a photovoltaic module, including several solar cells 200 as described above.

[0120] like Figure 17 Furthermore, embodiments of the present invention also provide a method for preparing a battery cell, comprising:

[0121] Step S10: Provide a silicon wafer substrate;

[0122] In this step, the doping type of the silicon substrate is not limited; it can be an n-type silicon substrate prepared from an n-type crystalline silicon wafer, and the specific type can be adapted according to requirements. The thickness of the silicon substrate can be 150 micrometers. The silicon substrate can be monocrystalline or polycrystalline.

[0123] Step S20: Prepare several through holes penetrating the silicon substrate at the silicon wafer substrate;

[0124] In the above steps, the surface of the prepared textured silicon substrate is coated with photoresist, and after illumination using a mask with a corresponding pattern, the photoresist in the unmasked areas is washed away, forming the corresponding hole structure. Further, Deep Reactive Ion Etching (DRIE), a high aspect ratio silicon etching technology based on fluorine-based gases, is employed. Fluorine-based gases (such as SF6, C4F8, etc.) are used as etching gases. These gases have a high etching rate in plasma conditions and can interact with the hole locations on the silicon substrate through chemical reactions, achieving precise etching to form multiple through-holes at these locations. After etching, the photoresist and polymer residues on the silicon wafer surface need to be removed, followed by cleaning and drying.

[0125] The one-dimensional size of a single via is 10um to 200um, the center distance D between two adjacent vias is 0 to 80um, and the total area of ​​the vias accounts for 10% to 70% of the area of ​​the first or second surface of the silicon substrate.

[0126] The shape of the through hole is not limited; it can be any of the following: cylindrical, pyramidal, inverted pyramidal, frustum, cuboid, or sphere.

[0127] Step S30: A first textured structure is prepared on the inner wall of the through hole, wherein at least one end of the first textured structure in the axial direction of the through hole is spaced apart from the surface of the silicon substrate in the axial direction.

[0128] In one alternative embodiment, step S30 includes:

[0129] Step S31: Arrange a protective layer in the interval region of the inner wall of the through hole; wherein the interval region is located at at least one end of the through hole along the axial direction;

[0130] A ring-shaped protective layer is coated on the inner wall A of the through-hole. The material of this protective layer can be silicon oxide (SiO2), polycrystalline silicon, or other suitable materials, depending on the process requirements and material properties.

[0131] Step S32: Remove the textured layer of the through hole located in the interval region, wherein the interval region is provided at at least one end of the through hole along the axial direction to form a first textured structure in the area of ​​the inner wall of the through hole other than the interval region.

[0132] Under the protection of the protective layer, appropriate processes (such as wet etching, dry etching, or selective etching after chemical vapor deposition) are used to ensure that the textured structure is formed only at the desired location on the inner wall of the via.

[0133] Understandably, after completing the fabrication of the first textured surface, the protective layer can be removed as needed. That is, the protective layer can be retained as a passivation layer. Alternatively, it can be removed using chemical cleaning, laser ablation, or other appropriate methods.

[0134] In another alternative embodiment, step S30 includes:

[0135] Step S31': Texturing the inner wall of the through hole to form a textured surface layer;

[0136] First, a textured surface structure, i.e., a textured surface layer for the through hole, is formed on the inner wall of the through hole using appropriate processes (such as the aforementioned wet etching, dry etching, etc.).

[0137] Step S32': Remove the textured layer of the through hole located in the interval region, wherein the interval region is provided at least one end of the through hole along the axial direction to form a first textured structure in the area of ​​the inner wall of the through hole other than the interval region.

[0138] The textured surface of the silicon wafer substrate is removed by using laser ablation, wet etching, or other precisely controlled methods to remove the textured surface of the area spaced axially from the vias, thereby forming the first textured surface.

[0139] For the former process, the protective layer is formed before the texturing structure is created, effectively preventing damage or contamination to the silicon substrate during subsequent texturing processes and maintaining the integrity and cleanliness of the substrate surface as much as possible. For the latter process, the texturing structure is first formed on the entire surface, and then the texturing structure in specific areas is removed as needed. This method offers greater flexibility, allowing the size and shape of the removed area to be adjusted according to actual needs and process conditions. Of course, in practical applications, the choice and adjustment can be made based on the specific circumstances.

[0140] In this embodiment of the application, the method further includes:

[0141] Step S40: Prepare a passivation layer on the light-receiving surface, the back-lighting surface, and at least part of the inner wall of the through hole;

[0142] A passivation layer is deposited on the inner wall of the second textured structure and the through-hole. The passivation layers on the back side and the light-receiving side can be the same or different, and the passivation layer can be one or more layers.

[0143] In one embodiment, the passivation layer is multilayered, with the first passivation layer being silicon oxide, which serves as a surface passivation layer; and then, multilayer silicon nitride is prepared on the first passivation layer, with silicon oxide and silicon nitride forming a multilayer structure.

[0144] In one embodiment, the first passivation layer is an ultrathin silicon oxide layer, and at least one layer of multilayer silicon nitride doped polycrystalline silicon thin film is further prepared on the first passivation layer.

[0145] In this embodiment of the application, the method further includes:

[0146] Step S50: Prepare an electrode on at least one of the light-receiving surface and the backlighting surface.

[0147] In this step, the electrodes can be placed on both sides or on one side.

[0148] The electrode includes several collectors, which are disposed in the region between the through holes.

[0149] In some embodiments, the bus electrode is disposed in the region between the through holes, or a portion of the bus electrode covers the surface of the through hole A portion and another portion is disposed at the second textured structure.

[0150] It is understood that the manufacturing process steps S10 to S40 of the embodiments of the present invention can be configured according to the requirements of the type of battery cell, which includes, but is not limited to, TOPCon batteries or back contact batteries.

[0151] In this embodiment of the application, the method further includes:

[0152] Step S11: Fabricate a second textured structure on at least one surface of the silicon wafer substrate.

[0153] Furthermore, a second textured structure can be formed on at least one surface of the silicon wafer substrate by a texturing process, thereby preparing a textured structure composed of pyramid and / or inverted pyramid structures.

[0154] Of course, the above steps can be performed in any order. For example, after providing a silicon wafer substrate, a through-hole can be formed first, followed by the formation of a second textured structure, and then the first textured structure can be prepared in the through-hole. That is, the first textured structure can be formed together with the second textured structure, or it can be formed before or after the second textured structure. Regardless of which sequence variation is used, the step sequence and process parameters can be flexibly adjusted according to the specific production process flow, equipment layout environment, and type of solar cell being produced.

[0155] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still adjust the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; and these adjustments or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A silicon wafer, characterized by, include: A silicon substrate (10) is provided with a through hole (A) penetrating the silicon substrate (10); as well as A first textured structure (20) is disposed on the inner wall of the through hole (A), and at least one end of the first textured structure (20) along the axial direction of the through hole (A) is spaced apart from the surface of the silicon substrate (10) perpendicular to the axial direction.

2. The silicon wafer according to claim 1, characterized in that, The height of the through hole (A) along the axial direction is the first height H1, and the distance between the surface of the first velvet structure (20) along the axial direction and perpendicular to the axial direction is the second height H2, wherein 0.2H1≤H2≤0.7H1.

3. The silicon wafer according to claim 2, characterized in that, 0.33H1≤H2≤0.45H1.

4. The silicon wafer according to claim 1, characterized in that, The first velvet structure (20) is pyramidal in shape; and / or The tower height h1 of the first velvet structure (20) is 2 to 20 μm and the tower base l1 is 1 to 10 μm.

5. The silicon wafer according to claim 1, characterized in that, The angle u between the inner wall of the through hole (A) and the axial direction is 0° to 60°.

6. The silicon wafer according to claim 1, characterized in that, The maximum size of the through hole (A) is 10 μm to 200 μm; And / or, The distance D between the centers of two adjacent through holes (A) is 0 to 80 μm.

7. The silicon wafer according to any one of claims 1 to 6, characterized in that, The silicon substrate (10) has a second textured surface structure (30) on at least one surface perpendicular to the axial direction. Both the first velvet structure (20) and the second velvet structure (30) are pyramid structures; The tower height h2 of the second velvet structure (30) and the tower height h1 of the first velvet structure (20), as well as the tower base l2 of the second velvet structure (30) and the tower base l1 of the first velvet structure (20), are at least different.

8. A battery cell, characterized in that, The silicon wafer includes the silicon wafer as described in any one of claims 1 to 7; wherein one of the surfaces of the silicon wafer substrate (10) perpendicular to the axial direction is configured as a light-receiving surface and the other as a backlight-receiving surface, and the first textured structure (20) is at least spaced apart from the light-receiving surface.

9. The battery cell according to claim 8, characterized in that, The battery cell also includes a passivation layer (201) that covers at least a portion of the inner wall of the light-receiving surface, the backlight surface, and the through-hole (A).

10. The battery cell according to claim 8, characterized in that, The battery cell also includes electrodes (202), the electrodes including a plurality of collector electrodes (2021), the collector electrodes (2021) being disposed in the region between the through holes (A); Alternatively, the electrode may include a collector electrode (2021) and a bus electrode (2022), wherein the collector electrode (2021) is disposed in the region between the through holes (A) and the bus electrode (2022) is disposed in the region between the through holes (A), or a portion of the bus electrode (2022) may cover a portion of the surface of the through holes (A) and the other portion may be disposed in the region between the through holes (A).

11. A photovoltaic module, characterized in that, Includes the battery cell as described in any one of claims 8 to 10.

12. A method for preparing a solar cell, comprising: Provide a silicon substrate; A plurality of through holes penetrating the silicon wafer substrate are formed therethrough; A first textured structure is prepared on the inner wall of the through hole, wherein at least one end of the first textured structure in the axial direction of the through hole is spaced apart from the surface of the silicon substrate in the axial direction.

13. The preparation method according to claim 12, characterized in that, The preparation of the first velvet structure on the inner wall of the through hole includes: A protective layer is arranged in a spaced region on the inner wall of the through hole; wherein the spaced region is located at at least one end of the through hole along the axial direction; Pile fabrication is performed in the through-hole to form the first pile structure in the area of ​​the inner wall of the through-hole excluding the spacer area.

14. The preparation method according to claim 12, characterized in that, The preparation of the first velvet structure on the inner wall of the through hole includes: The inner wall of the through hole is flocked to form a flocked surface layer. Remove the velvet layer from the through-hole located in the spacer region, wherein the spacer region is located at at least one end of the through-hole along the axial direction, so as to form the first velvet structure in the area of ​​the inner wall of the through-hole other than the spacer region.

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