Memory management method and memory controller

Abstract

The present disclosure provides a memory management method and a memory controller. The method obtains a plurality of virtual blocks and corresponding error bit statistical information of a memory module, evaluates the health status of each virtual block, and selects a target virtual block with poor health status. An enhanced block mapping operation is performed on the target virtual block, and the physical blocks in the target virtual block are paired and mapped into enhanced blocks. When writing data, the data is written into two physical blocks of an enhanced block in parallel; when reading data, one of the two physical blocks is selected for reading according to a preset reading strategy. The present disclosure provides additional data protection in the aging stage of the storage device through dynamic enhanced block mapping and round-robin reading strategy, prolongs the service life of the device, and dynamically balances between data security and storage capacity.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a memory management method and memory controller for managing physical blocks with poor health conditions. Background Technology

[0002] Solid-state drives (SSDs), as primary storage devices, have a lifespan limited by the finite number of erase cycles required for NAND flash memory. Once a flash block reaches its erase cycle threshold, its error probability rate (EPR) increases, increasing the likelihood of failure and reducing device reliability. Traditional storage management methods often recommend discontinuing use after a device reaches its expected lifespan to prevent data loss, leading to premature device obsolescence and resource waste.

[0003] Current technologies lack effective mechanisms to ensure the safe use of storage devices during their aging phase, particularly methods for dynamically adjusting data protection strategies based on device health. Furthermore, existing RAID protection schemes are mostly statically configured, unable to dynamically adjust according to the actual condition of the device, and unable to achieve a flexible balance between capacity requirements and data security. Summary of the Invention

[0004] In view of this, this disclosure provides a memory management method and a memory controller that provides additional data protection for the aging phase of the storage device through an enhanced block mapping method that is linked to the health status of physical blocks, maintains the data reliability of the storage device, and achieves a dynamic balance between capacity requirements and data security.

[0005] This disclosure provides a memory management method applied to a storage device configured with a memory module. The method includes: evaluating the health status of multiple virtual blocks of the memory module; selecting one or more target virtual blocks from the multiple virtual blocks based on the health status of each virtual block, wherein the health status of the one or more target virtual blocks is lower than the health status of other virtual blocks; performing an enhancement block mapping operation on each target virtual block, pairing multiple entity blocks within the target virtual block in pairs, mapping each pair of paired entity blocks to an enhancement block; when writing target data to a target enhancement block, writing the target data in parallel to a first entity block and a second entity block of the target enhancement block; and when reading the target data from the target enhancement block, selecting either the first entity block or the second entity block to read the target data according to a preset read strategy.

[0006] This disclosure also provides a memory controller for controlling a storage device configured with a memory module. The memory controller includes a memory interface control circuit electrically connected to the memory module, and a processor electrically connected to the memory interface control circuit. The processor is further electrically connected to a connection interface circuit of the storage device for electrical connection to a host system. The processor is configured to execute the memory management method described above.

[0007] Based on the above, the memory management method and memory controller provided in this disclosure can achieve precise monitoring and predictive maintenance of the memory module status by acquiring error bit statistics and assessing the health status of virtual blocks. By selecting target virtual blocks with poor health status to perform enhanced block mapping operations, the enhanced block mechanism provides additional protection for high-risk physical blocks, maintaining data reliability. The design of pairing and mapping physical blocks within the target virtual block to enhanced blocks implements a mirror backup mechanism. When any physical block fails, data can be recovered from the other physical block, improving data reliability. In addition, the parallel write mechanism ensures data synchronization and improves write performance by utilizing the parallel characteristics of different chips or planes. The preset read strategy effectively distributes read pressure through a round-robin read mechanism, preventing read interference caused by over-reading of a single physical block and extending the lifespan of the memory device. Attached Figure Description

[0008] Figure 1 This is a block diagram of a host system and storage device according to embodiments of the present disclosure;

[0009] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure;

[0010] Figure 3 This is a schematic diagram of a virtual block structure according to an embodiment of the present disclosure;

[0011] Figure 4 This is a schematic diagram of cross-chip enhancement block pairing according to an embodiment of the present disclosure;

[0012] Figure 5 This is a schematic diagram of cross-chip, cross-plane enhancement block pairing according to an embodiment of the present disclosure;

[0013] Figure 6 This is a schematic diagram of the pairing of the same chip enhancement blocks according to an embodiment of the present disclosure;

[0014] Figure 7 This is a schematic diagram of a round-robin reading strategy flow according to an embodiment of the present disclosure;

[0015] Figure 8This is a schematic diagram of an enhanced block mapping table and corresponding access operations according to an embodiment of the present disclosure. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0017] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0018] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0019] In this embodiment, the memory module 220 is a NAND flash memory module, including multiple virtual blocks, each virtual block having multiple physical blocks belonging to multiple planes of multiple chips. As the flash memory module is used for a longer period of time, the number of erase cycles of the physical blocks gradually increases. When a certain threshold is reached, the error rate will rise, affecting data reliability. The memory management method proposed in this disclosure provides additional data protection for virtual blocks with poor health through dynamic enhanced block mapping technology, thereby extending the lifespan of the storage device.

[0020] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0021] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0022] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0023] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0024] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0025] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10.

[0026] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program code, and these control instructions / program code are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, the processor 211 is configured to execute the memory management methods provided in this disclosure.

[0027] In other embodiments, the control instructions / program code corresponding to the data reading method can be implemented as hardware circuit units to implement the memory management method provided in this disclosure.

[0028] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0029] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0030] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213 (e.g., performing corresponding write operations according to various write instructions from the host system 10). As another example, it performs a read operation according to read instructions from the host system 10, reads data from one or more physical units of the memory module 220 (data can be read from one or more storage units in one or more physical units) via the memory interface control circuit 213, and writes the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230. In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0031] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform write (also known as programming), read, or erase operations on the memory module 220.

[0032] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0033] In addition, the memory controller 210 establishes a mapping table to record the mapping information between logical addresses and physical addresses. In traditional memory management, the memory controller typically establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table. These are used to find the physical units (e.g., physical erase units / physical blocks, physical pages) mapped to logical units (e.g., physical erase units / physical blocks, physical pages), and to find the logical units mapped to physical units, respectively. Furthermore, the physical-to-logical address mapping table can also be used to quickly determine valid and invalid data in a specific physical block.

[0034] In this disclosure, the memory controller 210 further establishes an enhancement block mapping table to record the mapping relationship between each enhancement block and the first and second entity blocks paired with the enhancement block. Simultaneously, a logic-to-entity mapping table records the mapping relationship between host logical addresses and corresponding enhancement block identifiers. Furthermore, in one embodiment, the enhancement block mapping table may also record a priority read identifier corresponding to each enhancement block, which indicates whether the first entity block or the second entity block is the target entity block selected for priority reading among the target enhancement blocks.

[0035] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data for managing the storage device 20.

[0036] In this embodiment, the buffer memory 214 is configured to provide the necessary cache resources and system data (e.g., logic-to-entity mapping tables, entity-to-logic mapping tables, and enhancement block mapping tables, etc.) when the processor 211 executes the memory management method of this disclosure. Specifically, the processor 211 is configured to execute the memory management method of this disclosure, including acquiring multiple virtual blocks of the memory module 220 and error bit statistics for each virtual block, evaluating the health status of each virtual block based on the error bit statistics, and selecting a target virtual block with poor health status to perform enhancement block mapping operations. The processor 211 is also configured to maintain the enhancement block mapping table, record the mapping relationship between enhancement blocks and paired entity blocks, and implement a round-robin reading mechanism according to a preset reading strategy to prevent read interference.

[0037] The memory module 220 is electrically connected to the memory controller 210 (specifically electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0038] Specifically, memory module 220 includes multiple chips, each chip being further subdivided into multiple planes, and each plane containing multiple physical blocks. Furthermore, each physical block in memory module 220 includes multiple physical pages, and each physical page contains multiple memory cells. It should be noted that this disclosure is not limited to the size of each physical page and logical page.

[0039] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure.

[0040] Reference Figure 2 In one embodiment, the memory management method provided in this disclosure includes the following main process steps:

[0041] First, in step S210, the processor 211 acquires multiple virtual blocks of the memory module 220 and corresponding error bit statistics for each virtual block. Each virtual block has multiple physical blocks belonging to multiple planes of multiple chips. Specifically, the processor 211 periodically collects error bit statistics for each virtual block within a preset time period. The error bit statistics may include, but are not limited to, indicators such as the number of Error Correction Code (ECC) corrections, the frequency of bit-flips, the number of read failures, and the number of erase failures. The processor 211 may temporarily store this statistical information in a buffer memory 214 for subsequent health status assessment.

[0042] Figure 3 This is a schematic diagram of a virtual block structure according to an embodiment of the present disclosure.

[0043] Reference Figure 3 For example, in one embodiment, the memory module 220 includes multiple chips, such as... Figure 3 The memory module 220 contains a first chip D1 and a second chip D2. Each chip is further subdivided into multiple planes, where the first chip D1 includes a first plane PL1 and a second plane PL2, and the second chip D2 also includes a first plane PL1 and a second plane PL2. The memory module 220 organizes and manages its multiple physical blocks in a virtual block manner. Each virtual block spans the corresponding planes of multiple chips, forming a unified logical management unit.

[0044] Specifically, the processor 211 can group multiple virtual blocks according to the order of the physical blocks in each plane. For example, the first virtual block VB1 includes the first physical block BK1 located in the first plane PL1 of the first chip D1, the first physical block BK1 located in the second plane PL2 of the first chip D1, the first physical block BK1 located in the first plane PL1 of the second chip D2, and the first physical block BK1 located in the second plane PL2 of the second chip D2. Similarly, the second virtual block VB2 includes the second physical block BK2 located in the two planes of the two chips, and the Nth virtual block VBN includes the Nth physical block BKN located in the two planes of the two chips. Through this cross-chip, cross-plane virtual block structure design, each virtual block has multiple physical blocks belonging to multiple planes of multiple chips, providing a flexible pairing selection space for subsequent enhancement block mapping operations.

[0045] When processor 211 performs enhanced block mapping operations on the target virtual block, the virtual block structure provides a variety of possible combinations for pairing physical blocks. Processor 211 can select two physical blocks belonging to different chips within the target virtual block for pairing, for example, pairing a physical block in the first plane PL1 of the first chip D1 with a physical block in the first plane PL1 of the second chip D2. This cross-chip pairing method can fully utilize the parallel processing capabilities between different chips, achieving better performance when performing parallel write or read operations.

[0046] In another embodiment, the processor 211 may also select two physical blocks belonging to different planes within the target virtual block for pairing, for example, pairing a physical block in the first plane PL1 of the first chip D1 with a physical block in the second plane PL2 of the same chip. Although the parallel capability of this pairing method is slightly limited compared to cross-chip pairing, it can still disperse the failure risk of a single plane to a certain extent, making it suitable for resource-constrained application scenarios.

[0047] In one embodiment, the processor 211 may also select two physical blocks belonging to different chips and different planes within the target virtual block for pairing, for example, pairing a physical block in the first plane PL1 of the first chip D1 with a physical block in the second plane PL2 of the second chip D2. This pairing strategy, which maximizes separation, can simultaneously achieve fault domain separation at the chip level and the plane level, providing the highest level of data protection capabilities.

[0048] The virtual block structure design also facilitates dynamic resource scheduling. When the processor 211 selects a target virtual block based on the health status assessment results, it can fully consider the wear distribution of each chip and plane, prioritizing the selection of virtual blocks containing physical blocks with poor health status for enhanced protection. Furthermore, the cross-chip and cross-plane characteristics of the virtual blocks ensure that the enhanced block mapping operation does not overload a single chip or plane. When the processor 211 writes target data in parallel to the paired first and second physical blocks, since these two physical blocks belong to different chips or planes, the write operations can be performed simultaneously, effectively reducing the impact on overall write performance. Similarly, when executing a round-robin read strategy, the switching between different chips or planes can better distribute read pressure, preventing read interference caused by over-reading in a single area.

[0049] It is worth noting that this disclosure is not limited to grouping multiple virtual blocks according to the order of physical blocks on each plane. For example, in another embodiment, the processor 211 may dynamically reorganize the composition of virtual blocks based on the health status, wear level, or performance characteristics of the physical blocks. Specifically, the processor 211 may classify physical blocks with similar health scores into the same virtual block, or mix and distribute physical blocks with different wear levels to achieve a more balanced load distribution.

[0050] In one embodiment, the processor 211 can also adjust the composition strategy of virtual blocks according to the data access pattern. For frequently accessed hot data areas, the processor 211 can preferentially select physical blocks with better performance to form the corresponding virtual blocks; for infrequently accessed cold data areas, relatively aged physical blocks that can still function normally can be used. In addition, the processor 211 can also implement a time-based reorganization strategy, periodically evaluate the state changes of each physical block, and dynamically adjust the internal composition of the virtual blocks to ensure the best performance of the overall storage system.

[0051] Back Figure 2 Next, processor 211 executes step S220, evaluating the health status of each virtual block based on error bit statistics. In one embodiment, processor 211 calculates a health score for each virtual block by analyzing the number of errors and the number of error bits in the error bit statistics. Specifically, processor 211 counts the number of errors and the number of error bits occurring in each virtual block within a preset time period, and obtains a health score for each virtual block based on the number of errors and the number of error bits. In one embodiment, processor 211 may use a weighted average algorithm to assign different weight coefficients to different types of error indicators, comprehensively calculating a numerical score reflecting the overall health status of the virtual block. The lower the health score, the worse the health status of the corresponding virtual block.

[0052] Next, processor 211 executes step S230, selecting one or more target virtual blocks from the plurality of virtual blocks based on the health status of each virtual block, wherein the health status of the one or more target virtual blocks is lower than that of the other virtual blocks. Processor 211 can obtain the one or more target virtual blocks by comparing the health score of each virtual block with a health score threshold. In another embodiment, processor 211 sorts the plurality of virtual blocks from low to high according to the health score and selects the top P virtual blocks as the one or more target virtual blocks, where P is a preset number of target virtual blocks. It is worth mentioning that, in one embodiment, processor 211 can also dynamically adjust the number of target virtual blocks selected based on the current available capacity of storage device 20, balancing the utilization efficiency of storage capacity while ensuring data security. For example, the higher the current available capacity, the higher the value of P can be set.

[0053] It should be noted that, in one embodiment, the processor 211 may also monitor the average number of erases of the memory module 220. Only when the average number of erases reaches a preset erase count threshold will the processor 211 begin selecting one or more target virtual blocks to perform the enhanced block mapping operation. In other words, the processor 211 only begins performing the enhanced block mapping operation when the memory module 220 has aged to a certain extent, in order to prevent data errors.

[0054] Next, in step S240, the processor 211 performs an enhancement block mapping operation on each target virtual block, pairing multiple entity blocks within the target virtual block into pairs, mapping each pair of paired entity blocks to an enhancement block, wherein the effective storage capacity of each enhancement block is equal to the storage capacity of a single entity block. During pairing, the processor 211 can select two entity blocks within the target virtual block belonging to different chips, or two entity blocks within the target virtual block belonging to different planes, or two entity blocks within the target virtual block belonging to both different chips and different planes.

[0055] In one embodiment, the processor 211 preferentially selects a cross-chip pairing scheme because the parallel write and read capabilities between different chips are generally better than the parallel capabilities between different planes, thereby achieving better performance. Simultaneously, the processor 211 establishes an enhancement block mapping table, recording the mapping relationship between each enhancement block and the first and second entity blocks paired with the enhancement block.

[0056] Figure 4 This is a schematic diagram of cross-chip enhancement block pairing according to an embodiment of the present disclosure.

[0057] Reference Figure 4For example, as shown by arrow A41, processor 211 selects physical block BK1 in the first plane PL1 of the first chip D1 as the first physical block. It also selects physical block BK1 in the first plane PL1 of the second chip D2 as the second physical block, pairing these two physical blocks belonging to different chips. Through this cross-chip pairing method, processor 211 maps the two paired physical blocks into an enhancement block, which in... Figure 4 The first enhancement block is represented by EBK1.

[0058] Similarly, processor 211 can perform the same pairing operation on other physical blocks within virtual block VB1. As shown in another pairing example by arrow A42, processor 211 selects physical block BK1 in the second plane PL2 of the first chip D1 as the first physical block and selects physical block BK1 in the second plane PL2 of the second chip D2 as the second physical block to pair them and form a second enhancement block EBK2.

[0059] When establishing the enhancement block mapping table, the processor 211 records in detail the mapping relationship between each enhancement block and its corresponding paired entity block. Specifically, the enhancement block mapping table contains the identification information of the first enhancement block EBK1, the physical address of its corresponding first entity block located on the first plane PL1 of the first chip D1, and the physical address of its second entity block located on the first plane PL1 of the second chip D2. Similarly, the mapping record of the second enhancement block EBK2 contains the physical addresses of its paired entity blocks located on the second plane PL2 of the first chip D1 and the second plane PL2 of the second chip D2, respectively.

[0060] When processor 211 performs write operations on enhancement blocks, the cross-chip pairing design plays a crucial role. Taking the first enhancement block EBK1 as an example, processor 211 can simultaneously send write commands to the first plane PL1 of the first chip D1 and the first plane PL1 of the second chip D2. Since the two target locations belong to different chips, the write operations can be executed in true parallel, avoiding resource contention and thus maintaining good write performance. Similarly, the write operation of the second enhancement block EBK2 can be performed simultaneously on the second plane PL2 of the first chip D1 and the second plane PL2 of the second chip D2, fully utilizing the parallel processing capabilities between different chips.

[0061] This pairing strategy also provides performance advantages during read operations. According to the preset read strategy's turn-around mechanism, the processor 211 can alternately select the read source between the two paired physical blocks of the first enhancement block EBK1. Since the first physical block is located on the first chip D1 and the second physical block is located on the second chip D2, the switching of read operations will not cause resource conflicts within the chip, while effectively distributing read pressure and preventing read interference caused by excessive reading on a single chip, thereby extending the lifespan of each physical block.

[0062] also, Figure 4 The cross-chip pairing scheme illustrated provides robust support for fault recovery. When any physical block in the first enhancement block EBK1 fails, the impact of the fault is effectively isolated within a single chip because the paired physical block is located on a completely different chip, preventing it from affecting the paired physical block. The processor 211 can immediately recover complete data from the corresponding physical block in the normally functioning chip, ensuring the continuity and reliability of data access. This chip-level fault domain separation design is particularly suitable for applications with high data security requirements.

[0063] It is worth noting that the cross-chip pairing method also exhibits unique advantages when performing garbage collection operations. When the processor 211 needs to release an enhancement block to increase available storage capacity, it can independently process paired entity blocks located on different chips, avoiding the performance bottleneck caused by multiple entity blocks within the same chip being garbage collected simultaneously.

[0064] Figure 5 This is a schematic diagram of cross-chip, cross-plane enhancement block pairing according to an embodiment of the present disclosure.

[0065] Reference Figure 5 In another embodiment, processor 211 employs a cross-chip, cross-plane pairing strategy to perform enhancement block mapping operations. As shown by arrow A51, processor 211 selects entity block BK1 in the first plane PL1 of the first chip D1 as the first entity block and selects entity block BK1 in the second plane PL2 of the second chip D2 as the second entity block, pairing these two entity blocks belonging to different chips and different planes to form the first enhancement block EBK1. Similarly, as shown by arrow A52, processor 211 selects entity block BK1 in the second plane PL2 of the first chip D1 as the first entity block and selects entity block BK1 in the first plane PL1 of the second chip D2 as the second entity block, pairing them to form the second enhancement block EBK2.

[0066] This cross-chip, cross-plane pairing method achieves maximum fault domain separation. When establishing the enhancement block mapping table, the processor 211 records in detail the pairing relationship of the first enhancement block EBK1, where its first physical block is located at the physical address of the first plane PL1 of the first chip D1, and its second physical block is located at the physical address of the second plane PL2 of the second chip D2. Similarly, the mapping record of the second enhancement block EBK2 includes the physical address of its first physical block located at the physical address of the second plane PL2 of the first chip D1, and the physical address of its second physical block located at the physical address of the first plane PL1 of the second chip D2.

[0067] The cross-chip, cross-plane pairing strategy exhibits superior performance in parallel processing. When processor 211 performs a write operation on the first enhancement block EBK1, it can simultaneously send write commands to the first plane PL1 of the first chip D1 and the second plane PL2 of the second chip D2. Since the target locations belong to different planes of different chips, the two write operations can be executed completely in parallel without any hardware resource contention, thus achieving optimal write performance.

[0068] In terms of fault tolerance, cross-chip, cross-plane pairing provides the highest level of data protection. When any physical block in the first enhancement block EBK1 fails, whether it is a chip-level or plane-level failure, the paired physical block is located in a completely independent hardware domain, ensuring complete data recovery. For example, even if the first plane PL1 of the first chip D1 fails, the processor 211 can still fully recover all the data of the first enhancement block EBK1 from the second plane PL2 of the second chip D2.

[0069] During the execution of the read operation's round-robin strategy, cross-chip and cross-plane pairing also plays a crucial role. The processor 211 can switch between different planes of different chips to distribute the read load to the greatest extent possible. Taking the first enhancement block EBK1 as an example, when the processor 211 has read from the first plane PL1 of the first chip D1 to a preset threshold number of times, it can switch to the second plane PL2 of the second chip D2 to continue reading.

[0070] Furthermore, cross-chip, cross-plane pairing exhibits unique advantages in garbage collection operations. When the processor 211 needs to release enhancement blocks to reclaim storage space, it can process paired entity blocks located on different chips and different planes completely independently, avoiding performance interference that may be caused by multiple operations within the same hardware domain. This design enables the storage system to maintain stable performance when performing capacity management operations, ensuring that user data access is not affected.

[0071] The cross-chip, cross-plane pairing method represents the highest level of data protection strategy in this disclosure. By simultaneously achieving fault isolation at the chip and plane levels, it provides the most reliable security guarantee for critical data and is particularly suitable for application environments with extremely high requirements for data integrity and system reliability.

[0072] It is worth mentioning that, in one embodiment, the processor 211 can also utilize cross-chip, cross-plane paired parallel read capabilities to improve data access speed. Specifically, when the host system 10 requests to read a large amount of target data, the processor 211 can divide the target data into a first part and a second part, and simultaneously read from the first physical block and the second physical block of the first enhancement block EBK1 in parallel. The processor 211 reads the first part of the target data in the first physical block EBK1 of the first plane PL1 of the first chip D1, while simultaneously reading the second part of the target data in the second physical block EBK2 of the second plane PL2 of the second chip D2. Since the two read operations are executed on different planes of different chips, there is no hardware resource conflict, thus truly achieving parallel processing and reducing the read time to nearly half the read time of a single physical block, thereby significantly accelerating the overall data read speed. This parallel read mechanism is particularly suitable for applications involving large-capacity file transfers or high-frequency data access.

[0073] Figure 6 This is a schematic diagram of the pairing of the same chip enhancement blocks according to an embodiment of the present disclosure.

[0074] Reference Figure 6 In another embodiment, when the target virtual block VB1 is located on a single chip D1 containing four planes, the processor 211 can employ various pairing strategies across planes within the same chip to perform enhancement block mapping operations. As shown by arrow A61, the processor 211 selects entity block BK1 in the first plane PL1 of the first chip D1 as the first entity block and selects entity block BK1 in the second plane PL2 within the same chip as the second entity block for pairing, forming the first enhancement block EBK1. Similarly, as shown by arrow A62, the processor 211 selects entity block BK1 in the third plane PL3 of the first chip D1 as the first entity block and selects entity block BK1 in the fourth plane PL4 as the second entity block for pairing, forming the second enhancement block EBK2. This pairing method fully utilizes the resource configuration of multiple planes within a single chip, providing plane-level fault tolerance for the target virtual block.

[0075] For example, in one embodiment, when the first chip D1 contains only two planes, the processor 211 adopts a corresponding dual-plane pairing strategy. Specifically, the processor 211 selects physical block BK1 in the first plane PL1 of the first chip D1 as the first physical block and selects physical block BK1 in the second plane PL2 of the first chip D1 as the second physical block for pairing, forming corresponding enhancement blocks. This dual-plane pairing method also utilizes the planar parallelism capability within the chip. When the processor 211 performs a write operation, it can simultaneously send write commands to the first plane PL1 and the second plane PL2, realizing parallel writing between planes. During read operations, the processor 211 switches between the two planes in turn according to a preset read strategy, effectively distributing read pressure and extending the lifespan of the physical blocks. Although the parallelism and fault tolerance of dual-plane pairing are limited compared to cross-chip pairing, it can still provide basic planar-level protection for data and is suitable for storage device configurations with dual-plane chip architectures.

[0076] In a preferred embodiment, when performing pairing mapping of enhanced blocks, the processor 211 preferentially selects physical blocks located on different chips for pairing, and secondly selects physical blocks located on the same chip but on different planes for pairing. When there are no free physical blocks available for cross-chip pairing within the target virtual block, the processor 211 will instead select physical blocks across planes for pairing, thereby improving parallel read / write performance and enhancing fault tolerance while ensuring data reliability.

[0077] Back Figure 2 Next, the processor 211 executes step S250, whereby, when writing target data to the target enhancement block, the target data is written in parallel to the first entity block and the second entity block of the target enhancement block. Specifically, the processor 211 assigns a corresponding target enhancement block identifier to the target enhancement block, obtains the first entity address of the first entity block and the second entity address of the second entity block corresponding to the target enhancement block identifier through the enhancement block mapping table, writes the target data to both the first entity address and the second entity address simultaneously, and records the mapping relationship between the host logical address of the target data and the target enhancement block identifier in the logical-to-entity mapping table. Since the two paired entity blocks belong to different chips or planes, this parallel write operation can effectively utilize the parallel processing capability of the memory module 220 and reduce the impact on the overall write performance.

[0078] In step S260, when reading the target data from the target enhancement block, the processor 211 selects either the first entity block or the second entity block to read the target data according to a preset reading strategy.

[0079] In one embodiment, the processor 211 looks up the target enhancement block identifier corresponding to the host logical address according to the logic-to-entity mapping table, determines the target entity address as the first entity address or the second entity address through the enhancement block mapping table and the preset reading strategy corresponding to the target enhancement block identifier, and reads the target data from the target entity address.

[0080] Specifically, the preset reading strategy employs a round-robin reading mechanism. The processor 211 acquires a priority reading flag, which indicates whether the first entity block or the second entity block is preferentially selected for reading from the target enhancement blocks. When the priority reading flag is a first value, the processor 211 determines the first entity block as the target reading entity block and prioritizes reading the target data from the first entity block. When the priority reading flag is a second value, the processor 211 determines the second entity block as the target reading entity block and prioritizes reading the target data from the second entity block. After completing this reading operation, the processor 211 updates the number of reads corresponding to the target reading entity block.

[0081] In one embodiment, when the number of reads reaches a read count threshold, the read count for the corresponding target read entity block is reset, and the priority read identifier is changed, either from the first entity block originally indicated to the second entity block, or from the second entity block originally indicated to the first entity block. In simpler terms, the processor 211 switches the entity block that is read preferentially.

[0082] It is worth mentioning that, in one embodiment, when reading the target data from the first entity block or the second entity block of the target enhancement block fails, the processor 211 can directly read the same target data from another entity block in the target enhancement block, thereby providing immediate fault recovery capability.

[0083] It should be noted that since the enhanced block mapping operation actually utilizes twice the storage space to ensure the security of the stored data, the actual available space of the storage device 20 will be consumed more quickly.

[0084] In one embodiment, the processor 211 can calculate the temporary storage capacity value after applying the enhancement block mapping operation and monitor the occupancy ratio of the effective user data volume relative to the temporary storage capacity value. When the occupancy ratio reaches an occupancy ratio threshold, the processor 211 releases some enhancement blocks through a garbage collection operation to increase the temporary storage capacity value, thereby reducing the occupancy ratio.

[0085] Specifically, the temporary storage capacity value refers to the effective capacity of the storage device 20 that can actually be used for user data storage after performing enhanced block mapping operations on a portion of the virtual blocks. Because the enhanced block mapping operation uses a dual-physical-block mirroring backup mechanism, the effective storage capacity of each enhanced block is equal to the storage capacity of a single physical block. Compared to the original single-physical-block storage method, the actual usable storage space is reduced by half. Therefore, the processor 211 needs to recalculate the actual usable capacity after enhanced block mapping.

[0086] The processor 211 calculates the temporary storage capacity value as follows: the temporary storage capacity value equals the number of virtual blocks that have not undergone enhanced block mapping operations multiplied by the original capacity of a single virtual block, plus the number of target virtual blocks that have undergone enhanced block mapping operations multiplied by the original capacity of a single virtual block divided by two. Through this calculation method, the processor 211 can accurately determine the impact of enhanced block mapping operations on the overall storage capacity. The original capacity of a single virtual block is the pre-defined total storage space of all physical blocks possessed by that single virtual block.

[0087] For example, suppose storage device 20 is originally rated to have a capacity of 512MB multiplied by 100 virtual blocks (each virtual block being 512MB), totaling 51200MB. When processor 211 performs enhanced block mapping on 40 of the lower-quality virtual blocks based on a health assessment, the effective data volume of these 40 target virtual blocks is halved due to the dual physical block mirroring backup mechanism used within these 40 virtual blocks; that is, each virtual block is 256MB. Therefore, the temporary storage capacity calculated by processor 211 is 512MB multiplied by 60 virtual blocks that did not undergo enhanced block mapping, plus 256MB multiplied by 40 virtual blocks that underwent enhanced block mapping, totaling 40960MB.

[0088] When the ratio between the amount of valid user data and the temporary storage capacity in storage device 20 reaches the occupancy ratio threshold (e.g., 90% or other preset ratio), processor 211 prioritizes the storage capacity requirement and gradually releases some enhancement blocks through garbage collection operations.

[0089] In one embodiment, when releasing a portion of the enhanced blocks, the processor 211 evaluates the health status of each target virtual block. Based on the health status, it preferentially selects virtual blocks with relatively good health status as candidate virtual blocks to ensure that the restored physical blocks can operate stably in normal storage mode. The processor 211 preferentially selects virtual blocks with relatively high health scores and low error rates for enhanced block release operations (e.g., selecting the top M virtual blocks with the highest health scores for enhanced block release operations), because the physical blocks within these virtual blocks can still maintain good data integrity and read / write performance after being restored as independent storage units, making them suitable for continuing to undertake single-mode storage tasks. This selection strategy ensures that the capacity release process does not introduce additional reliability risks, while retaining the necessary mirror backup mechanism for virtual blocks with truly poor health status that still require enhanced protection.

[0090] Next, by performing the garbage collection operation on the candidate virtual blocks, multiple candidate enhancement blocks of the candidate virtual blocks are released, restoring each candidate enhancement block to two independent and empty entity blocks. This increases the available storage capacity, resulting in a lower ratio between the amount of valid user data and the temporary storage capacity, ensuring sufficient storage space for the user and thus maintaining a good user experience.

[0091] In a preferred embodiment, when the proportion of valid user data occupancy reaches a preset threshold of the currently available temporary capacity, the processor 211 will initiate a garbage collection process to release space. This process includes: generating a candidate release list based on the health score of each virtual block, ranked from highest to lowest; the processor 211 sequentially processes the candidate enhancement blocks, restoring them to two independent and unused physical blocks, and updating the corresponding mapping table, thereby achieving rapid release and avoiding the migration of valid data to physical block regions with poor health.

[0092] Figure 7 This is a schematic diagram of a turn-reading strategy according to an embodiment of the present disclosure.

[0093] The following uses Figure 7 To illustrate the specific process of the round-robin reading strategy, refer to... Figure 7 In one embodiment, in step S710, the processor 211 obtains a read instruction, which instructs to read target data corresponding to the host logical address.

[0094] Specifically, when the host system 10 sends a read request through the connection interface circuit 230, the processor 211 parses the read instruction, obtains the host logical address, and determines the target enhancement block identifier (also known as the virtual enhancement block entity address) corresponding to the target enhancement block of the host logical address through the logic-to-entity mapping table.

[0095] Next, the processor 211 executes step S720, which reads the first entity block of the target enhancement block according to the priority read identifier corresponding to the first value of the target enhancement block to obtain the target data, and updates the first read count corresponding to the first entity block.

[0096] Specifically, processor 211 searches the enhancement block mapping table stored in buffer memory 214 to determine the specific value of the priority read flag corresponding to the target enhancement block identifier, thereby determining whether the target entity address to be read first is the first entity address of the corresponding first entity block or second is the second entity address of the corresponding second entity block. For example, when the priority read flag is a first value (e.g., 0), processor 211 determines the first entity block as the current target read entity block (the target entity address is the first entity address of the corresponding first entity block). Processor 211 sends a read instruction to the first entity block through memory interface control circuit 213, reads the target data from the specified first entity address, and transmits the read target data to host system 10. At the same time, processor 211 increments the first read count corresponding to the first entity block and records this read operation.

[0097] Next, processor 211 executes step S730, determining whether the first read count has reached a read count threshold. Processor 211 compares the currently accumulated first read count with a preset read count threshold, which can be set according to the specific configuration and performance requirements of the storage device. This determination step ensures that the alternating read mechanism can switch at appropriate times, preventing read interference caused by excessive reading of a single physical block.

[0098] If the determination result of step S730 is negative, processor 211 executes step S740 without changing the priority read flag. At this time, the first entity block remains the priority read entity block, and subsequent read operations will continue to be performed from the first entity block. Processor 211 maintains the current read configuration to ensure the continuity and stability of the read operation.

[0099] When the determination result of step S730 is yes, processor 211 executes step S750, resetting the first read count (to prepare for the next read cycle) and changing the priority read flag to a second value (e.g., 1). Since processor 211 changes the priority read flag from the first value to the second value, subsequent read operations will switch to the second physical block. This switching mechanism enables alternating reading between the two paired physical blocks, effectively distributing read pressure and delaying the time point when read interference occurs between the physical blocks.

[0100] In one embodiment, after the priority read flag is switched to the second value, the processor 211 will prioritize reading the target data from the second entity block in subsequent read operations and begin accumulating the number of reads of the corresponding second entity block. When the number of reads of the second entity block reaches the same read count threshold, the processor 211 performs the switching operation again, resetting the priority read flag to the first value, forming a continuous alternating read loop.

[0101] This round-robin read strategy is designed with full consideration of the physical characteristics of NAND flash memory devices. By periodically switching the read source, the processor 211 can avoid a single physical block from experiencing excessive read operations, thereby delaying read interference. Simultaneously, since the paired physical blocks store the same target data, switching the read source does not affect data integrity and accuracy, ensuring the reliability of user data access. This dynamic load balancing mechanism is one of the important technical means of extending the lifespan of storage devices in the memory management method of this disclosure.

[0102] Figure 8 This is a schematic diagram of an enhanced block mapping table and corresponding access operations according to an embodiment of the present disclosure.

[0103] Reference Figure 8 In one embodiment, the processor 211 establishes an enhancement block mapping table T81 to manage the mapping relationship between enhancement blocks and paired entity blocks. The enhancement block mapping table T81 contains multiple mapping records, each record describing in detail the enhancement block identifier, the corresponding first entity block entity address, the second entity block entity address, and the current priority read identifier.

[0104] For example, suppose the first enhancement block EPBA1 corresponds to the first entity block PBA11 and the second entity block PBA12, and its priority read flag is currently set to 0. The second enhancement block EPBA2 corresponds to the first entity block PBA21 and the second entity block PBA22, and its priority read flag is set to 1, and so on. This mapping table structure provides the processor 211 with complete enhancement block management information, ensuring that data access operations can accurately locate the corresponding entity block.

[0105] During the write operation, as shown by arrow A81, when processor 211 receives a write request for target data TD, it first assigns a corresponding target enhancement block identifier EPBA1 to the target enhancement block. Then, as shown by arrow A82, processor 211 obtains the first entity address PBA11 of the first entity block and the second entity address PBA12 of the second entity block corresponding to the target enhancement block identifier EPBA1 through enhancement block mapping table T81. Next, processor 211 simultaneously writes the target data TD to both the first entity address PBA11 and the second entity address PBA12, completing the parallel write operation of the mirrored data. After the data write is complete, processor 211 records the mapping relationship between the host logical address corresponding to the target data TD and the target enhancement block identifier EPBA1 in the logical-to-entity mapping table, ensuring that subsequent read operations can correctly locate the corresponding enhancement block. This write process ensures the integrity of the mirrored backup of the data and establishes a complete address mapping relationship, providing a foundation for subsequent data access operations. Because the paired entity blocks belong to different chips or planes, the write operation can be executed in true parallel, maintaining good write performance.

[0106] During the read operation, processor 211 employs a round-robin strategy based on priority read flags to select the read source. As shown by arrow A83, when processor 211 receives a read request, it first looks up the target enhanced block identifier EPBA1 corresponding to the host logical address according to the logical-to-entity mapping table. Subsequently, processor 211 checks the priority read flag of the corresponding target enhanced block identifier EPBA1 through enhanced block mapping table T81. Since the priority read flag of the first enhanced block identifier EPBA1 is currently 0, processor 211 determines the first entity address PBA11 as the target entity address. As shown by arrow A84, processor 211 reads the target data TD from the first entity address PBA11 and increments the corresponding read count. When the accumulated read count reaches a preset threshold, processor 211 changes the priority read flag to 1, causing subsequent read operations to switch to the second entity address PBA12, thereby realizing the round-robin read mechanism between paired entity blocks.

[0107] The enhanced block mapping table T81 is designed to support dynamic read strategy adjustments. The processor 211 can flexibly adjust the switching frequency and strategy of priority read identifiers based on the health status, load distribution, or performance requirements of each entity block. Furthermore, the enhanced block mapping table T81 records the pairing relationships of each enhanced block. When the processor 211 needs to perform garbage collection or data migration operations, it can accurately identify the paired entity blocks that need to be processed simultaneously, ensuring the integrity and consistency of the enhanced blocks.

[0108] It is worth noting that the enhanced block mapping table T81 works in conjunction with the traditional logical-to-entity mapping table to form a complete address translation system. The logical address sent by host system 10 is first converted into an enhanced block identifier through the logical-to-entity mapping table, and then further resolved into a specific entity block address through the enhanced block mapping table T81. This two-layer mapping mechanism maintains compatibility with the existing storage management architecture while supporting the special management needs of enhanced blocks, achieving a balance between data protection and system performance.

[0109] In one embodiment, the processor 211 may also record additional metadata information in the enhanced block mapping table T81, such as the health score, write-level (WL) metric, P / E cycle, cumulative read count, and last access time for each entity block. This extended information helps the processor 211 make more granular storage management decisions, including more complex management functions such as dynamically adjusting read strategies, predictive maintenance, and intelligent capacity management.

[0110] In one embodiment, the processor 211 can also implement a threshold-based automatic read voltage optimization technique during the read-by-read switching process. Specifically, whenever the cumulative number of reads reaches a preset threshold and triggers a target read block switch (also known as a read source switch operation), the processor 211 not only changes the priority read flag, but also automatically checks and fine-tunes the read reference voltage setting of the block based on the health index, cumulative erase count, or recent error correction code correction statistics of the block that has just completed a read cycle. The processor 211 can combine a read retry mechanism or an aging characteristic lookup table to dynamically adjust the voltage level and optimization strategy to ensure that the reliability of the read operation is compensated accordingly as the physical block ages. This preset value and adjustment strategy can be personalized according to the storage chip type and cumulative wear status to achieve fine-grained read performance optimization management.

[0111] In another embodiment, the processor 211 implements an integrated mechanism of threshold-based round-robin allocation and health checks, transforming the round-robin switching into a trigger point for proactive health monitoring. Whenever the cumulative number of reads reaches a preset threshold, the processor 211 not only performs a read source switching operation but also conducts a comprehensive health assessment of the physical blocks that have just undergone intensive reads, including bit flip statistics, error correction code performance analysis, and cumulative erase count checks. Based on the assessment results, the processor 211 can automatically initiate data refresh operations, optimize read voltage adjustments, and even trigger a data re-mirroring backup mechanism when health deterioration is detected. This integrated design transforms the round-robin read strategy from passive load balancing to a proactive preventative maintenance system, further extending the overall lifespan of the storage device 20 and improving data security through regular health monitoring and adaptive adjustments.

[0112] In one embodiment, the processor 211 may also maintain a cumulative read cycle count counter to record the total number of cycles for which each entity block is selected as a read source in turn. Specifically, whenever the processor 211 switches read sources due to the cumulative read count reaching a threshold, it not only resets the current read cycle count counter but also increments the cumulative read cycle count for the corresponding entity block. This cumulative cycle count counter reflects the total read pressure experienced by the entity block throughout its entire enhancement block lifecycle, providing a more comprehensive reference for assessing the health status of the entity block.

[0113] When the cumulative number of read cycles reaches a read cycle threshold, the processor 211 can trigger more aggressive data protection operations. For example, when the cumulative number of read cycles for a physical block exceeds the first read cycle threshold, the processor 211 can initiate a preventative data migration operation, migrating the data of that enhanced block to a new enhanced block with better health and re-establishing the mirror backup relationship. When the cumulative number of read cycles reaches the second read cycle threshold, the processor 211 can perform a data rewrite operation, refreshing the charge state within the physical block through a rewrite mechanism to delay the degradation of data retention capability. This multi-level cumulative cycle monitoring mechanism achieves round-robin load balancing and proactive lifetime management, providing the storage device 20 with a more aggressive data protection strategy.

[0114] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0115] Based on the above, the memory management method and memory controller provided in this disclosure achieve precise monitoring of the memory module status by acquiring error bit statistics and assessing the health status of virtual blocks. This enables timely identification of areas with poor health status and the implementation of targeted protection measures. By selecting target virtual blocks with lower health status than other virtual blocks to perform enhanced block mapping operations, this disclosure avoids impacting the performance of the entire storage system, providing additional data security guarantees only for high-risk virtual blocks (with lower health status) that require protection, thus achieving efficient resource utilization.

[0116] The design pairs entity blocks within the target virtual block and maps them to augmented blocks, establishing a complete mirror backup mechanism for each augmented block. When any entity block fails, data can be recovered from its paired entity block, improving data reliability and system fault tolerance. The pairing strategy supports various combinations across chips and planes, fully leveraging the hardware architecture advantages of the memory module to achieve fault domain separation across different chips or planes, thus enhancing the overall stability of the system.

[0117] Furthermore, the parallel write mechanism ensures the synchronization and consistency of mirrored data by simultaneously writing the same data to the paired first and second physical blocks. Since the paired physical blocks belong to different hardware resources, the write operations can be executed in true parallel, reducing write latency compared to the traditional sequential write method and maintaining good system performance.

[0118] On the other hand, the pre-defined read strategy employs a round-robin read mechanism that effectively distributes read pressure. By periodically switching read sources between paired physical blocks, it prevents read interference caused by excessive reading of a single physical block, thus extending the lifespan of the storage device. This strategy, combined with dynamic monitoring of read count thresholds, achieves balanced load distribution, ensuring the continued use of the storage device during its aging phase.

[0119] Finally, this disclosure achieves a flexible balance between data security protection and storage capacity requirements by establishing an enhanced block mapping table and a dynamic management mechanism for temporary storage capacity values. When user data volume increases, leading to capacity constraints, the system can intelligently release enhanced blocks in good health, restoring their original storage capacity and ensuring that the storage device can continuously meet user needs. This invention takes into account data reliability, access performance, and capacity flexibility, and is applicable to various application scenarios such as consumer and enterprise-level solid-state storage devices, providing a technical solution for extending the lifespan of storage devices.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method, applied to a storage device configured with a memory module, characterized in that, The method includes: Assess the health status of multiple virtual blocks in the memory module; Based on the health status of each virtual block, one or more target virtual blocks are selected from the plurality of virtual blocks, wherein the health status of the one or more target virtual blocks is lower than the health status of the other virtual blocks; An enhancement block mapping operation is performed on each target virtual block, pairing multiple entity blocks within the target virtual block into one pair, and mapping each pair of two entity blocks into one enhancement block; Establish an enhancement block mapping table to record the enhancement block identifier of each enhancement block and the mapping relationship between the first entity block and the second entity block paired with the enhancement block; The mapping relationship between the host logical address and the corresponding enhancement block identifier is recorded in the logical-to-entity mapping table; When writing target data to the target enhancement block, the target data is written in parallel to the first entity block and the second entity block of the target enhancement block; When reading the target data from the target enhancement block, according to a preset reading strategy, one of the first entity block or the second entity block is selected to read the target data; and When the target data being read is large, the target data is divided into a first part and a second part, and read in parallel from the first entity block and the second entity block of the target enhancement block.

2. The memory management method according to claim 1, characterized in that, The assessment of the health status of the plurality of virtual blocks of the memory module includes: Count the number of errors and the number of error bits that occur in each virtual block within a preset time period; and A health score for each virtual block is obtained based on the number of errors and the number of error bits.

3. The memory management method according to claim 2, characterized in that, Selecting one or more target virtual blocks from the plurality of virtual blocks based on the health status of each virtual block includes one of the following steps: The one or more target virtual blocks are obtained by comparing the health score and health score threshold of each virtual block; and The multiple virtual blocks are sorted from low to high according to the health score, and the top P virtual blocks are selected as one or more target virtual blocks, where P is the preset number of target virtual blocks.

4. The memory management method according to claim 1, characterized in that, Pairing the plurality of entity blocks within the target virtual block into pairs includes one of the following methods: Select two physical blocks belonging to different chips within the target virtual block and pair them; Select two entity blocks belonging to different planes within the target virtual block and pair them; and Select two physical blocks belonging to different chips and different planes within the target virtual block and pair them.

5. The memory management method according to claim 1, characterized in that, The method further includes: Monitor the average number of erases of the memory module; and When the average number of erases reaches a preset erase count threshold, one or more target virtual blocks are selected to perform the enhanced block mapping operation.

6. The memory management method according to claim 1, characterized in that, The method further includes: Record the number of times the target read entity block in the target enhancement block is preferentially selected for reading; When the number of reads of the target read entity block reaches a read count threshold, the target read entity block is changed from the first entity block to the second entity block, or from the second entity block to the first entity block; and Reset the read count.

7. The memory management method according to claim 1, characterized in that, According to the preset reading strategy, selecting one of the first entity block or the second entity block to read the target data includes: Obtain a priority read identifier, which indicates whether the target read entity block selected first or the second entity block is the first entity block among the target enhancement blocks; When the priority read identifier is a first value, the first entity block is determined to be the target read entity block, so that the target data is read preferentially from the first entity block; and When the priority read identifier is a second value, the second entity block is determined to be the target read entity block, so that the target data is read from the second entity block first.

8. The memory management method according to claim 1, characterized in that, The method further includes: When reading the target data from the first entity block or the second entity block of the target enhancement block fails, the same target data is read directly from another entity block in the target enhancement block.

9. The memory management method according to claim 1, characterized in that, The method further includes: Calculate the temporary storage capacity value after applying the enhanced block mapping operation; The proportion of valid user data usage relative to the temporary storage capacity value; and When the occupancy rate reaches the occupancy rate threshold, a portion of the enhancement blocks are released through garbage collection to increase the temporary storage capacity value, thereby reducing the occupancy rate.

10. The memory management method according to claim 9, characterized in that, Releasing the portion of the enhancement block through the aforementioned waste recycling operation includes: Assess the health status of each target virtual block; Based on the health status, virtual blocks with relatively better health status are preferentially selected as candidate virtual blocks; and By performing the garbage collection operation on the candidate virtual block, the candidate virtual block is released, thereby restoring each candidate enhancement block to two independent and empty entity blocks.

11. A memory controller for controlling a storage device configured with a memory module, characterized in that, The memory controller includes: A memory interface control circuit, for electrically connecting to the memory module; and The processor is electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device for electrical connection to the host system. The processor is configured to: Assess the health status of multiple virtual blocks in the memory module; Based on the health status of each virtual block, one or more target virtual blocks are selected from the plurality of virtual blocks, wherein the health status of the one or more target virtual blocks is lower than the health status of the other virtual blocks; An enhancement block mapping operation is performed on each target virtual block, pairing multiple entity blocks within the target virtual block into one pair, and mapping each pair of two entity blocks into one enhancement block; Establish an enhancement block mapping table to record the enhancement block identifier of each enhancement block and the mapping relationship between the first entity block and the second entity block paired with the enhancement block; The mapping relationship between the host logical address and the corresponding enhancement block identifier is recorded in the logical-to-entity mapping table; When writing target data to the target enhancement block, the target data is written in parallel to the first entity block and the second entity block of the target enhancement block; When reading the target data from the target enhancement block, according to a preset reading strategy, one of the first entity block or the second entity block is selected to read the target data; and When the target data being read is large, the target data is divided into a first part and a second part, and read in parallel from the first entity block and the second entity block of the target enhancement block.

12. The memory controller according to claim 11, characterized in that, The assessment of the health status of the plurality of virtual blocks of the memory module includes: Count the number of errors and the number of error bits that occur in each virtual block within a preset time period; and A health score for each virtual block is obtained based on the number of errors and the number of error bits.

13. The memory controller according to claim 12, characterized in that, Selecting one or more target virtual blocks from the plurality of virtual blocks based on the health status of each virtual block includes one of the following steps: The one or more target virtual blocks are obtained by comparing the health score and health score threshold of each virtual block; and The multiple virtual blocks are sorted from low to high according to the health score, and the top P virtual blocks are selected as one or more target virtual blocks, where P is the preset number of target virtual blocks.

14. The memory controller according to claim 11, characterized in that, The processor is also configured to pair the plurality of entity blocks within the target virtual block in one of the following ways: Select two physical blocks belonging to different chips within the target virtual block and pair them; Select two entity blocks belonging to different planes within the target virtual block and pair them; and Select two physical blocks belonging to different chips and different planes within the target virtual block and pair them.

15. The memory controller according to claim 11, characterized in that, The processor is also configured to: Monitor the average number of erases for the memory module; as well as When the average number of erases reaches a preset erase count threshold, one or more target virtual blocks are selected to perform the enhanced block mapping operation.

16. The memory controller according to claim 11, characterized in that, The processor is also configured to: Record the number of times the target read entity block in the target enhancement block is preferentially selected for reading; When the number of reads of the target read entity block reaches the read count threshold, the target read entity block is changed from the first entity block to the second entity block, or from the second entity block to the first entity block; as well as Reset the read count.

17. The memory controller according to claim 11, characterized in that, According to the preset reading strategy, selecting one of the first entity block or the second entity block to read the target data includes: Obtain a priority read identifier, which indicates whether the target read entity block selected first or the second entity block is the first entity block among the target enhancement blocks; When the priority read identifier is a first value, the first entity block is determined to be the target read entity block, so that the target data is read preferentially from the first entity block; and When the priority read identifier is a second value, the second entity block is determined to be the target read entity block, so that the target data is read from the second entity block first.

18. The memory controller according to claim 11, characterized in that, The processor is also configured to: When reading the target data from the first entity block or the second entity block of the target enhancement block fails, the same target data is read directly from another entity block in the target enhancement block.

19. The memory controller according to claim 11, characterized in that, The processor is also configured to: Calculate the temporary storage capacity value after applying the enhanced block mapping operation; The proportion of valid user data relative to the temporary storage capacity value; as well as When the occupancy rate reaches the occupancy rate threshold, a portion of the enhancement blocks are released through garbage collection to increase the temporary storage capacity value, thereby reducing the occupancy rate.

20. The memory controller according to claim 19, characterized in that, The portion of the enhancement block is released through the aforementioned garbage collection operation: Assess the health status of each target virtual block; Based on the health status, virtual blocks with relatively good health status are preferentially selected as candidate virtual blocks; as well as By performing the garbage collection operation on the candidate virtual block, the candidate virtual block is released, thereby restoring each candidate enhancement block to two independent and empty entity blocks.

Images