Method, equipment and medium for realizing PCIE to switch ATU based on FPGA

Abstract

The invention discloses a method for realizing switching of PCIE (Peripheral Component Interface Express) to ATU (Address Translation Unit) based on FPGA (Field Programmable Gate Array), which comprises the following steps: S1, defining a BAR space, and introducing a PAGE register and FPGA logic; s2, judging whether the RC controller can be directly controlled or not, and if yes, sending the DDR address to the RC controller; a PAGE value I is taken through FPGA logic, and a corresponding ATU register is set; the offset of the BAR is obtained through FPGA logic, and read-write operation is initiated; if not, skipping; s3, taking a PAGE value II and writing the PAGE value II into a PAGE register; the CPU obtains the offset of the BAR and initiates read-write operation; and S4, stopping. According to the method, the PAGE register and the FPGA logic are introduced and combined, the reading task of the CPU on the corresponding DDR is completed through the PCIE interconnection bus, time delay can be ignored, the DDR is accessed through the PCIE bus, no performance loss exists, software control does not need to be additionally arranged, and operation links are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of switching chips, and in particular to a method, device and medium for implementing PCIE switching ATU based on FPGA. Background Art

[0002] Nowadays, the DDR, or double data rate synchronous dynamic random access memory, in computer systems is becoming larger and larger; although the PCIE BAR, the base address register connected by the PCIE bus, is also increasing in size, many CPUs currently only support smaller BAR base address register space sizes, such as 256M.

[0003] Currently, the CPU only supports a small BAR base address register space, which is addressed by the PCIe ATU switching function. ATU stands for Address Translation Unit. By continuously switching the ATU window, the PCIe BAR is mapped to different DDR address spaces, thereby achieving access to the entire DDR space attached to the PCIe. The operation method is usually that the software obtains the DDR address to be accessed, calculates the window to switch to, sets the ATU register accordingly, and then reads and writes data.

[0004] Among them, the principle of accessing memory through the ATU function is as follows: First, the RC side, that is, the control side of PCIE, needs to configure outbound, and the device side needs inbound. For example, 0x5b000000 is inbound to BAR2, so that a mapping from BAR2 at 0x20100000 on the RC side to 0x5b000000 on the device side is established; if the content of the memory at 0x5b000000 is changed on the device side, the corresponding change can be seen at 0x20100000 on the RC side. Reading / writing 0x20100000 from the RC side and reading / writing 0x5b000000 from the device side have the same results.

[0005] However, these measures currently adopted have at least the following two problems: 1) Adding software control and switching the ATU through multiple steps will undoubtedly increase latency and reduce performance; 2) When adding a software-switched ATU, atomic operations and corresponding lock control procedures need to be performed, which will also reduce the performance of the entire system and increase the possibility of bugs. Summary of the Invention

[0006] In response to the above two problems, the purpose of the present invention is to propose a method, device, and medium for implementing PCIE switching ATU based on FPGA. The FPGA itself is used to implement ATU switching. By introducing a PAGE register and FPGA logic for calculating the PAGE value, and combining two situations of whether the RC controller can be directly controlled, the CPU's reading task of the corresponding DDR is completed in a classified manner using the PCIE interconnect bus. The delay is negligible, and there is no performance loss when accessing the DDR using the PCIE bus. No additional software control is required, the operation links are reduced, and performance is further guaranteed.

[0007] This is achieved through the following technical solutions: First, a method for implementing PCIE switching ATU based on FPGA is proposed, which includes the following steps: S1. Define the PCIE BAR space as 256M and the address width as 28 bits. Introduce the PAGE register and FPGA logic for calculating the PAGE value into the PCIE controller. S2. Determine whether the FPGA can directly control the PCIE RC controller. If so, use the CPU to send the DDR address to be accessed to the RC controller. In the RC controller, use the FPGA logic in step S1 to obtain bits 28 to 35 of the address as the page value I and set the PCIE ATU register based on the page value I. In the RC controller, continue to use the FPGA logic in step S1 to obtain bits 0 to 27 of the address as the offset in the BAR base address register to initiate a read and write operation. If not, jump to step S3. S3. Use the CPU to get bits 28 to 35 of the address as PAGE value II and write it into the PAGE register. In the PCIE RC controller, set the PCIE ATU register according to PAGE value II. Continue to use the FPGA logic in step S1 to get the ATU register. The CPU then gets bits 0 to 27 of the address as the offset in the BAR base address register to initiate a read and write operation. S4. After completing the read and write operations in step S2 or step S3, stop running.

[0008] Preferably, when any PAGE value is not in the range of 28 to 35 bits, an interrupt operation is triggered and the CPU is notified.

[0009] Secondly, a device is also proposed, including a memory and a processor, wherein the memory is used to store a program, and the processor is configured to implement the above-mentioned method for implementing PCIE switching ATU based on FPGA when executing the program.

[0010] Preferably, the processor includes at least a CPU, a PCIE interconnect bus 1, a PCIE control transmission unit, built-in logic, a PCIE interconnect bus II and a DDR memory subsystem. The CPU is connected to the PAGE register and the BAR base address register in the PCIE control transmission unit through the PCIE interconnect bus I. The built-in logic controls the ATU register through the PAGE register. The ATU register is connected to the DDR memory subsystem through the PCIE interconnect bus II. The DDR memory subsystem includes multiple DDRs.

[0011] Preferably, the PCIE control transmission unit is further provided with an interrupt controller for triggering an interrupt operation and notifying the CPU.

[0012] In addition, a storage medium is also proposed. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the above-mentioned method for implementing PCIE switching ATU based on FPGA.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention uses the FPGA itself to implement ATU switching. By introducing a PAGE register and FPGA logic for calculating the PAGE value, and combining two situations of whether the RC controller can be directly controlled, the CPU's reading task of the corresponding DDR is completed in a classified manner via the PCIE interconnect bus. The delay is negligible, and there is no performance loss when accessing the DDR via the PCIE bus. No additional software control is required, the operation links are reduced, and performance is further guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a flow chart of a method for implementing PCIE switching ATU based on FPGA; Figure 2 The following is a schematic diagram of the architecture of PCIE switching ATU based on FPGA. DETAILED DESCRIPTION

[0015] The following is a combination of the embodiments of the present invention Figure 1 and 2 , the technical solutions in the embodiments of the present invention are described in detail.

[0016] like Figure 1 The figure shows a flowchart of a method for implementing PCIE ATU switching based on FPGA. By introducing PAGE registers and corresponding FPGA logic into the FPGA and controlling ATU switching in the PCIE control transmission unit, the operation process can be effectively simplified and the FPGA performance can be guaranteed without the need for external software control. The specific steps include the following: S1. Define the BAR space of the PCIE transmission control unit as 256M and the address width as 28 bits. Introduce the PAGE register and the FPGA logic for calculating the PAGE value into the PCIE controller.

[0017] S2. Determine whether the FPGA can directly control the PCIE RC controller. If so, the CPU sends the DDR address to be accessed to the RC controller. The RC in the RC controller stands for Root Complex, which controls the PCIE transmission control unit and the PCIE interconnect bus connecting the CPU and storage-related devices.

[0018] Then, in the RC controller, use the FPGA logic in step S1 to get the 28-35 bits of the address as the PAGE value I and set the PCIE ATU register according to the PAGE value I; in the RC controller, continue to use the FPGA logic in step S1 to get the 0-27 bits of the address as the offset in the BAR base address register to initiate read and write operations; if not, jump to step S3.

[0019] In actual FPGAs, there are many types of models involved. Sometimes, the user may design and develop the device themselves, which can fully control the FPGA. But sometimes, the device may be purchased from outside. In this case, it is not necessarily possible to fully know the parameters of the entire FPGA and every detail of the control. In this case, it is necessary to divide it into two situations and deal with them accordingly.

[0020] In step S3, the CPU uses bits 28 to 35 of the address as page value II and writes it into the page register. The PCIE RC controller sets the PCIE ATU register based on page value II, and the FPGA logic in step S1 continues to access the ATU register. The CPU then uses bits 0 to 27 of the address as the offset in the base address register (BAR) to initiate a read / write operation. This offset is used to locate the specific physical location within the DDR memory subsystem, thereby determining which DDR memory is being read or written.

[0021] S4. After completing the read and write operations in step S2 or step S3, stop running.

[0022] In this embodiment, when any PAGE value is not in the range of 28 to 35 bits, an interrupt operation is triggered and the CPU is notified.

[0023] Secondly, a device is also proposed, including a memory and a processor, wherein the memory is used to store a program, and the processor is configured to implement the above-mentioned method for implementing PCIE switching ATU based on FPGA when executing the program.

[0024] like Figure 2 The following is a schematic diagram of the architecture of PCIE switching ATU based on FPGA, combined with Figure 2 As shown, in the processor based on this architecture, at least a CPU, a PCIE interconnect bus 1, a PCIE control transmission unit, built-in logic, a PCIE interconnect bus II and a DDR memory subsystem are included. The CPU is connected to the PAGE register and the BAR base address register in the PCIE control transmission unit through the PCIE interconnect bus I. The built-in logic is the built-in code of the processor. The built-in logic can control the ATU register through the PAGE register. The ATU register is connected to the DDR memory subsystem through the PCIE interconnect bus II. The DDR memory subsystem includes multiple DDRs, such as DDR0, DDR1, DDR2, etc.

[0025] It should be noted that built-in logic is code built into the processor, while FPGA logic is code built into the FPGA. Both codes can calculate the PAGE value based on the corresponding address and fill it into the ATU, thereby achieving control of the ATU. In this embodiment, the PCIE control transmission unit is also provided with an interrupt controller for triggering interrupt operations and notifying the CPU.

[0026] In addition, a storage medium is also proposed. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the above-mentioned method for implementing PCIE switching ATU based on FPGA.

[0027] In summary, the present invention uses the FPGA itself to implement ATU switching. By introducing the PAGE register and the FPGA logic for calculating the PAGE value, and combining the two situations of whether the RC controller can be directly controlled, the CPU's reading task of the corresponding DDR is completed in a classified manner via the PCIE interconnect bus. The delay is negligible, and there is no performance loss when accessing the DDR via the PCIE bus. No additional software control is required, the operation links are reduced, and performance is further guaranteed, which is a significant improvement.

[0028] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for implementing PCIE switching ATU based on FPGA, characterized in that: The steps include: S1. Define the PCIE BAR space as 256M and the address width as 28 bits. Introduce the PAGE register and the FPGA logic for calculating the PAGE value into the PCIE controller. S2. Determine whether the FPGA can directly control the PCIE RC controller. If so, use the CPU to send the DDR address to be accessed to the RC controller. In the RC controller, use the FPGA logic in step S1 to obtain bits 28 to 35 of the address as the page value I and set the PCIE ATU register based on the page value I. In the RC controller, continue to use the FPGA logic in step S1 to obtain bits 0 to 27 of the address as the offset in the BAR base address register to initiate a read or write operation. If not, jump to step S3; S3. Use the CPU to get bits 28 to 35 of the address as PAGE value II and write it into the PAGE register. In the PCIE RC controller, set the PCIE ATU register according to PAGE value II. Continue to use the FPGA logic in step S1 to get the ATU register. The CPU then gets bits 0 to 27 of the address as the offset in the BAR base address register to initiate a read and write operation. S4. After completing the read and write operations in step S2 or step S3, stop running.

2. The method for implementing PCIE switching ATU based on FPGA according to claim 1, characterized in that: When any PAGE value is not in the range of 28 to 35 bits, an interrupt operation is triggered and the CPU is notified.

3. A device, characterized in that The invention comprises a memory and a processor, wherein the memory is used to store a program, and the processor is configured to implement a method for implementing PCIE switching ATU based on FPGA as described in any one of claims 1 to 2 when executing the program.

4. A device according to claim 3, characterized in that The processor includes at least a CPU, a PCIE interconnect bus 1, a PCIE control transmission unit, built-in logic, a PCIE interconnect bus II and a DDR memory subsystem. The CPU is connected to the PAGE register and the BAR base address register in the PCIE control transmission unit through the PCIE interconnect bus I. The built-in logic controls the ATU register through the PAGE register. The ATU register is connected to the DDR memory subsystem through the PCIE interconnect bus II. The DDR memory subsystem includes multiple DDRs.

5. The device according to claim 3, characterized in that: The PCIE control transmission unit is also provided with an interrupt controller for triggering an interrupt operation and notifying the CPU.

6. A storage medium, characterized in that When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method for implementing PCIE switching ATU based on FPGA as described in any one of claims 1 to 2.

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