A read-only device supporting a multi-lane m.2 interface

Abstract

The application discloses a read-only device supporting a multi-channel M.2 interface, which adopts a master control module integrating a PCIe and a SATA protocol analysis engine, the master control module identifies the protocol followed by the M.2 device connected to each interface and switches the protocol processing logic; the master control module is further configured with a multi-path arbitration logic unit for adjusting the resource allocation between the interfaces; an interface module at least including a plurality of M.2 interfaces, each M.2 interface independently configuring a PCIe channel and a SATA channel to connect the master control module; a security interception module synchronizing the protocol information followed by the M.2 device connected to each interface and the write protection state information of each interface from the master control module, judging and executing whether to implement write protection on the interface. The application solves the problem that the existing evidence collection device lacks M.2 native support and the requirement of high-concurrency safe transmission of data of multiple transmission channels.

Description

Technical Field

[0001] This application relates to the field of reading and writing electronic devices, and in particular to a read-only device that supports an M.2 interface. Background Technology

[0002] With the widespread adoption of M.2 solid-state drives (SSDs), their application demands in scenarios such as digital forensics, data security, and high-speed storage have surged. In these scenarios, read-only locking technology is required. This technology is a concurrency control mechanism that allows multiple threads to read shared resources simultaneously, but prohibits write operations until all read locks are released before an exclusive lock can be acquired. Specifically, read-only locks typically have two states: read-locked and write-locked. In the read-locked state, multiple threads can acquire read locks simultaneously, sharing access to the resource; in the write-locked state, only one thread is allowed to hold the write lock, and all read and write requests are blocked.

[0003] However, existing read-only lock technology has significant limitations and is difficult to meet the data protection requirements of multi-channel, high-concurrency scenarios. The specific technical bottlenecks are as follows: 1. Insufficient interface compatibility, relying on adapter solutions. Current mainstream read-only lock devices are primarily designed for traditional interfaces such as USB and SATA, lacking native support for M.2 interfaces. Users who need to perform read-only operations on M.2 hard drives must use a USB adapter or PCIe adapter, which not only increases hardware complexity but may also lead to signal attenuation and reduced transmission speeds.

[0004] 2. Insufficient hardware and protocol compatibility The M.2 interface relies on PCIe or SATA protocols for data transmission, and existing adapter solutions (such as USB to M.2) may cause compatibility issues due to protocol conversion, such as inability to recognize NVMe protocol hard drives or limited transfer rates. Furthermore, resource conflicts are prone to occur during multi-channel concurrency, and there is a lack of effective bus arbitration mechanisms.

[0005] 3. Limited scalability of application scenarios Existing devices mostly focus on a single interface or a small number of storage media, which cannot adapt to the diverse forms of M.2 hard drives (such as different sizes and protocol versions) and the need for multi-device collaboration. Summary of the Invention

[0006] This application provides a read-only device that supports multi-channel M.2 interfaces to address the problem that existing electronic forensics devices lack native support for M.2 interfaces and are insufficiently adaptable to the needs of multi-channel, high-concurrency data protection.

[0007] An embodiment of this application provides a read-only device supporting a multi-channel M.2 interface, comprising: The main control module integrates a PCIe and SATA protocol parsing engine. The main control module is used to call the PCIe and SATA protocol parsing engine to identify the protocol followed by the M.2 devices connected to each interface and switch the protocol processing logic. The main control module is also configured with a multi-way arbitration logic unit to adjust the resource allocation between the various interfaces. The interface module includes at least multiple M.2 interfaces. Each M.2 interface is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the protocol followed by the M.2 device connected to the interface is NVMe, the interface module performs data transmission through the PCIe channel, and when it identifies that the protocol followed is SATA, it performs data transmission through the SATA channel. The security interception module is connected to the main control module to synchronize the protocol information followed by each M.2 device connected to each interface and the write protection status information of each interface from the main control module, and to determine and execute whether to implement write protection for the interface based on the protocol information and write protection status information.

[0008] Furthermore, in this invention, the main control module uses an RK3568 chip, and each M.2 interface is independently connected to the RK3568 chip, wherein: The M.2 interface conforming to the NVMe protocol is connected to the RK3568 chip as follows: The clock signal pin of the M.2 interface is connected to the corresponding high-speed clock output pin of the RK3568 chip; The M.2 interface transmit data differential signal pairs TX_P and TX_N are connected to the high-speed data receive pins of the RK3568 chip, and the M.2 interface receive data differential signal pairs RX_P and RX_N are connected to the corresponding high-speed data transmit pins of the chip. The M.2 interface conforming to the SATA protocol is connected to the RK3568 chip as follows: The SATA data pins of the M.2 interface are connected to the corresponding pins of the SATA controller inside the RK3568 chip.

[0009] Furthermore, the present invention also includes a USB 3.0 controller, and the interface module further includes a USB 3.0 interface, wherein the high-speed data transmission pin of the USB 3.0 interface is connected to the high-speed data pin of the USB 3.0 controller.

[0010] Furthermore, in this invention, the step of determining and executing whether to implement write protection for the interface based on the protocol information and write protection status information includes: Configure a PCIe TLP packet filter to intercept all TLP headers containing MWR opcodes to write-protect the M.2 interface; Disconnect the write enable signal of the USB 3.0 device to write-protect the USB 3.0 interface.

[0011] Furthermore, in this invention, the multi-way arbitration logic unit is used to adjust the resource allocation between various interfaces, including: Configure the initial bandwidth to the corresponding interface according to the protocol of each interface; During data transmission, the CRC error rate of each channel is collected in real time. For M.2 channels using the same protocol: When the CRC error rate of a certain M.2 channel exceeds the threshold, its link rate is gradually reduced until the error is eliminated; The total reduced link rate of each M.2 channel is obtained in real time. Based on the real-time CRC error rate of the M.2 channels whose current CRC error rate does not exceed the threshold, the total reduced link rate is allocated in descending order to the M.2 channels whose CRC error rate does not exceed the threshold. When the CRC error rate of a certain M.2 channel drops below the threshold for a continuous preset time after exceeding the threshold, the link rate of that M.2 channel is restored to the average of the link rates of all M.2 channels in transmission where the CRC error rate does not exceed the threshold. Correspondingly, the link rates of M.2 channels with link rates higher than the average of the link rates are synchronously reduced, and the reduction ratio of each M.2 channel is gradually reduced in descending order of its link rate before reduction.

[0012] Furthermore, in this invention, when the CRC error rate of a certain M.2 channel exceeds a threshold, its link rate is gradually reduced until the error is eliminated; Real-time monitoring of flash memory temperature sensor data for each M.2 interface; When the temperature reaches the first threshold range, the corresponding M.2 interface is clocked and spread. When the temperature reaches the second threshold range, the link rate of the corresponding M.2 interface is constrained to below 50% of the nominal value until the temperature is below the second threshold range, at which point the constraint on the link rate of the corresponding M.2 interface is released. The temperature values ​​in the first threshold interval are less than those in the second threshold interval.

[0013] Furthermore, in this invention, the multi-way arbitration logic unit, used to adjust resource allocation between various interfaces, further includes: When a signature forensic instruction is detected, all transmissions on non-forensic channels are stopped, and the current link state is frozen. Prioritize the TLP packets in the evidence collection channel to the highest level; Once the evidence collection is complete, the bandwidth of the evidence collection channel will be allocated to the non-evidence collection channel, restoring the bandwidth ratio of the non-evidence collection channel to its state before it was frozen.

[0014] Furthermore, in this invention, the multi-way arbitration logic unit, used to adjust resource allocation between various interfaces, further includes: When a USB device timeout occurs, bandwidth is dynamically and gradually added to the USB 3.0 interface from the emergency bandwidth pool, which is a dedicated bandwidth pre-configured specifically for the USB 3.0 interface.

[0015] Furthermore, in this invention, the base bandwidth of the NVMe device is 1.8-2.5 times that of the base bandwidth of the SATA device.

[0016] Furthermore, in this invention, there are at least four M.2 interfaces.

[0017] In this embodiment, a read-only device supporting a multi-channel M.2 interface is provided. This device employs a main control module that integrates PCIe and SATA protocol parsing engines. The main control module is used to call the PCIe and SATA protocol parsing engines to identify the protocols followed by the M.2 devices connected to each interface and switch protocol processing logic accordingly. The main control module is also configured with multiple arbitration logic units to adjust resource allocation among the interfaces. An interface module includes at least multiple M.2 interfaces, each M.2 interface independently configured with a PCIe channel and a SATA channel connected to the main control module. The interface module responds to the main control module's identification that the protocol followed by the M.2 device connected to the interface is NVMe, by transmitting data through the PCIe channel; and by identification that the protocol followed is SATA, by transmitting data through the SATA channel. A security interception module is connected to the main control module to synchronize the protocol information followed by the M.2 devices connected to each interface and the write protection status information of each interface from the main control module, and determines and executes whether to implement write protection for the interface based on the protocol information and write protection status information. This application addresses the lack of native support for M.2 in existing forensic equipment and the need for secure, high-concurrency data transmission across multiple transmission channels. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the composition of a read-only device supporting a multi-channel M.2 interface according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram illustrating a method for adjusting resource allocation between various interfaces by a multi-way arbitration logic unit according to an embodiment of this application; Figure 3 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0022] Embodiments of the present invention provide a read-only device that supports multi-channel M.2 interfaces. This device can directly and natively support M.2 interface devices and coordinate multi-channel data transmission, such as... Figure 1 As shown, the read-only device supporting a multi-channel M.2 interface includes: The main control module integrates a PCIe and SATA protocol parsing engine. The main control module is used to call the PCIe and SATA protocol parsing engine to identify the protocol followed by the M.2 devices connected to each interface and switch the protocol processing logic. The main control module is also configured with a multi-way arbitration logic unit to adjust the resource allocation between the various interfaces.

[0023] The interface module includes at least multiple M.2 interfaces. Each M.2 interface is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the M.2 device connected to the interface follows the NVMe protocol, the interface module performs data transmission through the PCIe channel, and when it identifies that the protocol followed is the SATA protocol, it performs data transmission through the SATA channel.

[0024] The security interception module is connected to the main control module to synchronize the protocol information followed by each M.2 device connected to each interface and the write protection status information of each interface from the main control module, and to determine and execute whether to implement write protection for the interface based on the protocol information and write protection status information.

[0025] This embodiment of a read-only device supporting multi-channel M.2 interfaces enables native support for M.2 devices by configuring PCIe and SATA channels to support different protocols of M.2 devices, thus eliminating the need for external conversion devices, reducing signal latency, and achieving a measured latency reduction of 60%. A multi-arbitration logic unit coordinates the resource allocation of multiple channels, maintaining efficient collaboration in multi-channel transmission, and a security interception module implements necessary write protection for the interface to prevent data tampering during evidence collection.

[0026] The aforementioned devices support mixed insertion of multiple NVMe / SATA M.2 devices. Taking a four-channel M.2 interface as an example, a solution using two Samsung 980 Pro NVMe interfaces and two Samsung 860 EVO SATA M.2 interfaces is employed. The NVMe / SATA protocol type is identified by sending PCIe ConfigurationRead TLP packets, with a 100% success rate. The native interface design reduces power consumption, with a four-channel concurrent power consumption of only 40W. Compared to the traditional solution requiring four adapters and external latches, this represents a 108% improvement in energy efficiency. The four-channel concurrent read speed reaches 55GB / min, a four-fold increase in efficiency compared to traditional solutions. In the field of electronic forensics, this reduces the time required for multi-device forensics collection by 75% and lowers labor costs by 40%.

[0027] In some preferred embodiments, the main control module uses an RK3568 chip, and each M.2 interface is independently connected to the RK3568 chip, wherein: The M.2 interface conforming to the NVMe protocol is connected to the RK3568 chip as follows: The clock signal pin of the M.2 interface is connected to the corresponding high-speed clock output pin of the RK3568 chip; The M.2 interface transmit data differential signal pairs TX_P and TX_N are connected to the high-speed data receive pins of the RK3568 chip, and the M.2 interface receive data differential signal pairs RX_P and RX_N are connected to the corresponding high-speed data transmit pins of the chip. The M.2 interface conforming to the SATA protocol is connected to the RK3568 chip as follows: The SATA data pins of the M.2 interface are connected to the corresponding pins of the SATA controller inside the RK3568 chip.

[0028] Because the SATA protocol has high requirements for signal integrity, the data transmission lines must be of equal length and as short as possible during wiring to reduce signal transmission delay and loss. Similarly, the power pins are connected to a stable power supply, and a suitable filtering circuit is installed at the power input, such as a π-type filter circuit consisting of a ferrite bead and a capacitor in series, to further reduce the impact of power ripple on the device. Furthermore, by setting specific GPIO pin levels on the RK3568 chip, such as setting GPIO_X high to indicate that the M.2 interface is currently operating in SATA protocol mode, the chip's internal memory controller will switch to the corresponding protocol processing logic based on this level state. The four M.2 interfaces are connected to the corresponding pins of the RK3568 chip in the above manner, with the clock, data, and control signals of each interface independent to ensure that the M.2 devices can operate in parallel.

[0029] In some preferred embodiments, a USB 3.0 controller is also included, and the interface module further includes a USB 3.0 interface, the high-speed data transmission pins of which are connected to the high-speed data pins of the USB 3.0 controller.

[0030] Because USB 3.0 offers higher data transfer rates, it places extremely stringent requirements on signal integrity. During cabling, these high-speed data lines must employ differential pair routing, and the line width and spacing must strictly adhere to the USB 3.0 standard, typically with a line width of 5 mil and a spacing of 4 mil. Simultaneously, to reduce signal interference, high-speed data lines must maintain a certain distance from other low-frequency signal lines, for example, at least 10 mil. A common-mode inductor must be placed near the USB interface to suppress common-mode interference on the high-speed data lines, ensuring accurate data transmission.

[0031] In this embodiment, in addition to the M.2 read-only interface, the device is also equipped with a USB 3.0 read-only interface, which is compatible with traditional USB devices such as USB flash drives and external hard drives, providing greater compatibility while ensuring data security.

[0032] In some preferred embodiments, after the main control module obtains the protocol of the device connected to each interface and shares it with the secure connection module, the security interception module determines the type of each interface based on the protocol information and write protection status information, configures different write protection schemes for different protocol types, and performs write protection for interfaces that have not yet implemented write protection, wherein: For the M.2 interface, configure a PCIe TLP packet filter to intercept all TLP headers containing the MWR opcode to write-protect the M.2 interface.

[0033] For USB interfaces, disconnecting the write enable signal of USB 3.0 devices is used to write-protect the USB 3.0 interface.

[0034] In some preferred embodiments, since multiple transmissions exist in the implementation of this application, and each transmission channel is independent, in order to coordinate the various channels and ensure transmission efficiency, this application employs the aforementioned multi-channel arbitration logic unit to adjust the resource allocation between various interfaces, controlling aspects such as initial transmission configuration and dynamic adjustment during the transmission process, to ensure efficient transmission coordination. Specifically, in this embodiment, a method for resource allocation between various interfaces is provided, including: Step S101: Configure the initial bandwidth to the corresponding interface according to the protocol of each interface. In some preferred embodiments, the base bandwidth of the NVMe device is 1.8-2.5 times that of the SATA device.

[0035] Step S102: During data transmission, the CRC error rate of each channel is collected in real time. For M.2 channels of the same protocol: when the CRC error rate of a certain M.2 channel exceeds the threshold, its link rate is reduced successively until the error is eliminated.

[0036] Step S103: Real-time acquisition of the total reduced link rate of each M.2 channel whose link rate is reduced each time; and in descending order of the real-time CRC error rate of the M.2 channels whose current CRC error rate does not exceed the threshold, the total reduced link rate is allocated to the M.2 channels whose CRC error rate does not exceed the threshold.

[0037] Step S104: When the CRC error rate of a certain M.2 channel drops below the threshold for a continuous preset time after exceeding the threshold, the link rate of that M.2 channel is restored to the average of the link rates of all M.2 channels in transmission where the CRC error rate does not exceed the threshold. Correspondingly, the link rates of M.2 channels with link rates higher than the average of the link rates are synchronously reduced, and the reduction ratio of each M.2 channel is gradually reduced in order from high to low link rates before the reduction.

[0038] CRC can detect single-bit errors, double-bit errors, odd-numbered errors, and errors with a burst length less than or equal to the generator polynomial degree. Therefore, CRC can detect errors that may occur during data transmission or storage, ensuring data integrity and correctness. Before receiving data, the receiver needs to perform error detection; the receiver only accepts the data if and only if the detection result is correct. Commonly used CRC detection methods include parity check, Internet check, and cyclic redundancy check, etc., but no specific limitations are imposed in this embodiment.

[0039] In this embodiment, in step S102, when the CRC error rate exceeds the threshold, it indicates that the transmission error rate of the channel is high. Therefore, the transmission efficiency is low, and it is impossible to control data integrity and correctness. Furthermore, because data packets need to be repeatedly transmitted, the transmission rate will also be affected. Therefore, it is necessary to investigate the cause immediately. At this time, the link rate is gradually reduced until the error is eliminated. That is, the rate is reduced by a portion first, and the CRC error rate is monitored to see if it can recover to normal. If it can, the link rate is no longer reduced. If the CRC error rate cannot recover, the rate is reduced by a portion a second time. This cycle continues. As the link rate decreases, the transmission pressure of the channel is relieved. If necessary, joint investigation and troubleshooting can be carried out to eliminate the cause of the fault, so that the CRC error rate is maintained at a certain transmission rate and does not exceed the threshold. Then, the link rate is no longer reduced. The first and second steps can be divided by time interval or data transmission volume, such as every 1 second, 2 seconds, or 3 seconds, or every 200MB, 300MB, 500MB, or 1GB of data transmission. Those skilled in the art can set the specific steps as needed. The link rate reduction mentioned above can be a uniform reduction or a proportional reduction. Each channel can use the same or different link rate reduction strategies each time, which can be set by those skilled in the art as needed.

[0040] In some optional embodiments, when the CRC error rate is first detected to exceed the threshold, the link rate of the channel is reduced by 100 Mbps. Thereafter, the CRC error rate of the channel is checked every 2 seconds. If both subsequent detected CRC error rates exceed the threshold, and the subsequent detected CRC error rate is M% of the previous detected CRC error rate, and if M is greater than or equal to 100, the link rate of the channel is reduced to 1 / M% of the previous rate. If M is less than 100, the rate is reduced at a constant rate of 100 Mbps each time. This scheme allows for rapid rate limiting of channels where the CRC error rate shows no improvement.

[0041] In step S103, taking an M.2 interface with four channels, all conforming to the NVMe protocol, as an example, if the CRC error rate of the first and second channels exceeds the threshold, while the CRC error rates of the third and fourth channels do not exceed the threshold and the CRC error rate of the third channel is lower than that of the fourth channel, then the link rates of the first and second channels are reduced. The total reduced link rate D for these two channels is 200Mbps, and more than half of this 200Mbps is allocated to the third channel, with the remainder allocated to the fourth channel. Specifically, when the ratio of the CRC error rate of the third channel to that of the fourth channel is A:B, A / (A+B) of the link rate in D is allocated to the third channel, and the remaining link rate is allocated to the fourth channel. In this way, channels with higher transmission efficiency can be prioritized, enabling them to complete transmission tasks efficiently.

[0042] In step S104, when the CRC error rate of a certain M.2 channel drops below the threshold for a continuous preset time, the channel is considered to have resumed normal transmission. During this period, if the CRC error rate does not exceed the threshold each time, the link rate of the channel will not be reduced accordingly. After that, once the CRC error rate is below the threshold for a continuous preset time, the channel is speed-upped, with the link rate of other similar channels being monitored in real time. Taking the aforementioned 4-channel NVMe protocol M.2 interface as an example, when the first channel meets the speed-up condition, the first, third, and fourth channels are all channels whose CRC error rates do not exceed the threshold. Therefore, the link rate of the first channel after speed-up is taken as the average of the current link rates of these three channels. Channels in the third and fourth channels that have a higher average current link rate are slowed down accordingly. The speed-down percentage of each M.2 channel gradually decreases in descending order of its link rate before speed-down. For example, if the current average link rate is N, and the link rates of the third and fourth channels before the speed reduction are E and F respectively, where E is greater than F and both are greater than N, then the speed reduction ratio of the third channel is greater than that of the fourth channel. This allows more resources of the higher-speed channels to be allocated to the channels to be upgraded, and the changes in the speed of the channels to be upgraded before and after the upgrade are controllable. On the one hand, this facilitates further monitoring of whether the transmission process of the channel is normal, and on the other hand, it balances the transmission of all channels.

[0043] In some preferred embodiments, since temperature affects transmission performance, step S102, which describes gradually reducing the link rate of an M.2 channel until the error is eliminated when the CRC error rate exceeds a threshold, further includes: S1021, Real-time monitoring of flash memory temperature sensor data for each M.2 interface; S1022. When the temperature reaches the first threshold range, the corresponding M.2 interface is clocked and spread. S1023. When the temperature reaches the second threshold range, constrain the link rate of the corresponding M.2 interface to below 50% of the nominal value until the temperature is below the second threshold range, and release the constraint on the link rate of the corresponding M.2 interface. The temperature values ​​in the first threshold interval are less than those in the second threshold interval.

[0044] When the temperature is too high, for example, in the first threshold range of 70℃~85℃, clock spread spectrum can reduce the heat concentration caused by concentrated frequency. When the temperature rises further to the second threshold range, for example, above 85℃, rate limiting can prevent adverse effects such as disk damage. In this embodiment, rate limiting due to excessive temperature has higher priority than rate limiting due to CRC errors.

[0045] The released bandwidth is prioritized for heat dissipation-related command transmissions of the USB interface (such as SMART data reading). Once the temperature returns to normal, in some specific embodiments, the original bandwidth is gradually restored in increments of 200 Mbps.

[0046] In some optional embodiments, in order to coordinate the allocation of transmission resources and ensure transmission stability, stability detection is performed during link rate adjustment: After each link rate reallocation, monitor the following stability metrics: The change in Skew value of the PCIe link (Δ < 100ps). USB eye diagram opening (≥70% UI); BER of M.2 interface (<1E-12). When the metric is abnormal, it will automatically roll back to the previous stable configuration.

[0047] In some preferred embodiments, the multi-way arbitration logic unit, used to adjust resource allocation among various interfaces, further includes: S201. When a signature for evidence collection instruction is detected, stop the transmission of all non-evidence collection channels and freeze the current link state. S202. Prioritize the TLP packets in the evidence collection channel to the highest level; S203. After the evidence collection is completed, the bandwidth of the evidence collection channel is allocated to the non-evidence collection channel, so that the bandwidth ratio of the non-evidence collection channel is restored to that before it was frozen.

[0048] In this embodiment, the TLP packet of the forensic instruction is characterized by a TC field of 3 in the Header (highest priority) and a data payload containing a SHA-256 hash signature (such as 0x9F2D...). By prioritizing the service of channels with forensic needs in the above manner, it is possible to facilitate and quickly complete the forensic process.

[0049] In some optional examples, the multi-arbitration logic unit, used to adjust the resource allocation between the various interfaces, further includes: dynamically reducing the clock frequency of the SATA protocol channel to 60%-80% of the base value when the M.2 interface is under full load.

[0050] In some optional examples, the multiple arbitration logic unit, used to adjust the resource allocation between the various interfaces, further includes: triggering a bandwidth rebalancing mechanism when a USB interface is inserted into a high-speed storage device, proportionally reducing the PCIe link width of the idle M.2 channel.

[0051] In some preferred embodiments, the multi-way arbitration logic unit, used to adjust resource allocation among various interfaces, further includes: S301. When a USB device transmission times out, bandwidth is dynamically and gradually added to the USB 3.0 interface from the emergency bandwidth pool. The emergency bandwidth pool is a dedicated bandwidth pre-configured specifically for the USB 3.0 interface. For example, when a USB transmission times out, the bandwidth of the USB 3.0 interface is increased by 10% every 2 seconds to accelerate the transmission.

[0052] The read-only device also provided in this application embodiment includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it enables the electronic device to implement the control method described in the above embodiment.

[0053] In one embodiment, the read-only device can be a server, and in this embodiment, the electronic device can be structured as follows: Figure 3 As shown, it includes a memory 2001, a communication module 2003, and one or more processors 2002.

[0054] The memory 2001 is used to store computer programs executed by the processor 2002. The memory 2001 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and programs required to run instant messaging functions, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc.

[0055] Memory 2001 may be volatile memory, such as random-access memory (RAM); memory 2001 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 2001 may be any other medium capable of carrying or storing a desired computer program having the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 2001 may be a combination of the above-mentioned memories.

[0056] Processor 2002 may include one or more central processing units (CPUs) or digital processing units, etc. Processor 2002 is used to implement the above-mentioned audio data processing method when calling computer programs stored in memory 2001.

[0057] The communication module 2003 is used to communicate with terminal devices and other servers.

[0058] This application embodiment does not limit the specific connection medium between the memory 2001, communication module 2003, and processor 2002. This application embodiment... Figure 3 The memory 2001 and the processor 2002 are connected via a bus 2004, which is in... Figure 3 The connections between other components are illustrated with arrows and are for illustrative purposes only, not as limiting information. The Bus 2004 can be divided into address bus, data bus, control bus, etc. For ease of description, Figure 3 The text uses only one arrow to describe it, but does not indicate that there is only one bus or one type of bus.

[0059] It should also be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0060] Based on the same inventive concept as the above-described method embodiments, embodiments of the present invention also provide a computer-readable storage medium for storing a computer program. When the computer program is run on a computer, it enables the electronic device to implement the control method described in the above embodiments. The computer-readable storage medium can be a readable signal medium or a readable storage medium. A readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0061] Based on the same inventive concept as the above-described method embodiments, embodiments of the present invention also provide a computer program product, which includes a computer program that, when run on an electronic device, causes the electronic device to perform the steps of the control methods described above according to various exemplary embodiments of this application. The program product may take the form of any combination of one or more readable media. These computer program commands can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the commands executed by the processor of the computer or other programmable data processing device generate a process for implementing... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0062] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

Claims

1. A read-only device supporting a multi-channel M.2 interface, characterized in that, include: The main control module integrates a PCIe and SATA protocol parsing engine. The main control module is used to call the PCIe and SATA protocol parsing engine to identify the protocol followed by each M.2 device connected to the interface and switch the protocol processing logic. The main control module is also equipped with a multi-arbitration logic unit for adjusting the resource allocation between various interfaces; The interface module includes at least multiple M.2 interfaces. Each M.2 interface is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the protocol followed by the M.2 device connected to the interface is NVMe, the interface module performs data transmission through the PCIe channel, and when it identifies that the protocol followed is SATA, it performs data transmission through the SATA channel. The security interception module is connected to the main control module to synchronize the protocol information followed by each M.2 device connected to each interface and the write protection status information of each interface from the main control module, and to determine and execute whether to implement write protection for the interface based on the protocol information and write protection status information. The multi-way arbitration logic unit is used to adjust the resource allocation between various interfaces, including: Configure the initial bandwidth to the corresponding interface according to the protocol of each interface; During data transmission, the CRC error rate of each channel is collected in real time. For M.2 channels using the same protocol: When the CRC error rate of a certain M.2 channel exceeds the threshold, its link rate is gradually reduced until the error is eliminated; The total reduced link rate of each M.2 channel is obtained in real time. Based on the real-time CRC error rate of the M.2 channels whose current CRC error rate does not exceed the threshold, the total reduced link rate is allocated in descending order to the M.2 channels whose CRC error rate does not exceed the threshold. When the CRC error rate of a certain M.2 channel drops below the threshold for a continuous preset time after exceeding the threshold, the link rate of that M.2 channel is restored to the average of the link rates of all M.2 channels in transmission where the CRC error rate does not exceed the threshold. Correspondingly, the link rates of M.2 channels with link rates higher than the average of the link rates are synchronously reduced, and the reduction ratio of each M.2 channel is gradually reduced in descending order of its link rate before reduction.

2. The read-only device according to claim 1, characterized in that, The main control module uses the RK3568 chip, and each M.2 interface is independently connected to the RK3568 chip, wherein: The M.2 interface conforming to the NVMe protocol is connected to the RK3568 chip as follows: The clock signal pin of the M.2 interface is connected to the corresponding high-speed clock output pin of the RK3568 chip; The M.2 interface transmit data differential signal pairs TX_P and TX_N are connected to the high-speed data receive pins of the RK3568 chip, and the M.2 interface receive data differential signal pairs RX_P and RX_N are connected to the corresponding high-speed data transmit pins of the chip. The M.2 interface conforming to the SATA protocol is connected to the RK3568 chip as follows: The SATA data pins of the M.2 interface are connected to the corresponding pins of the SATA controller inside the RK3568 chip.

3. The read-only device according to claim 1, characterized in that, It also includes a USB 3.0 controller, and the interface module further includes a USB 3.0 interface, the high-speed data transmission pin of which is connected to the high-speed data pin of the USB 3.0 controller.

4. The read-only device according to claim 3, characterized in that, The step of determining and executing whether to implement write protection for the interface based on the protocol information and write protection status information includes: Configure a PCIe TLP packet filter to intercept all TLP headers containing MWR opcodes to write-protect the M.2 interface; Disconnect the write enable signal of the USB 3.0 device to write-protect the USB 3.0 interface.

5. The read-only device according to claim 4, characterized in that, When the CRC error rate of a certain M.2 channel exceeds the threshold, its link rate is gradually reduced until the error is eliminated. Real-time monitoring of flash memory temperature sensor data for each M.2 interface; When the temperature reaches the first threshold range, clock spread spectrum is applied to the corresponding M.2 interface; When the temperature reaches the second threshold range, the link rate of the corresponding M.2 interface is constrained to below 50% of the nominal value until the temperature is below the second threshold range, at which point the constraint on the link rate of the corresponding M.2 interface is released. The temperature values ​​in the first threshold interval are less than those in the second threshold interval.

6. The read-only device according to claim 4, characterized in that, The multi-way arbitration logic unit, used to adjust resource allocation among various interfaces, also includes: When a signature forensic instruction is detected, all transmissions on non-forensic channels are stopped, and the current link state is frozen. Prioritize the TLP packets in the evidence collection channel to the highest level; Once the evidence collection is complete, the bandwidth of the evidence collection channel will be allocated to the non-evidence collection channel, restoring the bandwidth ratio of the non-evidence collection channel to its state before it was frozen.

7. The read-only device according to claim 4, characterized in that, The multi-way arbitration logic unit, used to adjust resource allocation among various interfaces, also includes: When a USB device timeout occurs, bandwidth is dynamically and gradually added to the USB 3.0 interface from the emergency bandwidth pool, which is a dedicated bandwidth pre-configured specifically for the USB 3.0 interface.

8. The read-only device according to claim 4, characterized in that, The base bandwidth of the NVMe device is 1.8-2.5 times that of the SATA device.

9. The read-only device according to claim 1, characterized in that, There are at least four M.2 interfaces.

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