memory

Abstract

The application discloses a memory, which comprises a memory array composed of a plurality of OTP units. The OTP unit comprises a selection transistor composed of an NMOS transistor and a storage transistor composed of a PMOS transistor. The source of the selection transistor is a bit line end of the OTP unit. The drain of the selection transistor is connected to the drain of the storage transistor. The source of the storage transistor is a source line end of the OTP unit. The gate of the selection transistor is a selection gate of the OTP unit, and the gate of the storage transistor is a floating gate. The memory array comprises an NMOS group and a PMOS group. Each selection transistor is formed in the NMOS group. Each storage transistor is formed in the PMOS group. The programming voltage of the OTP unit is greater than the power supply voltage. The maximum voltage of the voltage domain of the NMOS group is the power supply voltage. The maximum voltage of the voltage domain of the PMOS group is the programming voltage. The application can reduce the area of the memory and lower the programming interference.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a memory. Background Technology

[0002] Existing memories include OTP memories that use one-time programmable (OTP) cells. For example... Figure 1 The diagram shown is a layout of the existing memory's OTP (Overlay Point) cells; as shown... Figure 2 The diagram shown is a circuit diagram of an existing memory's OTP unit; as shown... Figure 3 The diagram shown is a circuit diagram of a storage array of an existing memory. The OTP cell 101 is composed of two PMOS transistors connected in series, one of which is the select transistor 202 and the other is the storage transistor 203.

[0003] like Figure 1 As shown, the selector tube 202 and the storage tube 203 are formed in the same active region 104, which is composed of an N-type well region. Figure 2 As shown, the N-type well region is connected to the N-well electrode VNW, and the N-type well regions of all the OTP cells 101 in the memory array are connected to the N-well electrode VNW.

[0004] The gate 105 of the select transistor 202 is a select gate (SG).

[0005] The gate 106 of the storage tube 203 is a floating gate (FG).

[0006] The source and drain regions of the select transistor 202 are self-aligned and formed in the active regions 104 on both sides of the gate 105; the source and drain regions of the memory transistor 203 are self-aligned and formed in the active regions 104 on both sides of the gate 106. The drain region of the select transistor 202 and the source region of the memory transistor 203 are shared; the source region of the select transistor 202 is connected to the source line VSL. Figure 3 In this configuration, all the source lines VSL of the selector tube 202 are connected together.

[0007] The drain region of the storage tube 203 is connected to the corresponding bit line VBL. Figure 3 The text displays multiple rows of bit lines, such as bit line VBL. <1> VBL <2> VBL <3> and VBL <4> .

[0008] The gate 105 terminal VSG of the select transistor 202 is connected to the word line VWL. Figure 3 The text displays multiple columns of word lines, such as the word line VWL. <1> VWL <2> and VWL <3> .

[0009] Existing memory is prone to program disturbances, as explained below:

[0010] Figure 3 In the diagram, the selected OTP unit during reading or programming is represented by the label 101a, and the three OTP units adjacent to the selected OTP unit 101a are represented by the labels 101b, 101c, and 101d, respectively. Specifically, OTP units 101b and 101a are located in the same row, OTP units 101c and 101a are located in the same column, OTP units 101d and 101b are located in the same column, and OTP units 101d and 101c are located in the same row.

[0011] Table 1

[0012]

[0013] As shown in Table 1, "Program" indicates programming, "selected cell" indicates the selected OTP unit 101a, and "unselected cell" indicates the unselected OTP unit. The four OTP units in Table 1 are numbered 1, 2, 3, and 4 respectively. The first OTP unit is located in the selected OTP unit 101a; the other three OTP units are unselected OTP units, namely: the second... Figure 3 The third one in OTP unit 101b is Figure 3 The fourth one in OTP unit 101c is Figure 3 In the OTP cell 101d, VWL represents the voltage of the word line of the corresponding OTP cell, VBL represents the voltage of the bit line of the corresponding OTP cell, VSL represents the voltage of the source line, and VNW represents the voltage of the N-well electrode.

[0014] It can be seen that, during programming, the VWL corresponding to the first OTP unit is... Figure 3 VWL in <2> The applied voltage is 0V; the VBL corresponding to the first OTP unit is Figure 3 VBL in <2> The applied voltage is 0V. The voltage of VSL is the programming voltage (VPP), and the voltage of VNW is also VPP. VPP is a high voltage greater than the power supply voltage. Combined with... Figure 3 As can be seen, the select transistor of the OTP unit 101a will be turned on, the high voltage of VSL will be transmitted to the source region of the memory transistor of the OTP unit 101a, the gate-source coupling will turn on the memory transistor of the OTP unit 101a, and finally, under the action of the high voltage of the source region of the memory transistor and the high voltage of VNW, the floating gate of the OTP unit 101a will be programmed by hot electron injection.

[0015] Compared to the first OTP unit, the VWL corresponding to the second OTP unit is Figure 3 VWL in <3> The applied voltage is VPP. The voltage VBL of the second OTP unit is the same as that of the first OTP unit. The second OTP unit will generate programming interference, mainly because, although the VWL corresponding to the second OTP unit is VPP and the select transistor of the second OTP unit will be turned off, the select transistor of the second OTP unit is actually prone to leakage, especially at high temperatures. The leakage of the select transistor of the second OTP unit can affect the stored information of the storage transistor of the second OTP unit, thus generating programming interference.

[0016] Compared to the first OTP unit, the voltage VWL of the third OTP unit is the same as that of the first OTP unit, and the voltage VBL of the third OTP unit is... Figure 3 VBL in <3> The applied voltage is VPP.

[0017] The voltage of VWL in the fourth OTP unit is the same as the voltage of VWL in the second OTP unit, and the voltage of VBL in the fourth OTP unit is the same as the voltage of VBL in the third OTP unit.

[0018] Table 2

[0019]

[0020] In Table 2, "read" indicates a read operation. In Table 2, the first to fourth OTP units are the same as those in Table 1. The corresponding voltages during reading are shown in Table 2, and the unit of each voltage is V. Summary of the Invention

[0021] To address the aforementioned technical problems, this invention provides a memory that can reduce memory area and decrease programming interference.

[0022] To solve the above-mentioned technical problems, the memory provided by the present invention includes a memory array composed of multiple OTP units.

[0023] The OTP unit includes a select transistor composed of NMOS transistors and a memory transistor composed of PMOS transistors.

[0024] The source of the select transistor serves as the bit line terminal of the OTP unit.

[0025] The drain of the selector is connected to the drain of the storage tube.

[0026] The source of the storage tube serves as the source terminal of the OTP unit.

[0027] The gate of the select transistor serves as the select gate of the OTP cell, and the gate of the storage transistor is a floating gate.

[0028] The memory array includes NMOS groups and PMOS groups.

[0029] Each of the selected transistors is formed in the NMOS group.

[0030] Each of the aforementioned memory transistors is formed within the PMOS group.

[0031] The programming voltage of the OTP unit is greater than the power supply voltage, and the maximum voltage of the voltage domain of the NMOS group is the power supply voltage; the maximum voltage of the voltage domain of the PMOS group is the programming voltage.

[0032] A further improvement is that the NMOS group is formed in a P-type semiconductor substrate; the P-type semiconductor substrate is connected to a substrate electrode, which serves as the back gate electrode of each of the select transistors.

[0033] A further improvement is that the PMOS group is formed in an N-type well, which is located in the P-type semiconductor substrate; the N-type well is connected to an N-well electrode, which serves as the back gate electrode of each memory transistor.

[0034] A further improvement is that the NMOS group includes multiple NMOS columns, and each NMOS column includes multiple select transistors.

[0035] The gates of the select transistors in the same NMOS column are connected together.

[0036] A further improvement is that, in the NMOS group, the select transistors located in each of the NMOS columns are arranged in multiple rows, and the select transistors in the same row are aligned.

[0037] A further improvement is that the PMOS group includes multiple memory transistors, which are arranged in multiple rows and columns.

[0038] A further improvement is that the area of ​​the select transistor is smaller than the area of ​​the storage transistor, and the area of ​​the NMOS group is smaller than the area of ​​the PMOS group.

[0039] A further improvement is that each of the OTP units is formed by connecting the select transistor in the NMOS group and the corresponding storage transistor in the PMOS group.

[0040] In the memory array, the gates of the select transistors of the OTP cells in the same column are connected to the word lines of the same column.

[0041] The source of each select transistor in the OTP cell of the same row is connected to the bit line of the same row.

[0042] The source of the storage tube in each of the OTP units is connected to the source line.

[0043] A further improvement is that, during programming, the selected OTP unit is the programming unit, and the voltage applied to the programming unit includes:

[0044] The voltage of the word line is the power supply voltage.

[0045] The voltage of the bit line is a first voltage, which is a positive voltage and is less than the power supply voltage.

[0046] The voltage of the source line is the programming voltage, and the voltage of the N-well electrode is the programming voltage.

[0047] A further improvement is that, during programming, the voltage of the word line of each unselected OTP unit in a different column from the programming unit is 0V.

[0048] A further improvement is that, during reading, the voltage applied to the selected OTP unit includes:

[0049] The voltage of the word line is the power supply voltage.

[0050] The voltage of the bit line is the power supply voltage minus the first bias voltage, the first bias voltage being the gate-source voltage of the select transistor, and the first bias voltage being greater than or equal to the threshold voltage of the select transistor to ensure that the select transistor is turned on.

[0051] The voltage of the source line is the power supply voltage, and the voltage of the N-well electrode is the power supply voltage.

[0052] A further improvement is that the gate of the selector is made of polysilicon, and a first gate dielectric layer is formed at the bottom of the gate of the selector.

[0053] A further improvement is that the gate of the memory transistor is made of polysilicon, and a second gate dielectric layer is formed at the bottom of the gate of the memory transistor.

[0054] A further improvement is that the material of the first gate dielectric layer includes an oxide layer.

[0055] The material of the second gate dielectric layer includes an oxide layer.

[0056] A further improvement is that, during programming, each non-selected OPT unit in a different column and row from the programming unit is a programming interference unit.

[0057] The voltage of the substrate electrode is less than the first voltage.

[0058] This invention first features a special configuration for the OTP unit, using NMOS transistors for the select transistors and PMOS transistors for the memory transistors. It also features a special configuration for the memory array, placing all select transistors in NMOS groups and all memory transistors in PMOS groups. Furthermore, this invention uses the source of the select transistor as the bit line terminal and the source of the memory transistor as the source line terminal. This connection structure ensures that the maximum voltage of the select transistor during read / write operations is the power supply voltage, without bearing a large programming voltage. Since the size of the select transistor needs to meet voltage withstand requirements, the larger the operating voltage, the larger the required size of the select transistor, and vice versa. Therefore, the size of the select transistor in this invention can be made smaller. Placing all select transistors in NMOS groups significantly reduces the area of ​​the NMOS groups. Simultaneously, the area of ​​the decoder required for decoding the select gate, i.e., the word line, is also reduced, ultimately reducing the memory area.

[0059] In this invention, since NMOS transistors are used as selection transistors, compared with PMOS transistors, the back gate electrode of the selection transistor and the back gate electrode of the storage transistor can be set independently. In this way, by setting the voltage of the back gate electrode of the selection transistor, the leakage current of each selection transistor in a different column from the programming unit can be greatly reduced during programming, thereby reducing programming interference. Attached Figure Description

[0060] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0061] Figure 1 This is the layout of the OTP cells in the existing memory;

[0062] Figure 2 This is a circuit diagram of the OTP unit of an existing memory.

[0063] Figure 3 It is a circuit diagram of an existing memory array;

[0064] Figure 4 This is a circuit diagram of the OTP unit of the memory in an embodiment of the present invention;

[0065] Figure 5 This is a layout of the memory array of the memory according to an embodiment of the present invention;

[0066] Figure 6 It is along Figure 5 A schematic diagram of the cross-sectional structure of the selector tube at the center line AA;

[0067] Figure 7 It is along Figure 5 A schematic diagram of the cross-sectional structure of the storage tube at the center line BB. Detailed Implementation

[0068] like Figure 4 The diagram shown is a circuit diagram of the OTP unit 201 of the memory in an embodiment of the present invention; the memory in this embodiment of the present invention includes a memory array composed of a plurality of OTP units 201.

[0069] The OTP unit 201 includes a select transistor 202 composed of NMOS transistors and a storage transistor 203 composed of PMOS transistors.

[0070] The source of the selector transistor 202 serves as the bit line terminal BL of the OTP unit 201.

[0071] The drain of the selector 202 is connected to the drain of the storage 203.

[0072] The source of the storage tube 203 serves as the source terminal SL of the OTP unit 201.

[0073] The gate 305 of the select transistor 202 serves as the select gate SG of the OTP unit 201, and the gate 308 of the storage transistor 203 is a floating gate.

[0074] like Figure 5 The diagram shown is a layout of the memory array of an embodiment of the present invention; the memory array includes an NMOS group 301 and a PMOS group 302.

[0075] Each of the selected transistors 202 is formed in the NMOS group 301.

[0076] Each of the aforementioned storage transistors 203 is formed in the PMOS group 302.

[0077] The programming voltage of the OTP unit 201 is greater than the power supply voltage, and the maximum voltage of the voltage domain of the NMOS group 301 is the power supply voltage; the maximum voltage of the voltage domain of the PMOS group 302 is the programming voltage.

[0078] In embodiments of the present invention, such as Figure 6 As shown, it is along Figure 5 A cross-sectional view of the selector at the center line AA; the NMOS group 301 is formed in a P-type semiconductor substrate 401. (Back) Figure 4 As shown, the P-type semiconductor substrate 401 is connected to the substrate electrode Psub, which serves as the back gate electrode of each of the select transistors 202.

[0079] like Figure 6 As shown, field oxygen 402 is also formed in the P-type semiconductor substrate 401, and the field oxygen 402 is typically shallow trench isolation (STI). Figure 6In the first active region 304 formed by the selector 202, the field oxygen 402 is formed on the periphery of the first active region 304, that is, the first active region 304 is composed of the P-type semiconductor substrate 401 between the field oxygen 402. Figure 5 The first active region 304 corresponding to the selection tube 202 is also shown in the image.

[0080] In this embodiment of the invention, the gate 305 of the select transistor 202 is made of polysilicon, and a first gate dielectric layer 404 is formed at the bottom of the gate 305. A first source-drain region 403a and a second source-drain region 403b are formed on both sides of the gate 305 of the select transistor 202. The first source-drain region 403a and the second source-drain region 403b of the select transistor 202 are symmetrically arranged. When the first source-drain region 403a is the source region of the select transistor 202, the second source-drain region 403b is the drain region of the select transistor 202, and vice versa. The electrode connected to the source region of the select transistor 202 is the source electrode, and the electrode connected to the drain region of the select transistor 202 is the drain electrode.

[0081] In some embodiments, the material of the first gate dielectric layer 404 includes an oxide layer.

[0082] In this embodiment of the invention, the PMOS group 302 is formed in an N-type well 306. For example... Figure 7 As shown, it is along Figure 5 A cross-sectional view of the memory cell at the center line BB; the N-type well 306 is located in the P-type semiconductor substrate 401; the N-type well 306 is connected to the N-well electrode NW, which serves as the back gate electrode of each memory cell 203.

[0083] In this embodiment of the invention, the gate 308 of the storage transistor 203 is made of polysilicon, and a second gate dielectric layer 405 is formed at the bottom of the gate 308 of the storage transistor 203.

[0084] A first source-drain region 406a and a second source-drain region 406b are formed on both sides of the gate 308 of the memory transistor 203. The first source-drain region 406a and the second source-drain region 406b of the memory transistor 203 are symmetrically arranged. When the first source-drain region 406a is the source region of the memory transistor 203, the second source-drain region 406b is the drain region of the memory transistor 203, and vice versa. The electrode connected to the source region of the memory transistor 203 is the source electrode, and the electrode connected to the drain region of the memory transistor 203 is the drain electrode.

[0085] In some embodiments, the material of the second gate dielectric layer 405 includes an oxide layer.

[0086] In embodiments of the present invention, such as Figure 5As shown, the NMOS group 301 includes a plurality of NMOS columns 303, and each NMOS column 303 includes a plurality of select transistors 202.

[0087] The gates 305 of each of the select transistors 202 in the same NMOS column 303 are connected together.

[0088] In the NMOS group 301, the select transistors 202 located in each of the NMOS columns 303 are arranged in multiple rows, and the select transistors 202 in the same row are aligned.

[0089] The PMOS group 302 includes a plurality of memory transistors 203, and the memory transistors 203 are arranged in multiple rows and columns.

[0090] In some embodiments, such as Figure 5 As shown, the PMOS group 302 is composed of multiple memory transistor assemblies 307. Each memory transistor assembly 307 includes two memory transistors 203. A contact hole 310 is formed in the middle region of the memory transistor assembly 307. The bottom of the contact hole 310 is connected to the N-type well 306, and the top of the contact hole 310 is connected to an electrode 311 composed of a front-side metal layer. The electrode 311 serves as the N-well electrode NW. Four symmetrically arranged P+ doped regions 309 are shown in the memory transistor assembly 307. Figure 7 The first source / drain region 406a and the second source / drain region 406b of the corresponding storage tube 203 are composed of the P+ doped region 309 at the corresponding positions.

[0091] The area of ​​the select transistor 202 is smaller than the area of ​​the storage transistor 203, and the area of ​​the NMOS group 301 is smaller than the area of ​​the PMOS group 302. For example... Figure 5 As shown, in the NMOS group 301, there are 32 select transistors 202 arranged in 8 columns × 4 rows. In the PMOS group 302, there are 16 memory transistor combinations 307 and 32 memory transistors 203. However, the area occupied by the NMOS group 301 is significantly smaller.

[0092] Each of the OTP units 201 is formed by connecting the select transistor 202 in the NMOS group 301 and the corresponding storage transistor 203 in the PMOS group 302. Figure 5 In the NMOS group 301, the drain of each select transistor 202 is connected to the drain of the corresponding storage transistor 203 in the PMOS group 302 via a metal interconnect. Figure 5 The diagram of the metal interconnects is not shown.

[0093] In the memory array, the gates 305 of the select transistors 202 of the OTP cells 201 in the same column are connected to the word lines in the same column.

[0094] The source of each of the select transistors 202 in the OTP unit 201 in the same row is connected to the bit line in the same row.

[0095] The source of the storage tube 203 in each of the OTP units 201 is connected to the source line.

[0096] During programming, the selected OTP unit 201 is the programming unit, and the voltage applied to the programming unit includes:

[0097] The voltage of the word line is the power supply voltage.

[0098] The voltage of the bit line is a first voltage, which is a positive voltage and less than the power supply voltage. In some embodiments, the first voltage is 0.3V.

[0099] The voltage of the source line is the programming voltage, and the voltage of the N-well electrode NW is the programming voltage.

[0100] During programming, the voltage of the word line of each unselected OTP unit 201 in a different column from the programming unit is 0V.

[0101] During programming, each non-selected OPT unit in a different column and row from the programming unit is a programming interference unit. The voltage of the substrate electrode Psub is lower than the first voltage to reduce leakage current of the selection transistor 202 of the programming interference unit, thereby reducing programming interference to the storage transistor 203 of the programming interference unit.

[0102] During reading, the voltage applied to the selected OTP unit 201 includes:

[0103] The voltage of the word line is the power supply voltage.

[0104] The voltage of the bit line is the power supply voltage minus the first bias voltage, the first bias voltage being the gate-source voltage of the select transistor 202, and the first bias voltage being greater than or equal to the threshold voltage of the select transistor 202 to ensure that the select transistor 202 is turned on.

[0105] The voltage of the source line is the power supply voltage, and the voltage of the N-well electrode NW is the power supply voltage.

[0106] Please refer to Table 3 for the voltages applied during the programming and reading processes described above.

[0107] Table 3

[0108]

[0109]

[0110] In Table 3, `read` represents a read operation on the selected OTP unit 201; `PGM` represents a programming operation on the programming unit; `PGM disturb` represents the voltage applied to the unselected OTP unit 201 (i.e., the programming interference unit) in the same row but different column as the programming unit during the programming operation; `VDD` represents the power supply voltage; `bias` represents the first bias voltage; `VPP` represents the programming voltage; and 0.3V is the first voltage. `SG` represents the selection gate of the corresponding OTP unit 201. Since `SG` is connected to the word line, its voltage also represents the voltage of the corresponding word line. `BL` represents the bit line terminal of the corresponding OTP unit 201. Since `BL` is connected to the corresponding bit line, its voltage also represents the voltage of the corresponding bit line. `SL` represents the source line terminal of the OTP unit 201. All source line terminals of the OTP units 201 are connected to the source line, so the voltage of `SL` also represents the voltage of the source line. `NW` represents the N-well electrode. All N-well electrodes of the OTP units 201 are connected together.

[0111] This embodiment of the invention first makes special arrangements for the OTP unit 201, using NMOS transistors for the select transistor 202 and PMOS transistors for the storage transistor 203; it also makes special arrangements for the storage array, placing all select transistors 202 in the NMOS group 301 and all storage transistors 203 in the PMOS group 302; this embodiment of the invention also uses the source of the select transistor 202 as the bit line terminal BL and the source of the storage transistor 203 as the source line terminal SL. This connection structure allows the maximum voltage of the select transistor 202 during read and write operations to be the power supply voltage, without bearing a large programming voltage. Since the size of the select transistor 202 needs to meet the withstand voltage requirements, the larger the operating voltage, the larger the size of the select transistor 202 needs to be, and vice versa. Therefore, the size of the select transistor 202 in this embodiment of the invention can be made smaller. When all select transistors 202 are placed in the NMOS group 301, the area of ​​the NMOS group 301 can be greatly reduced. At the same time, the area of ​​the decoder required for decoding the select gate SG, i.e., the word line, is also reduced, ultimately reducing the area of ​​the memory.

[0112] In this embodiment of the invention, since an NMOS transistor is used as the selection transistor 202, compared with a PMOS transistor, the back gate electrode of the selection transistor 202 and the back gate electrode of the storage transistor 203 can be set independently. In this way, by setting the voltage of the back gate electrode of the selection transistor 202, the leakage current of each selection transistor 202 in a different column from the programming unit can be greatly reduced during programming, thereby reducing programming interference.

[0113] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A memory, characterized in that, Includes a storage array composed of multiple OTP units; The OTP unit includes a select transistor composed of NMOS transistors and a storage transistor composed of PMOS transistors; The source of the select transistor serves as the bit line terminal of the OTP unit; The drain of the select transistor is connected to the drain of the storage transistor; The source of the storage tube serves as the source terminal of the OTP unit; The gate of the select transistor serves as the select gate of the OTP unit, and the gate of the storage transistor is a floating gate. The memory array includes an NMOS group and a PMOS group; Each of the aforementioned selection transistors is formed within the NMOS group; Each of the aforementioned memory transistors is formed within the PMOS group; The programming voltage of the OTP unit is greater than the power supply voltage, and the maximum voltage of the voltage domain of the NMOS group is the power supply voltage; the maximum voltage of the voltage domain of the PMOS group is the programming voltage.

2. The memory as claimed in claim 1, characterized in that: The NMOS group is formed in a P-type semiconductor substrate; the P-type semiconductor substrate is connected to a substrate electrode, which serves as the back gate electrode of each of the select transistors.

3. The memory as described in claim 2, characterized in that: The PMOS array is formed in an N-type well, which is located in the P-type semiconductor substrate; the N-type well is connected to an N-well electrode, which serves as the back gate electrode of each memory transistor.

4. The memory as described in claim 3, characterized in that: The NMOS group includes multiple NMOS columns, and each NMOS column includes multiple select transistors; The gates of the select transistors in the same NMOS column are connected together.

5. The memory as described in claim 4, characterized in that: In the NMOS group, the select transistors located in each NMOS column are arranged in multiple rows, and the select transistors in the same row are aligned.

6. The memory as claimed in claim 4, characterized in that: The PMOS group includes multiple memory transistors, which are arranged in multiple rows and columns.

7. The memory as claimed in claim 6, characterized in that: The area of ​​the select transistor is smaller than the area of ​​the storage transistor, and the area of ​​the NMOS group is smaller than the area of ​​the PMOS group.

8. The memory as claimed in claim 6, characterized in that: Each of the aforementioned OTP units is formed by connecting the select transistor in the NMOS group and the corresponding memory transistor in the PMOS group; In the memory array, the gates of the select transistors of the OTP cells in the same column are connected to the word lines of the same column; The sources of the select transistors in the OTP cells of the same row are connected to the bit lines of the same row; The source of the storage tube in each of the OTP units is connected to the source line.

9. The memory as claimed in claim 8, characterized in that: During programming, the selected OTP unit is the programming unit, and the voltage applied to the programming unit includes: The voltage of the word line is the power supply voltage; The voltage of the bit line is a first voltage, which is a positive voltage and less than the power supply voltage; The voltage of the source line is the programming voltage, and the voltage of the N-well electrode is the programming voltage.

10. The memory as claimed in claim 9, characterized in that: During programming, the voltage of the word line of each unselected OTP unit in a different column from the programming unit is 0V.

11. The memory as claimed in claim 8, characterized in that: During reading, the voltage applied to the selected OTP unit includes: The voltage of the word line is the power supply voltage; The voltage of the bit line is the power supply voltage minus the first bias voltage, the first bias voltage is the gate-source voltage of the select transistor, and the first bias voltage is greater than or equal to the threshold voltage of the select transistor to ensure that the select transistor is turned on. The voltage of the source line is the power supply voltage, and the voltage of the N-well electrode is the power supply voltage.

12. The memory as claimed in claim 7, characterized in that: The gate of the selector is made of polysilicon, and a first gate dielectric layer is formed at the bottom of the gate of the selector.

13. The memory as claimed in claim 12, characterized in that: The gate of the memory transistor is made of polysilicon, and a second gate dielectric layer is formed at the bottom of the gate of the memory transistor.

14. The memory as claimed in claim 13, characterized in that: The material of the first gate dielectric layer includes an oxide layer; The material of the second gate dielectric layer includes an oxide layer.

15. The memory as claimed in claim 10, characterized in that: During programming, each non-selected OTP unit in a different column and row from the programming unit is a programming interference unit; The voltage of the substrate electrode is less than the first voltage.

Images