A method for processing data loss caused by frequency offset in request-to-send satellite data transmission

Abstract

The application relates to a processing method for solving the problem of data loss caused by frequency deviation in satellite data transmission, belonging to the technical field of satellite communication. Two-channel request satellite two-channel modulators respectively send request frames to a data processor, and the request frames are combined and then output to a solid-state memory; the solid-state memory sends playback data corresponding to the number of single-channel data frames to the data processor according to the number of received request frames; the data processor divides the received single-channel playback data into two channels averagely, carries out data processing on the two channels respectively, and generates full identification signals; after the data processing is completed, the two-channel modulators are output according to the number of request frames; when the full identification signals of any one of the two channels are 1, the request frame combination is stopped, and at this time, the solid-state memory pauses the playback data. The application can solve the problem of data loss caused by the clock crystal oscillator frequency deviation of the modulator in satellite request data transmission in real time and reliably by detecting the capacity of the data cached in the internal buffer of the two-channel coding processing units in real time.

Description

Technical Field

[0001] This invention relates to a method for handling data loss caused by frequency offset in request-based satellite data transmission, belonging to the field of satellite communication technology, specifically to a method for handling data loss caused by crystal oscillator frequency offset in request-based satellite data transmission. Background Technology

[0002] In recent years, with the improvement of satellite camera resolution and the development of diverse payload types, the amount of satellite data has continued to increase. Compared with the massive increase in data, the satellite data transmission bandwidth is extremely limited. Therefore, how to improve the transmission efficiency of effective satellite data is a perpetual research problem.

[0003] To improve the efficiency of satellite data transmission, the following methods are commonly used: First, source coding, also known as data compression, aims to transmit the maximum amount of information with the least amount of data. Currently, satellite-based compression methods include ADPCM, JPEGLS, JPEG2000, H.265, etc. Second, preprocessing techniques aim to preprocess data before it is transmitted, reducing the amount of data transmitted. Currently, satellite-based preprocessing techniques include cloud detection, ship detection, and point target extraction, etc. Third, high-efficiency data transmission aims to maximize the utilization of effective bandwidth. Currently, satellite-based data transmission methods include traditional data transmission and request-based data transmission.

[0004] Traditional data transmission is sequential, starting from the generation of satellite payload data, through data storage and processing, then to the modulator, and finally to the channel. The drawback of this method is that, with limited bandwidth, the total data volume must be less than the channel capacity to prevent data overflow and loss; therefore, invalid data (empty frames) consume a certain amount of channel bandwidth. Request-based data transmission, a feedback-based method, sends request frames to the data processor whenever channel bandwidth allows. Upon receiving the request, the data processor, according to different operating modes, reads data from solid-state memory or the payload and sends it to the modulator in real time. This method maximizes the transmission of valid data, while the amount of invalid data (empty frames) is almost negligible.

[0005] In the dual-channel request-based satellite data transmission method, the two modulators operate independently, but the data processor and solid-state storage (SSD) are integrated. The data processor's encoding unit combines the dual-channel request frames into a single request frame and sends it to the SSD. The SSD, based on the request frame data content, replays the corresponding number of single-channel satellite data streams back to the data processor's encoding unit. The data processor's encoding unit then splits the replay data into two streams according to a certain rule, processes them separately, and sends them to modulator 1 and modulator 2 respectively, based on the number of request frames. When the dual-channel modulator request frames (clock crystal oscillators) have the same frequency, this transmission scheme works correctly. However, when the dual-channel modulator clock crystal oscillators experience frequency shifts in opposite directions, the number of dual-channel request frames changes over time. Since the SSD sends the corresponding number of satellite data streams based on the combined request frame content, and the satellite data lacks channel identifiers, the data processor's encoding unit can only divide the total data into two channels. After processing the two channels separately, the data is sent to the modulator based on the number of request frames for each channel. This process results in the loss of some satellite data. Summary of the Invention

[0006] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a method for handling data loss caused by frequency offset in request-based satellite data transmission. By real-time detection of the capacity of the data cached in the internal buffer of the two-channel encoding processing unit, the request frame combining signal is controlled to no longer be output to the solid-state memory, thus reliably solving the problem of data loss caused by modulator clock crystal frequency offset in satellite request-based data transmission.

[0007] The technical solution of the present invention is: Firstly, a data processor for preventing data loss due to frequency offset in requested satellite data transmission, comprising:

[0008] The request frame combining unit receives the full flag signal and the request frames sent by the two-channel modulators when the dual-channel request satellite transmits data, and performs request frame combining. If and only if the received full flag signal is 0, the combined request frame is output to the external solid-state memory.

[0009] The data splitting unit receives the single-channel playback data of the corresponding number of data frames sent by the external solid-state memory according to the number of frames of the combining request frame, and divides the single-channel playback data into two equal channels, which are then sent to the encoding processing units corresponding to the two-channel modulators respectively.

[0010] The encoding processing unit has several corresponding to the modulator channels. It is used to process the received single-channel playback data. After the data processing is completed, it outputs the request frame number to the corresponding channel modulator according to the corresponding channel. It also generates a full flag signal according to the amount of buffered data monitored in real time during data processing and sends the full flag signal to the request frame combining unit. When the amount of buffered data exceeds the preset threshold of the total buffer capacity, the full flag signal is set to 1; otherwise, it is set to 0.

[0011] Furthermore, the encoding processing unit includes a dual-port RAM buffer. After completing data processing, the data is stored in the dual-port RAM buffer. The amount of data output by the buffer is determined in real time by the modulator request frame number.

[0012] Secondly, a method for handling data loss caused by frequency offset in request-based satellite data transmission using the aforementioned data processor includes:

[0013] During dual-channel request-based satellite data transmission, the two channel modulators send request frames to the data processor, which then outputs the combined request frames to the solid-state storage. The solid-state storage, based on the number of received request frames, sends playback data for the corresponding number of data frames to the data processor. The data processor divides the received playback data into two equal streams, processes them separately, and generates a full flag signal based on the amount of buffered data processed in real-time monitoring. After processing, the data processor outputs the data to the corresponding channel modulator based on the number of request frames for that stream. When the amount of buffered data exceeds a preset threshold of the total buffer capacity, the full flag signal is set to 1; otherwise, it is set to 0. When the full flag signal of either channel is 1, request frame combining and output stops, and the solid-state storage pauses playback.

[0014] Furthermore, if the full flag signal becomes 1 while the merge request frame is being output, the full flag signal is delayed until the entire request frame is output to the solid-state memory.

[0015] Furthermore, the step of dividing the single-channel playback data into two channels includes: allocating the first to Nth frames of the input single-channel solid-state memory playback data to the first channel, allocating the (N+1)-2Nth frames to the second channel, and so on, to divide the data into two channels for data processing, where N is the number of requested frames.

[0016] Furthermore, after the encoding processing unit corresponding to each channel completes the data processing, it writes the data to the dual-port RAM buffer. Each time a modulator request frame is received, the data of the request frame number is read from the dual-port RAM and given to the corresponding modulator. When the amount of data in the dual-port RAM buffer exceeds 60% of the total buffer capacity, the full flag signal is set to 1, otherwise the full flag signal is 0.

[0017] Furthermore, if the number of valid data frames stored in the dual-port RAM buffer is less than the number of requested frames, then the buffer is filled with the corresponding number of empty frame data.

[0018] Furthermore, the method of dividing the single playback data into two channels is to divide it into two channels in a ping-pong format according to the number of requested frames.

[0019] Thirdly, a computer-readable storage medium storing a computer program, characterized in that, when executed by a processor, the computer program implements the steps of the method for handling data loss caused by frequency offset in requested satellite data transmission.

[0020] Fourthly, a processing device for data loss caused by frequency offset in requested satellite data transmission includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: when the processor executes the computer program, it implements the steps of the processing method for data loss caused by frequency offset in requested satellite data transmission.

[0021] The advantages of this invention compared to the prior art are:

[0022] (1) The characteristic of the request-based satellite data transmission of the present invention is that it is a feedback-type data transmission. As long as the channel bandwidth allows, the modulator sends a request frame to the data processor. After receiving the request instruction, the data processor reads data from the solid-state memory or payload according to different working modes and sends it to the modulator in real time. Compared with the traditional satellite data transmission scheme, this request-based transmission scheme can utilize the satellite channel bandwidth more efficiently and transmit effective data.

[0023] (2) The present invention provides a method for handling data loss caused by frequency offset in request-based satellite data transmission. This method is simple, feasible, and reliable in real time, and solves the problem of data loss caused by frequency offset of modulator clock crystal in dual-channel request-based satellite data transmission. Attached Figure Description

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0025] Figure 1 This is a block diagram illustrating the principle of a method for handling data loss caused by frequency offset in satellite data transmission.

[0026] Figure 2 This is a diagram illustrating the request frame format.

[0027] Figure 3 This is a block diagram illustrating the principle of request frame combining.

[0028] Figure 4 This is a block diagram illustrating the ping-pong splitting principle of playback data in frame-by-frame format. Detailed Implementation

[0029] To better understand the above technical solutions, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present invention, rather than limitations on the technical solutions of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0030] The following description, in conjunction with the accompanying drawings, provides a more detailed explanation of a method for handling data loss caused by frequency offset in request-based satellite data transmission, as provided in an embodiment of the present invention. Figure 1 Specific implementation methods may include:

[0031] Step A: Dual-channel request-based satellite data transmission scheme. Modulators 1 and 2 each send request frames to the data processor. The data processor combines the two request frames into a single request frame signal according to the frame format and sends it to the solid-state storage. The solid-state storage sends the corresponding number of onboard data frames to the data processor based on the number of received request frames. The data processor ping-pong splits the received single-channel solid-state storage playback data into two channels according to the request frame number format. After completing the data processing functions for each channel, each channel outputs to modulators 1 and 2 according to its own request frame number.

[0032] Step B: When the full flag is '0', combine the request frame signals of modulator 1 and modulator 2 and output them to the solid-state memory; when the full flag is '1', neither the request frame signals of modulator 1 nor modulator 2 will be output; if the full flag changes to '1' while the combined request frame is being output, the full flag needs to be delayed until the entire content of the request frame is output to the solid-state memory.

[0033] Step C: The solid-state storage replays single-channel data. The data processor ping-pong splits the data into two channels according to the format of the requested frame number and outputs it to two encoding processing units. If the number of frames requested each time is N, then the 1st to Nth frames are assigned to the first channel, the (N+1)th to 2Nth frames are assigned to the second channel, the (2N+1)th to 3Nth frames are assigned to the first channel, the (3N+1)th to 4Nth frames are assigned to the second channel, and so on, ping-pong splitting the data into two channels and outputting it to two encoding processing units.

[0034] Step D: After each encoding processing unit completes the encoding function, it stores the data in the dual-port RAM buffer. Each time a modulator request frame is received, the data of the request frame number is read from the dual-port RAM and sent to the corresponding modulator. When the data in the RAM buffer exceeds 60% of the total buffer capacity, a full flag signal of '1' is generated; otherwise, the full flag signal of '0' is generated.

[0035] Step E: Perform an OR operation on the two full flag signals and output a full flag signal to the request frame combining unit; when either of the full flag signals is '1', the request frame combining signal will no longer be output to the solid-state memory until both full flag signals are '0', then the request frame combining signal will continue to be sent to the solid-state memory.

[0036] In the solution provided by the embodiments of the present invention, a method for handling data loss caused by frequency offset in requested satellite data transmission is shown in the schematic diagram below. Figure 1 The steps include the following:

[0037] Step A:

[0038] Dual-channel modulator 1 and modulator 2 separately send request frames to the data processor; the request frame format is as follows: Figure 2 As shown, the request frame data has a bit width of 16 bits and a frame length of 512 clock cycles. The fifth byte of the request frame data is the request frame number N.

[0039] Step B:

[0040] (1) The data processor combines the two request frames into one, such as Figure 3 As shown; the shortest retrace time of the request frame is (N-1) times the forward time, so the two request frames have a sufficiently long retrace time to be combined according to the frame format; the two request frames are combined according to the first one to arrive, and if they arrive at the same time, the modulator 1 request frame is output first.

[0041] (2) When the full flag signal is '0', a request frame combining signal is output to the solid-state memory; when the full flag signal is '1', no request frame combining signal is output. If a request frame signal is being output when the full flag signal becomes '1', the full flag signal is delayed until the current request frame content is completely output, such as... Figure 3 As shown.

[0042] Step C: Each time the solid-state storage receives a request frame, it replays N frames of data to the data processor.

[0043] Step D: The data processor receives playback data from a single-channel solid-state memory and ping-pong-dives the data into two channels according to an N-frame format, outputting them to two encoding processing units, such as... Figure 4 As shown;

[0044] Step E:

[0045] (1) As shown in the code below, after the two encoding processing units receive the data, they perform encoding processing respectively, and then write the data into the internal buffer dual-port RAM1 and dual-port RAM2.

[0046] If (WR_cnt=B<N)=> Read valid data from frame B (B≥0) from RAM, fill empty frames NB, and set the full flag FULL=0; Elsif(N≤WR_cnt)<NUM×60%)=> Read N frames of valid data from RAM, and set the full flag FULL=0;

[0047] Else(WR_cnt≥NUM×60%) => Read N frames of valid data from RAM, set FULL flag to 1;

[0048] End if;

[0049] Where: Wcnt: number of RAM write frames; Rcnt: number of RAM read frames; WR_cnt = Wcnt - Rcnt; NUM: number of full RAM frames; B: number of RAM data frames remaining; N: number of requested frames; FULL: full flag;

[0050] (2) Encoding processing unit 1 reads N frames of data from dual-port RAM1 each time it receives a request frame from modulator 1. If the RAM is less than N frames, it fills in empty frames and sends them to modulator 1. Encoding processing unit 2 reads N frames of data from dual-port RAM2 each time it receives a request frame from modulator 2. If the RAM is less than N frames, it fills in empty frames and sends them to modulator 2.

[0051] (3) When the amount of data in the data frame stored in the dual-port RAM1 is greater than 60% of the total capacity, the full flag 1 signal is '1', otherwise it is '0'; when the amount of data in the data frame stored in the dual-port RAM2 is greater than 60% of the total capacity, the full flag 2 signal is '1', otherwise it is '0'.

[0052] Step F: When either the full indicator 1 signal or the full indicator 2 signal becomes '1', the full indicator signal is '1'; otherwise, it is '0'.

[0053] Example 1

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the following detailed description, in conjunction with embodiments, details a method for handling data loss caused by frequency offset in requested satellite data transmission, providing a further detailed explanation of the invention. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0055] Step A:

[0056] (1) Dual-channel modulator 1 and modulator 2 separately send request frames to the data processor; request frames

[0057] Frame format such as Figure 2 As shown, the request frame data has a width of 16 bits, a frame length of 512 clock cycles, a frame synchronization header of "1ACFFC1D", specific data of "441F + frame counter (23~0) + "00", a request end address of "B1", a response end address of "C2", a request frame counter of "0000", a request frame number of "08", a reserved "00", a CRC check bit (CRC check bit position from the fifth byte to the 16th byte), and other bytes are filled with "00".

[0058] (2) The hardware interface of the data processor and modulator is the 2711 chip with a clock frequency of 100MHz. The 2711 bus software interface protocol is detailed in the public information and will not be described in detail in this article.

[0059] Step B:

[0060] (1) The data processor combines the two request frames into one, such as Figure 3 As shown; the shortest retrace time of the request frame is 7 times the forward time, so the two request frames have a long enough retrace time to be combined according to the frame format; the two request frames are combined according to the first one to arrive, and if they arrive at the same time, the modulator 1 request frame is output first.

[0061] (2) When the full flag signal is '0', a request frame combining signal is output to the solid-state memory; when the full flag signal is '1', no request frame combining signal is output. If a request frame signal is being output when the full flag signal becomes '1', the full flag signal is delayed until the current request frame content is completely output, such as... Figure 3 As shown.

[0062] (3) The data processor and solid-state storage use the GTX bus interface with a clock frequency of 125MHz. For details of the GTX bus interface protocol, please refer to the public information. This article will not describe it in detail.

[0063] Step C: For each request frame received, the solid-state storage replays 8 frames of data to the data processor.

[0064] Step D: The data processor receives the playback data from the solid-state memory and ping-pong splits the data into two paths according to the 8-frame format, outputting them to two encoding processing units, such as... Figure 4 As shown;

[0065] Step E:

[0066] (1) As shown in the code below, after the two encoding processing units receive the data, they perform encoding processing respectively, and then write the data into the internal buffer dual-port RAM1 and dual-port RAM2, where the total number of frames buffered by dual-port RAM is 128.

[0067] If (WR_cnt = B < 8) => Read B (B ≥ 0) frames of valid data from RAM, fill with 8 - B empty frames, and set the full flag FULL = 0; Elsif (8 ≤ WR_cnt < 80) => Read 8 frames of valid data from RAM, and set the full flag FULL = 0;

[0068] Else(WR_cnt≥80) => Read 8 frames of valid data from RAM, set the full flag FULL=1;

[0069] End if;

[0070] Where: Wcnt: number of RAM write frames; Rcnt: number of RAM read frames; WR_cnt = Wcnt - Rcnt; NUM: RAM full frame count is 128; B: number of RAM remaining data frames; N: number of requested frame bits (8); FULL: full flag;

[0071] (2) Encoding processing unit 1 reads 8 frames of data from dual-port RAM1 each time it receives a request frame from modulator 1. If the RAM is less than 8 frames, it fills in empty frames and sends them to modulator 1. Encoding processing unit 2 reads 8 frames of data from dual-port RAM2 each time it receives a request frame from modulator 2. If the RAM is less than 8 frames, it fills in empty frames and sends them to modulator 2.

[0072] (3) When the number of data frames stored in dual-port RAM1 is greater than 80, the full indicator 1 signal is '1', otherwise it is '0'; when the number of data frames stored in dual-port RAM2 is greater than 80, the full indicator 2 signal is '1', otherwise it is '0'.

[0073] Step F: When either the full indicator 1 signal or the full indicator 2 signal becomes '1', the full indicator signal is '1'; otherwise, it is '0'.

[0074] This invention provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform... Figure 1 The method described.

[0075] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0076] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0077] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0078] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0079] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0080] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A data processor for preventing data loss due to frequency offset in requested satellite data transmission, characterized in that, include: The request frame combining unit receives the full flag signal and the request frames sent by the two-channel modulators when the dual-channel request satellite transmits data, and performs request frame combining. If and only if the received full flag signal is 0, the combined request frame is output to the external solid-state memory. The data splitting unit receives the single-channel playback data of the corresponding number of data frames sent by the external solid-state memory according to the number of frames of the combining request frame, and divides the single-channel playback data into two equal channels, which are then sent to the encoding processing units corresponding to the two-channel modulators respectively. The encoding processing unit has several corresponding to the modulator channels. It is used to process the received single-channel playback data. After the data processing is completed, it outputs the request frame number to the corresponding channel modulator according to the corresponding channel. It also generates a full flag signal according to the amount of buffered data monitored in real time during data processing and sends the full flag signal to the request frame combining unit. When the amount of buffered data exceeds the preset threshold of the total buffer capacity, the full flag signal is set to 1; otherwise, it is set to 0.

2. The data processor according to claim 1, characterized in that, The encoding processing unit includes a dual-port RAM buffer. After completing data processing, the data is stored in the dual-port RAM buffer. The amount of data output by the buffer is determined in real time by the modulator request frame number.

3. A method for handling data loss caused by frequency offset in request-based satellite data transmission implemented using the data processor described in claim 1 or 2, characterized in that, include: During dual-channel request-based satellite data transmission, the two channel modulators send request frames to the data processor respectively. The data processor combines the request frames and outputs them to the solid-state memory. The solid-state storage (SSD) sends playback data of the corresponding number of data frames to the data processor based on the number of frames of the received request frames. The data processor divides the received single-channel playback data into two equal channels, processes the data separately, and generates a full flag signal based on the amount of buffered data processed in real time. After completing the data processing, it outputs the data to the corresponding channel modulator based on the number of frames of the request frames in this channel. When the amount of buffered data exceeds a preset threshold of the total buffer capacity, the full flag signal is set to 1; otherwise, it is set to 0. When the full flag signal of either channel is 1, the request frame combining output stops, and the SSD pauses playback data.

4. The method for handling data loss caused by frequency offset in requested satellite data transmission according to claim 3, characterized in that, If the full flag signal becomes 1 while the merge request frame is being output, the full flag signal is delayed until the entire request frame is output to the solid-state memory.

5. The method for handling data loss caused by frequency offset in requested satellite data transmission according to claim 3, characterized in that, The step of dividing the single-channel playback data into two channels includes: dividing the input single-channel solid-state memory playback data into two channels, assigning the first to N frames to the first channel, assigning the (N+1)-2N frames to the second channel, and so on, and then dividing the data into two channels for data processing, where N is the number of requested frames.

6. The method for handling data loss caused by frequency offset in requested satellite data transmission according to claim 3, characterized in that, After the encoding processing unit corresponding to each channel completes the data processing, it writes the data to the dual-port RAM buffer. Each time a modulator request frame is received, the frame number of the request frame is read from the dual-port RAM and sent to the corresponding modulator. When the amount of data in the dual-port RAM cache exceeds 60% of the total cache capacity, the full flag signal is set to 1; otherwise, the full flag signal is set to 0.

7. The method for handling data loss caused by frequency offset in requested satellite data transmission according to claim 6, characterized in that, If the number of valid data frames stored in the dual-port RAM buffer is less than the number of requested frames, then fill the buffer with the corresponding number of empty frames.

8. The method for handling data loss caused by frequency offset in requested satellite data transmission according to claim 3, characterized in that, The method for dividing single-channel playback data into two channels is to divide it into two channels in a ping-pong format according to the number of requested frames.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 3 to 8.

10. A processing device for data loss caused by frequency offset in requested satellite data transmission, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements the steps of the method as described in any one of claims 3 to 8.

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