Message processing method of cxl protocol link layer, electronic device and program product

Abstract

The message processing method of the cxl protocol link layer provided in the embodiments of the present disclosure comprises: acquiring a flit transmission message of a link layer; determining a message type contained in the flit transmission message; the message type comprises a first type of message and / or a second type of message; the first type of message comprises a message header and data; the second type of message only comprises a message header; in response to the flit transmission message comprising the first type of message and the second type of message, the first type of message is preferentially processed; and the second type of message is processed based on the processing result of the first type of message. Through the embodiment scheme, a general and efficient cxl protocol link layer data analysis and packet assembly method is provided, the development cost and the maintenance cost are reduced, the implementation complexity of the hardware circuit is effectively reduced, the hardware resource consumption is reduced, the portability and the reusability are strong, and the expansibility is good.

Description

Technical Field

[0001] This disclosure relates to the field of interconnection technology, such as CPUs and servers, and particularly to a message processing method, electronic device, and program product for the CXL protocol link layer. Background Technology

[0002] In versions 1.0 and 2.0 of the CXL (Compute Express Link) protocol, the link layer only had a 68-bit flit (link transmission unit) format. However, starting from version 3.0, the link layer added a 256-bit Standard flit format and a 256-bit Latency-Optimized flit format. This means that the link layer needs to be able to support the processing of three different flit formats simultaneously, and the three flit formats are quite different.

[0003] Traditional enumeration methods require listing all flit formats to perform packet assembly and disassembly. However, since CXL 3.0, there can be thousands of combinations of various protocol messages and flit formats, and listing them all would lead to enormous complexity and resource consumption. Therefore, optimizing CXL link layer data parsing and packet assembly processing, and providing an efficient link layer packet assembly and disassembly method suitable for cxl.cache and cxl.mem, while also considering ease of hardware implementation and resource conservation, is a technical problem that needs to be solved by those in the field. Summary of the Invention

[0004] This disclosure provides a message processing method, electronic device, and program product for the CXL protocol link layer.

[0005] In a first aspect, embodiments of this disclosure provide a message processing method for the CXL protocol link layer, comprising:

[0006] Obtain the link layer transmission unit (flit) transmission message;

[0007] Determine the message type contained in the flit transmission message; the message type includes a first type of message and / or a second type of message; the first type of message includes a message header and data; the second type of message includes only a message header.

[0008] Since the flit transmission message includes both the first type of message and the second type of message, the first type of message is processed first.

[0009] The second type of message is processed based on the processing result of the first type of message.

[0010] Secondly, embodiments of this disclosure also provide an electronic device, including:

[0011] One or more processors;

[0012] A memory that stores one or more programs, which, when executed by one or more processors, enable the one or more processors to implement the message processing method of the cxl protocol link layer;

[0013] One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

[0014] Thirdly, this disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements the message processing method of the cxl protocol link layer.

[0015] This embodiment of the scheme obtains the link layer transmission unit (flit) transmission message; determines the message type contained in the flit transmission message; the message type includes a first type of message and / or a second type of message; the first type of message includes a message header and data; the second type of message only includes a message header; in response to the flit transmission message including both the first and second types of messages, the first type of message is processed first; the second type of message is processed based on the processing result of the first type of message. This embodiment provides a general and efficient method for parsing and assembling link layer data in the CXL protocol, reducing development and maintenance costs, effectively reducing the implementation complexity of hardware circuits, reducing hardware resource consumption, exhibiting strong portability and reusability, and possessing good scalability. Attached Figure Description

[0016] In the accompanying drawings of the embodiments disclosed herein:

[0017] Figure 1 A flowchart of a message processing method provided in an embodiment of this disclosure;

[0018] Figure 2 This is a schematic diagram of the analytical processing provided in the embodiments of this disclosure;

[0019] Figure 3 A flowchart of a method for prioritizing the parsing of a first type of message provided in an embodiment of this disclosure;

[0020] Figure 4 This is a schematic diagram illustrating a method for calculating the first data volume based on flit fragmentation, as provided in an embodiment of this disclosure.

[0021] Figure 5A flowchart illustrating a method for prioritizing the parsing of first-type messages when the message headers of multiple first-type messages are in the same slot, as provided in this embodiment of the disclosure.

[0022] Figure 6 A schematic diagram illustrating the process of aligning message headers and corresponding data according to embodiments of this disclosure;

[0023] Figure 7 This is a schematic diagram of a package assembly method provided in an embodiment of the present disclosure;

[0024] Figure 8 A flowchart illustrating a method for reading the message collection queue according to the initial message priority set by the system and the backpressure of the next-level module, provided in an embodiment of this disclosure;

[0025] Figure 9 A flowchart of the packaging method provided in this embodiment of the disclosure;

[0026] Figure 10 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this disclosure, the communication-sensing data processing method and computer-readable storage medium provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0028] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0029] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0030] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0031] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0032] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0034] The CXL (Compute Express Link) protocol defines a series of interconnects between hosts and devices and is an open industry standard. As a new open interconnect technology standard, CXL enables high-speed and efficient interconnects between CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), or other accelerators, thereby meeting the requirements of high-performance heterogeneous computing and maintaining consistency between host memory space and connected device memory.

[0035] The CXL protocol is based on PCIe (Peripheral Component Interconnect Express) and runs on the PCIe physical layer. It shares the same electrical characteristics as PCIe, and CXL devices can be plugged into PCIe slots. The underlying layer negotiates whether to use the PCIe or CXL protocol. The CXL protocol defines three sub-protocols: cxl.io, cxl.cache, and cxl.mem. cxl.io is used for initialization, linking, device discovery and enumeration, and register access. cxl.cache defines the interaction between the host and the device, allowing connected CXL devices to cache host memory efficiently and with low latency using request and response methods. cxl.mem provides the host with access to the memory of the device using load and store commands and supports both volatile and persistent memory architectures. cxl.cache and cxl.mem share a common link and transaction layer, while cxl.io has its own.

[0036] The CXL protocol has now evolved to version 3.1. The `cxl.cache` file contains six protocol messages: H2D req (Host to Device req), H2D rsp (Host to Device rsp), H2D data (Host to Device data), D2Hreq (Device to Host req), D2H rsp (Device to Host rsp), and D2H data (Device to Host data). The `cxl.mem` file contains six protocol messages: M2S req (Master-to-Subordinate Request), M2S rwd (Master-to-Subordinate Request with Data), and M2S birsp (Master-to-Subordinate Back-Invalidate). Response (a message from the master device to the slave device to revoke an invalid response), S2M ndr (Subordinate-to-Master No Data Response, a message from the slave device to the master device without data), S2M drs (Subordinate-to-Master Data Response, a response message from the slave device to the master device), S2M bisnp. Meanwhile, the CXL protocol specifies that data in cxl.cache and cxl.mem at the link layer is transmitted in flit (link transmission unit) format, with three flit formats: 68B (68 bytes) flit, 256B Standard flit, and 256B (256 bytes) Latency-Optimized flit.

[0037] Traditional enumeration methods require listing all flit formats to perform packet assembly and disassembly. However, since CXL 3.0, there can be thousands of combinations of various protocol messages and flit formats, and listing them all would lead to enormous complexity and resource consumption. Therefore, optimizing CXL link layer data parsing and packet assembly processing, and providing an efficient link layer packet assembly and disassembly method suitable for cxl.cache and cxl.mem, while also considering ease of hardware implementation and resource conservation, is a technical problem that needs to be solved by those in the field.

[0038] This embodiment of the scheme obtains the link layer transmission unit (flit) transmission message; determines the message type contained in the flit transmission message; the message type includes a first type of message and / or a second type of message; the first type of message includes a message header and data; the second type of message only includes a message header; in response to the flit transmission message including both the first and second types of messages, the first type of message is processed first; the second type of message is processed based on the processing result of the first type of message. This embodiment provides a general and efficient method for parsing and assembling link layer data in the CXL protocol, reducing development and maintenance costs, effectively reducing the implementation complexity of hardware circuits, reducing hardware resource consumption, and exhibiting strong portability, reusability, and good scalability.

[0039] The solutions disclosed herein can be applied to any processor with data and message processing functions, such as CPU (Central Processing Unit / Processor), FPGA (Field-Programmable Gate Array), etc., and can be applied to processors of host devices, slave devices, etc.

[0040] The embodiments of this disclosure will be described in detail below.

[0041] This disclosure provides a message processing method for the CXL protocol link layer, such as... Figure 1 As shown, it includes steps S11-S14:

[0042] S11. Obtain the link layer transmission unit flit transmission message.

[0043] S12. Determine the message type contained in the flit transmission message; the message type includes a first type of message and / or a second type of message; the first type of message includes a message header and data; the second type of message includes only a message header.

[0044] S13. In response to the flit transmission message, which includes a first type of message and a second type of message, the first type of message is processed first.

[0045] S14. Process the second type of message based on the processing result of the first type of message.

[0046] In this embodiment of the disclosure, the method for processing the flit transmission message includes a message processing method during message parsing and a message processing method during message packet assembly. The two processing methods are described below.

[0047] In this embodiment of the disclosure, the message processing method during the message parsing process of the flit transmission message in the host uplink layer receiving direction is first described. For example... Figure 2 The diagram shown is a schematic representation of the analytical processing in an embodiment of this disclosure.

[0048] In this embodiment of the disclosure, a flit transmission message can be received from an upstream module (such as a parent module) and parsed. Before parsing the flit transmission message, the flit transmission message is first verified.

[0049] In this embodiment, the CXL protocol uses the PCIe (Peripheral Component Interconnect Express) physical layer to transmit messages. After the PCIe connection is established at the bottom layer, the received message needs to be verified. According to the protocol, regardless of the FLT format, the FLT transmission message will contain cyclic redundancy check (CRC) content. The CRC information specified by the CXL protocol can be used to verify the validity of the data. Only after the CRC verification is correct will the FLT transmission message be passed to the next level module for further parsing. If the CRC verification fails, the current FLT transmission message will be discarded and a retransmission operation will be initiated to the peer.

[0050] In this embodiment of the disclosure, the CXL protocol contains multiple message types, including, but not limited to, a first type of message and a second type of message. The first type of message includes a message header and data; the second type of message only includes a message header. Since the message header of the first type of message is followed by data (or simply data), it is necessary to first determine the boundary between these two message types to avoid misidentifying the following data as the message header of other message types, and to distinguish whether the first type of message is included from among the various message types.

[0051] In this embodiment of the disclosure, for example, the first type of message may include two link layer messages with data, namely D2H data and S2M drs.

[0052] In this embodiment of the disclosure, determining the message type contained in the flit transmission message may include:

[0053] The slot type of the flit transmission message is determined based on the message header of the flit transmission message;

[0054] The type of message contained in the flit transmission message is determined based on the slot type.

[0055] In this embodiment of the disclosure, the flit transmission message after CRC verification can enter the link layer flit parsing module for parsing. The CXL protocol stipulates that a flit transmission message is divided into multiple slots (slots, components of a flit, used to structurally carry different types of data or control information). The flit header carries a slot type description. The flit format used for transmission in the current system can be determined according to the system configuration. Then, the slot type contained in the flit can be determined according to the flit header. Based on the slot type, it can be preferentially determined whether the flit carries the first type of message (e.g., D2H data and / or S2M drs message).

[0056] In this embodiment of the disclosure, if the flit transmission message contains the first type of message, the first type of message is parsed first.

[0057] In this embodiment of the disclosure, for example, priority is given to parsing and extracting data from D2H data (Host to Device data) and S2M drs (Subordinate-to-Master Data Response) messages. In the CXL protocol, both D2H data and S2M drs messages consist of two parts: a message header and the data following the header. Other types of messages only contain a message header; therefore, D2H data and S2M drs messages are processed first.

[0058] In the embodiments disclosed herein, such as Figure 3 As shown, the first type of message is processed first, which may include steps S21-S23:

[0059] S21. Determine the processing cycle of the first type of message based on the bit width of the first type of message.

[0060] S22. Extract data within each processing cycle based on the processing cycle, and determine the first data volume of the parsed data within each processing cycle; the first data volume may include, but is not limited to: total data volume, newly generated data volume, and remaining data volume.

[0061] S23. Based on the first data volume of data parsed throughout the entire processing cycle, determine the end time and / or end position of the first type of message parsing.

[0062] In this embodiment of the disclosure, if the flit transmission message contains the first type of message, then the subsequent slot transmission is the data (or data) corresponding to the message header. This data can be input into the real-time computing module to calculate the first data volume (the first data volume may include, but is not limited to: total data, newly generated data volume, and remaining data volume). Based on the calculation result, data extraction is performed, and the end time and / or end position of the first type of message are determined.

[0063] In this embodiment of the disclosure, for example, the flit transmission message received by the host side is in 256B standard format, transmitting two S2M drs messages and one D2H data message. The message header of the S2M drs is located in the first slot of the first flit, followed by the data corresponding to the message header. The D2H data message is transmitted later. The parsing method of the flit transmission message is as follows.

[0064] In this embodiment, the host sends the CRC-verified flit transmission message to the link layer flit parsing module for parsing. The overall parsing process includes: determining the type and number of data in each slot of the flit. According to the CXL protocol, the first 4 bits of each slot of the 256B flit transmission message carry message type information. In this embodiment, the type of the first slot receiving the flit transmission message is determined to be an S2M drs message, and the number of S2M drs message headers is 2. Thus, starting from the second slot of the current flit, the subsequent transmissions are the data corresponding to the message headers of the two S2M drs.

[0065] In this embodiment of the disclosure, the data corresponding to the message header of the S2M drs can be input into the real-time calculation module to calculate a first data volume. This first data volume may include, but is not limited to, at least one of the following: the total amount of data corresponding to the message header of the S2M drs, the newly generated data volume, the remaining data volume, and the amount of data to be extracted from the current S2M drs. Based on the first data volume, data extraction can be performed, and the end time and / or end position of the 2M drs message can be determined.

[0066] In the embodiments disclosed herein, the same method can be used to determine the end time and / or end position of the D2H data message.

[0067] In the embodiments disclosed herein, the parsing process of the 256B standard flit (i.e., flit transmission message) S2Mdrs message is described in detail below.

[0068] In this embodiment of the disclosure, the data processing bit width of the parsing module on the host side is 64B. Therefore, a 256B standard flit (i.e., a flit transmission message) requires 4 clock cycles to transmit. Each clock cycle transmits 1 flit fragment. Each flit fragment contains 4 slots, and each slot is 16B. A flit fragment counter can be set, and the count value of the counter cycles from 0 to 3 to determine which 64B part (i.e., which flit fragment) in the 256B flit is in the current clock cycle.

[0069] In this embodiment of the disclosure, the first slot in the flit transmission message received by the parsing module contains two S2M drs message headers. Subsequent slots transmit two sets of data corresponding to the two message headers, each set of data being 64B in size. Therefore, in the first clock cycle, the total data volume parameter S0 is calculated to be 128B, the newly generated data volume parameter S1 is 128B, the remaining total data volume parameter S2 is 128B, and the data volume parameter S3 to be extracted in the current flit fragment is 48B.

[0070] In this embodiment of the disclosure, based on the above information, it can be determined that a 64B data corresponding to the message header cannot be collected in the first clock cycle. Therefore, in the first clock cycle, only the message header can be extracted from the first flit fragment, without extracting the corresponding data. In the second clock cycle, when the current data plus the data from the previous clock cycle can collect a 64-byte data set, this data corresponds to the first S2M DRSS message header. Therefore, in the second clock cycle, a 64-byte data set is extracted from the first and second flit fragments. At this time, the parameter values ​​are calculated and updated. The parameter changes in the second clock cycle are: S0 = 64 bytes, S1 = 0 bytes, S2 = 64 bytes, and S3 = 16 bytes. Similarly, in the third clock cycle, the current data plus the data from the previous clock cycle can collect a 64-byte data set. Therefore, in the third clock cycle, a 64-byte data set corresponding to the second S2M DRSS message header is extracted from the second and third flit fragments. The parameter values ​​are calculated and updated. The parameter changes in the third clock cycle are: S0 = 0 bytes, S1 = 0 bytes, S2 = 0 bytes, and S3 = 16 bytes. Since parameters S0 and S2 both become 0 at this time, it indicates that the two S2M DRSS messages have been updated. The drs message header and corresponding data have been extracted. Combining this with the value of parameter S3 (the amount of data to be extracted), we can determine the end time and / or end position of the S2M drs message. The parsed end position is the first slot in the third flit. Therefore, a new round of message type determination begins from the second slot of the third flit. For example... Figure 4 The diagram shown illustrates a method for calculating the first data volume based on flit partitioning.

[0071] In this embodiment of the disclosure, the second slot in the third flit slice carries a D2H data message header, followed by a corresponding 64B data. Therefore, in the third clock cycle, the parameters are finally updated to S0 as 64B, S1 as 64B, S2 as 64B, and S3 as 32B.

[0072] In this embodiment of the disclosure, since the end boundary (end time and / or end position) of the S2M drs message has been known in the aforementioned steps, the message type and number of valid messages contained in each subsequent slot are determined sequentially from the end boundary. If it is a D2H data message, the parameter values ​​of each data volume are calculated and updated in the previous S2M drs processing, and the message header and corresponding data are extracted. The processing is similar and will not be described in detail here.

[0073] In the embodiments disclosed herein, such as Figure 5 As shown, the first type of message is processed first, and may also include steps S31-S33:

[0074] S31. In response to multiple Class 1 messages having message headers in the same slot, parse the data of the multiple Class 1 messages after parsing the message headers of the multiple Class 1 messages first.

[0075] S32. Align the parsed message headers of the multiple first-class messages with the data of the multiple first-class messages.

[0076] S33. The aligned header and data are treated as the first type of message after processing.

[0077] In this embodiment, multiple D2H data and / or S2M drs message headers exist in a slot. Subsequent slots transmit data corresponding to each message header. In this case, multiple message headers can be parsed first, followed by the corresponding data. Since the message headers are parsed first, they can be cached, awaiting data retrieval. Each time a set of data is retrieved, a corresponding message header is output from the cache, and the message header and data are sent together to the next-level module.

[0078] In this embodiment of the disclosure, since the message header is extracted earlier than the corresponding data, the message header and the corresponding data are aligned before being output to the next level module.

[0079] In this embodiment of the disclosure, the extracted message header can be stored in a shift buffer, such as... Figure 6The diagram illustrates the process of aligning message headers with corresponding data. The shift buffer can consist of two parts, A and B. Part A contains the extracted message header content, and part B is a message type identifier. This identifier indicates whether the buffer is for an S2M drs message header or a D2H data message header. Whenever the parsing module outputs a set of data corresponding to the message header, a set of message headers is synchronously extracted from the shift buffer. The message header and data in part A are aligned, and then, based on the message type identifier in part B, the output is selected from either the S2Mdrs channel or the D2H data channel.

[0080] In this embodiment of the disclosure, processing the second type of message based on the processing result of the first type of message may include:

[0081] After the end time and / or end position of the first type of message parsing, determine the type of subsequent slots;

[0082] In response to the determination that the subsequent message type of the flit transmission message is a second type message based on the subsequent slot type, the message header of the second type message is directly output through the corresponding output channel.

[0083] In this embodiment of the disclosure, as can be seen from the foregoing scheme, the slot type of the flit transmission message can be used to determine whether there is a first type of message (such as a D2H data message or an S2M drs message) in the flit transmission message. If there is a first type of message, the first type of message is processed first. If there is no first type of message and only a second type of message (such as other D2H and S2M messages) exists, the second type of message is processed directly. If both the first type of message and the second type of message exist, the first type of message is processed first, and then the second type of message is processed based on the processing result of the first type of message.

[0084] In this embodiment of the disclosure, if there are no first-type messages such as D2H data or S2M drs, and the identification of the remaining second-type messages such as D2H and S2M messages is started directly, since the remaining D2H and S2M messages do not follow the data, only the message header needs to be extracted; if there are D2H data or S2M drs messages in the flit transmission message, after determining the end time and / or end position of the D2H data or S2M drs messages, the message types contained in the subsequent slots can be determined from the end time and / or end position, and the remaining D2H or S2M messages can be identified and extracted.

[0085] In this embodiment of the disclosure, for example, if the flit transmission message received by the host side carries one S2M drs message and three D2H req messages, and the S2M drs message is transmitted before the D2H req message, the S2M drs message is extracted first, and the processing method is the same as described in the previous scheme, so it will not be repeated here. After the S2M drs message is extracted, the end time and / or end position of the S2M drs message can be known. From the end time and / or end position, the message type and the number of data following each slot can be determined in turn to obtain the message header and the number of data of the D2H req message. Since no data follows the D2H req message header, there is no need to perform message header and data alignment processing. The parsed message header can be directly output by the D2H req output channel.

[0086] In this embodiment of the disclosure, when transmitting the parsed first type of message and / or second type of message to the next level module, channel-based output can be performed based on the domain segments in the message.

[0087] In this embodiment, mixed transmission of link-layer D2H and S2M messages can be supported. Based on the preceding parsing scheme, various types of message headers for D2H and S2M can be identified and extracted from the flit transmission messages. Each message header also contains various field segment messages. Since the data format required by the next-level module differs from the cxl protocol, after the aforementioned parsing process and message header extraction, valid field segment information is extracted from the message header. Furthermore, the format of each field segment information in the message header is readjusted to form the format required by the next-level module, thereby adapting to the format required by the next-level module and outputting it. Each message has an independent corresponding channel with the next-level module, and the parsing module can place the finally parsed content in the corresponding output channels and transmit it to the next-level module.

[0088] In this embodiment of the disclosure, the message processing method during the message packet assembly process of the flit transmission message in the uplink layer sending direction of the host is described below. For example... Figure 7 The diagram shown is a schematic representation of the packaging method according to an embodiment of this disclosure.

[0089] In this embodiment of the disclosure, in the data transmission direction of the host link layer, the upper-level module can output various types of messages through different channels according to different message types (or protocol message types), and the packet assembly module of the link layer can receive various types of messages through different channels.

[0090] In this embodiment of the disclosure, the packet assembly module can first cache the received messages for subsequent processing (e.g., packet assembly). At the entry point of the packet assembly module, a message collection queue is set for each message channel. Each time a message is received, the message is written to the corresponding message collection queue.

[0091] In this embodiment of the disclosure, since multiple message collection queues may have messages cached at the same time, the messages in the queues can be read from each other based on priority arbitration and back pressure from the next level module (such as the packet assembly module).

[0092] In this embodiment of the disclosure, the priority of each message collection queue can be dynamically adjusted according to the system configuration and the back pressure of the packet assembly module, with high-priority messages being read first and low-priority messages being read later.

[0093] In this embodiment, when the packet assembly module pulls down the backpressure signal sent to the message collection queue, it indicates that packet assembly for a certain message needs to be temporarily stopped. The message collection queue is skipped in the current processing cycle and re-evaluated in the next round of packet assembly, thus achieving dynamic sorting of queue readings. Furthermore, each message collection queue can determine in real time whether its buffer is full. When the message collection queue buffer is full, a feedback signal can be generated and sent to the previous-level module. When this feedback signal is valid, it indicates that the packet assembly module pauses receiving flit transmission messages, and the previous-level module stops outputting flit transmission messages for the corresponding channel. Each message collection queue can generate its own independent feedback signal.

[0094] In this embodiment of the disclosure, the first type of messages in the received flit transmission message can be grouped into packets. Before doing so, it is necessary to first determine the message types contained in the flit transmission message.

[0095] In this embodiment of the disclosure, determining the message type contained in the flit transmission message may include:

[0096] Determine the receiving channel for the flit transmission message; flit transmission messages are sent through different channels based on different message types;

[0097] The message type contained in the flit transmission message is determined based on the message type corresponding to the receiving channel.

[0098] In this embodiment of the disclosure, for example, the packet assembly module receives four different types of messages from the previous-level module simultaneously from different receiving channels. Based on the four different receiving channels, it can be determined that the received messages are M2Srwd, M2S req, H2D req, and H2D rsp messages, respectively. The four messages can be cached in their respective message collection queues, and then different messages can be read from the corresponding message collection queues.

[0099] In this embodiment of the disclosure, after storing the four messages into their respective message collection queues, the message collection queues can be read starting according to the initial message priority set by the system. For example, as... Figure 8As shown, the initial priority order can be set as follows: M2S rwd messages have the highest priority, followed by M2S req messages, then H2D req messages, and finally H2D rsp messages have the lowest priority. In the first clock cycle (1clk), the M2S rwd message queue is read. Then, in the second clock cycle (2clk), when reading M2S req messages, if the reverse voltage signal for M2S req messages from the next-level module is pulled low, the priority of M2S req messages is dynamically adjusted to the lowest, and M2S req messages are skipped. The H2D req message queue is read instead. In the third clock cycle (3clk), the H2D rsp message queue is read, at which point the first round of reading ends. Since only M2S req messages remain in the queue, the second round begins. In the fourth clock cycle (4clk), the M2S req message queue is read directly, at which point all messages have been read from the queue.

[0100] In this embodiment of the disclosure, the processing includes: packet assembly; prioritizing the processing of the first type of message may include:

[0101] Read the message header and data corresponding to the first type of message, and place the data after the message header during the packet assembly process;

[0102] as well as,

[0103] Determine the second data volume of the data; the second data volume includes: the total data volume and the remaining data volume; determine the end time and / or end position of the first type of message group based on the second data volume.

[0104] In this embodiment of the disclosure, according to the flit format set by the current system, the packet assembly module can assemble different types of messages. Since M2S rwd and H2D data messages consist of two parts, a message header and the data that follows, both M2S rwd and H2D data messages belong to the first type of data, while other types of messages only contain a message header and belong to the second type of data, M2S rwd and H2D data messages are prioritized for assembling.

[0105] In this embodiment of the disclosure, it can first be determined whether there are messages in the message collection queues of the H2D data channel and the M2S rwd channel. If there are messages, the message header and data in the message collection queues of the H2D data channel and the M2S rwd channel are read, and the data is placed immediately after the message header. If there are no H2D data and M2S rwd messages, other messages (such as second type messages) are processed.

[0106] In this embodiment, the packetization of H2D data messages and M2S rwd messages can be processed in two parallel streams. One stream processes the packets in flit format, and the flit format of the current transmission can be obtained according to the system configuration. The message header and corresponding data are placed in the flit according to the format specified by the cxl protocol. The other stream performs real-time data calculation, calculates the total amount of data following the message header and the amount of remaining data, and calculates the end position and end time of the H2D data and M2S rwd message packetization. After the H2D data and M2S rwd message packetization ends, the packetization of the remaining messages begins.

[0107] In this disclosure, an example of H2D data message packetization is given below.

[0108] In this embodiment of the disclosure, for example, two H2D data messages can be packetized and output, with each H2D data message header corresponding to a 64B data segment. The system uses a 256B standard format for the flit type, and the processing flow is as follows. Figure 9 As shown, the system first determines whether an H2D data message can be sent. This is based on two criteria: one, polling the H2D data message collection queue; and two, the absence of backpressure from the next-level module. If an H2D data message cannot be sent at this time, the system continues to wait for one, as shown in the attached diagram. Figure 9 In the waiting step, if an H2D data message can be sent, proceed to the next step: calculate the number of H2D data messages to be packaged and the corresponding second data volume. The second data volume includes, but is not limited to, the total data volume and the remaining data volume. If there are two H2D data messages to be packaged, place the H2D data message header in the first slot of the flit according to the format defined by the cxl protocol, and calculate the total data volume following the message header and the remaining data volume. The initial total data volume is 128B, and the remaining data volume is 128B. Then, calculate the total data volume and the remaining volume in real time according to the packaging situation. When the total data volume and the remaining volume are 0, it means that the data corresponding to the H2D data message header has been fully packaged into the flit; otherwise, continue to package the H2D data messages.

[0109] In this embodiment of the disclosure, the second type of message is processed based on the processing result of the first type of message, including:

[0110] The second type of message is packaged based on the end time and / or end position of the first type of message package.

[0111] In this embodiment, the M2S rwd and H2D data messages (first type of messages) in the aforementioned embodiments are prioritized for packet assembly. The remaining H2D and M2S messages only have message headers and do not require subsequent data. The remaining M2S and H2D messages (second type of messages) need to wait for the M2S rwd and H2D data messages to finish packet assembly before they begin packet assembly. Therefore, during the packet assembly of the M2S rwd and H2D data messages, the remaining M2S and H2D messages wait in the message collection queue. When the M2S rwd and H2D data messages finish packet assembly, the remaining M2S and H2D messages begin packet assembly. Based on the output of the real-time calculation module in the third step, the end time and exact end position of the M2S rwd and H2D data message packet assembly can be determined. The remaining M2S and H2D messages immediately follow the end position of the M2S rwd and H2D data message packet assembly and begin packet assembly, placing the remaining M2S and H2D messages in the flit according to the format defined by the cxl protocol.

[0112] In this embodiment of the disclosure, the method may further include:

[0113] Count the number of packets of each message type within the first preset time period;

[0114] Determine the first target message type that has the largest proportion of the total number of packets;

[0115] Increase the packet assembly priority of the first target message type in the next round of packet assembly;

[0116] or,

[0117] Count the number of messages of each message type sent within the second preset time period;

[0118] Determine the second target message type that has the largest proportion of the number of messages sent;

[0119] Increase the packet assembly priority of the second target message type in the next round of packet assembly.

[0120] In this embodiment, a packet assembly efficiency balancing module is provided. The purpose of this module is to balance the packet sending efficiency among different types of messages, so that messages with large sending volumes can be sent first. The packet assembly efficiency balancing module counts the number of each type of message over a certain period of time and determines the message with the largest percentage of messages. The largest percentage indicates that the message has the largest sending volume, and the sending priority of the message is increased in the next round of packet assembly, and the message is assembled first.

[0121] In this embodiment of the disclosure, the packet priority of each message is not fixed. The efficiency balancing module can be used to dynamically adjust the packet priority of each message so that messages with a large demand for sending within a certain period of time can be sent first, avoiding long-term blocking of messages with a large number of messages.

[0122] In this embodiment, for example, there are three types of messages that need to be packetized and sent: M2S req, H2D req, and H2D rsp. The efficiency balancing module can count the number of packetizations of these three types of messages within a certain period of time. The counting period is set by the system to N clock cycles. In the first counting period, the three types of messages are packetized according to the initial priority set by the system, with M2S req having the highest priority, followed by H2D req, and H2D rsp having the lowest priority. After N clock cycles, if the efficiency balancing module finds that the proportion of H2D req messages sent is the largest, it indicates that the demand for H2D req messages is the largest during this period. Therefore, in the second counting period, the packetization priority of H2D req messages is adjusted to the highest, and a new round of packetization processing is performed. In the new cycle, the proportion of message sending is counted again to achieve dynamic balance of the priorities of each message.

[0123] In this embodiment of the disclosure, according to the CXL protocol, each flit carries cyclic redundancy (CRC) information. Therefore, after packet assembly, CRC calculation needs to be performed on the flit to generate a CRC checksum. The calculated CRC checksum is then filled into the flit according to the format specified in the CXL protocol and sent to the next-level module for further processing.

[0124] This disclosure embodiment includes at least the following advantages:

[0125] 1. Unlike traditional enumeration methods, the solution in this disclosure employs a dynamic, real-time calculation approach for group unpacking. This method is applicable to all current flit combinations, and when future protocols evolve to new flit formats, only the calculation parameters need to be modified accordingly for unpacking the new format. It exhibits broad versatility and flexibility. Furthermore, while the description of this disclosure is from a host perspective, the method is not limited to the host and is equally applicable to slave devices.

[0126] 2. The present invention provides a general and efficient method for parsing and assembling data at the link layer of the CXL protocol. This method has low hardware circuit complexity and good scalability, and is of great significance and value in the context of the ongoing changes and evolution of the CXL protocol.

[0127] This disclosure also provides an electronic device 100, such as... Figure 10As shown, it includes:

[0128] One or more processors 101;

[0129] The memory 102 stores one or more programs, which, when executed by the one or more processors, enable the one or more processors 101 to implement the message processing method of the CXL protocol link layer.

[0130] One or more input / output (I / O) interfaces 103 are connected between the processor 101 and the memory 102 and configured to enable information interaction between the processor 101 and the memory 102.

[0131] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the message processing method of the CXL protocol link layer.

[0132] This disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements the message processing method of the CXL protocol link layer.

[0133] In this disclosure, any of the aforementioned message processing methods for the cxl protocol link layer are applicable to the electronic device, storage medium, and program product embodiments, and will not be described in detail here.

[0134] Those skilled in the art will understand that all or some of the functional modules / units disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0135] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0136] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0137] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A message processing method for the link layer of the CXL protocol, comprising: Obtain the link layer transmission unit (flit) transmission message; Determine the message type contained in the flit transmission message; the message type includes a first type of message and / or a second type of message; the first type of message includes a message header and data; the second type of message includes only a message header. In response to the fact that the flit transmission message includes the first type of message and the second type of message, the first type of message is processed first. The message processing method includes a message processing method during message parsing or a message processing method during message packet assembly. Wherein, when the message processing method is a message processing method during message parsing, the priority processing of the first type of message includes: determining the processing period of the first type of message based on its bit width; extracting the data within each processing period based on the processing period, and determining a first data volume of the parsed data within each processing period; and determining the end time and / or end position of the parsing of the first type of message based on the first data volume of the parsed data across all processing periods. The second type of message is processed based on the processing result of the first type of message.

2. The message processing method of the cxl protocol link layer according to claim 1, wherein, The message processing method is the message processing method during the message parsing process; Determining the message type contained in the flit transmission message includes: The slot type of the flit transmission message is determined based on the message header of the flit transmission message; The message type contained in the flit transmission message is determined based on the slot type.

3. The message processing method of the cxl protocol link layer according to claim 1, wherein, The first data volume includes at least one of the following: the total data volume corresponding to the message header of the first type of message, the newly generated data volume, the remaining data volume, and the data volume to be extracted from the current first type of message.

4. The message processing method of the cxl protocol link layer according to claim 3, wherein, The step of prioritizing the processing of the first type of message further includes: In response to the fact that the message headers of multiple messages of the first type are in the same slot, the data of the multiple messages of the first type are parsed after the message headers of the multiple messages of the first type are parsed first. Align the parsed message headers of the multiple first-type messages with the data of the multiple first-type messages; The aligned header and data are used as the processed first type of message.

5. The message processing method of the cxl protocol link layer according to claim 3, wherein, The processing of the second type of message based on the processing result of the first type of message includes: After the end time and / or end position of the first type of message parsing, determine the subsequent slot type; In response to determining that the subsequent message type of the flit transmission message is the second type of message based on the subsequent slot type, the message header of the second type of message is directly output through the corresponding output channel.

6. The message processing method of the cxl protocol link layer according to claim 1, wherein, The message processing method is the message processing method during the message packet assembly process; Determining the message type contained in the flit transmission message includes: Determine the receiving channel for the flit transmission message; the flit transmission message is sent through different channels based on different message types; The message type contained in the flit transmission message is determined based on the message type corresponding to the receiving channel.

7. The message processing method of the cxl protocol link layer according to claim 1, wherein, The message processing method is the message processing method during the message packet assembly process; The priority processing of the first type of message includes: Read the message header and data corresponding to the first type of message, and place the data after the message header during the packet assembly process; as well as, Determine a second data volume of the data; the second data volume of the data includes: total data volume and / or remaining data volume; determine the end time and / or end position of the first type of message packet based on the second data volume.

8. The message processing method of the cxl protocol link layer according to claim 7, wherein, The processing of the second type of message based on the processing result of the first type of message includes: The second type of messages are packaged based on the end time and / or end position of the first type of message package.

9. The message processing method of the cxl protocol link layer according to claim 1, wherein, The message processing method is the message processing method during the message packet assembly process; The method further includes: Count the number of packets of each message type within the first preset time period; Determine the first target message type that has the largest proportion of the total number of packets; Increase the packet assembly priority of the first target message type in the next round of packet assembly; or, Count the number of messages of each message type sent within the second preset time period; Determine the second target message type that has the largest proportion of the number of messages sent; Increase the packet assembly priority of the second target message type in the next round of packet assembly.

10. An electronic device, comprising: One or more processors; A memory having stored one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the message processing method of the cxl protocol link layer as described in any one of claims 1-9; One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

11. A computer program product comprising a computer program that, when executed by a processor, implements the message processing method of the CXL protocol link layer as described in any one of claims 1-9.

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