Complementary method of three-path pwm signal, computer device and readable storage medium

Abstract

The application discloses a complementary method of three-way PWM signals, a computer device and a readable storage medium, and relates to the technical field of illumination. The method comprises the following steps: setting a counting mode of a timer to a central alignment mode, and dividing a counting period of the timer into a first half period and a second half period; initializing a front comparison value of the first half period, a rear comparison value of the second half period and an effective level of a first PWM channel, a second PWM channel and a third PWM channel, so that a first PWM signal of the first PWM channel, a second PWM signal of the second PWM channel and a third PWM signal of the third PWM channel are complementary; acquiring duty cycle setting values of the first PWM signal, the second PWM signal and the third PWM signal in real time; and adjusting the front comparison value, the rear comparison value and the effective level of the first PWM channel, the second PWM channel and the third PWM channel in real time according to the duty cycle setting values of the first PWM signal, the second PWM signal and the third PWM signal, so that the first PWM signal, the second PWM signal and the third PWM signal are complementary. By adopting the application, strict alternation and dynamic collaborative control of the three-way PWM signals can be realized.

Description

Technical Field

[0001] This invention relates to the field of lighting technology, and more particularly to a method for complementing three PWM signals, a computer device, and a readable storage medium. Background Technology

[0002] Pulse Width Modulation (PWM) technology, as a core control method in the field of power electronics, is widely used in motor drives, power conversion, and lighting systems. In recent years, with the popularization of multi-channel loads (such as RGB three-color LED lighting), the synchronous control of multiple PWM signals has become a key technical requirement. For example, in RGB lighting mixed scenarios, it is necessary to independently adjust the brightness duty cycle of red, green, and blue light through three PWM signals while ensuring a constant total light intensity. This places stringent requirements on the timing synchronization and duty cycle coordination of multiple PWM signals.

[0003] Traditional multi-channel PWM solutions typically employ independent timers or time-division multiplexing of channels, which have the following significant drawbacks:

[0004] (1) Risk of high-level overlap: When each channel runs independently, the duty cycle is not forced to be correlated, which can easily lead to high-level overlap of multiple PWM signals, causing instantaneous overcurrent or color mixing distortion in the circuit (such as RGB light color shift).

[0005] (2) Limitations of complementary PWM: Existing complementary PWM technology only supports paired channels (such as H-bridge drive) and avoids shoot-through through dead time, but cannot be extended to strict time-sharing control of three independent channels, resulting in the inability to achieve complete alternation of three color signals in RGB lighting.

[0006] (3) Insufficient dynamic adjustment capability: Current solutions rely on software to calculate the duty cycle in real time or external logic circuits (such as CPLD, Complex Programmable Logic Device) to coordinate multiple channels, which has problems such as response delay, high resource consumption and increased cost; especially when dynamically adjusting RGB colors, the total duty cycle is difficult to maintain a constant, resulting in brightness fluctuations or color temperature deviations.

[0007] To address the aforementioned issues, existing technologies attempt to achieve multi-channel collaboration through time-division multiplexing or complex algorithms. However, due to limitations in hardware architecture, bottlenecks such as poor real-time performance and insufficient stability remain. For example, software solutions require frequent interrupts to update registers, leading to PWM waveform jitter or limiting the minimum duty cycle; external circuitry increases system complexity and power consumption, making it difficult to adapt to miniaturized, low-cost lighting equipment. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a method for complementing three PWM signals, a computer device and a readable storage medium, which can realize strict alternation and dynamic coordinated control of three PWM signals.

[0009] To address the aforementioned technical problems, this invention provides a method for complementing three PWM signals, comprising: setting a timer's counting mode to a center-aligned mode, wherein the timer's counting period is divided into a first half-cycle and a second half-cycle; initializing the front comparison value of the first half-cycle, the back comparison value of the second half-cycle, and the valid level of the first PWM channel, the second PWM channel, and the third PWM channel, so that the first PWM signal of the first PWM channel, the second PWM signal of the second PWM channel, and the third PWM signal of the third PWM channel are complementary; acquiring the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal in real time; and adjusting the front comparison value, the back comparison value, and the valid level of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal, so that the first PWM signal, the second PWM signal, and the third PWM signal are complementary.

[0010] As an improvement to the above scheme, the step of initializing the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel includes: setting the effective level of the second PWM channel to a first level; setting the effective levels of the first PWM channel and the third PWM channel to a second level; wherein, when the first level is high, the second level is low, and when the first level is low, the second level is high.

[0011] As an improvement to the above scheme, when the first level is high and the second level is low, the step of initializing the first half-cycle comparison value and the second half-cycle comparison value of the first PWM channel, the second PWM channel, and the third PWM channel includes: initializing the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal is 100%; according to the formula CCR1=(T / 2-D PWM1 )×E, calculate the first pre-compare value CCR1 of the first half-cycle of the first PWM channel; according to the formula CCR2=(T / 2-D PWM1Calculate the second front comparison value CCR2 for the first half-cycle of the second PWM channel according to the formula CCR3 = (T / 2) × E; calculate the third front comparison value CCR3 for the first half-cycle of the third PWM channel according to the formula CCR3 = (T / 2) × E; calculate the first back comparison value CCR1FALL for the second half-cycle of the first PWM channel according to the formula CCR1FALL = (T / 2) × E; calculate the first back comparison value CCR1FALL for the second half-cycle of the first PWM channel according to the formula CCR2FALL = (T / 2 - D) × E; PWM3 )×E, calculate the second post-compare value CCR2FALL of the second half-cycle of the second PWM channel; according to the formula CCR3FALL=(T / 2-D PWM3 )×E, calculate the third post-compare value CCR3FALL of the second half-cycle of the third PWM channel; where T is 100%, D PWM1 D sets the duty cycle value for the first PWM signal. PWM3 This sets the duty cycle value for the third PWM signal, where E is the PWM resolution.

[0012] As an improvement to the above scheme, when the first level is low and the second level is high, the step of initializing the first half-cycle's front comparison value and the second half-cycle's back comparison value of the first PWM channel, the second PWM channel, and the third PWM channel includes: initializing the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal is 100%; according to the formula CCR1 = D PWM1 ×E, calculate the first pre-compare value CCR1 of the first half-cycle of the first PWM channel; according to the formula CCR2=D PWM1 ×E, calculate the second front comparison value CCR2 for the first half-cycle of the second PWM channel; according to the formula CCR3=0, calculate the third front comparison value CCR3 for the first half-cycle of the third PWM channel; according to the formula CCR1FALL=0, calculate the first back comparison value CCR1FALL for the second half-cycle of the first PWM channel; according to the formula CCR2FALL=D PWM3 ×E, calculate the second post-compare value CCR2FALL for the second half-cycle of the second PWM channel; according to the formula CCR3FALL=D PWM3 ×E, calculate the third post-compare value CCR3FALL of the second half-cycle of the third PWM channel; where, D PWM1 D sets the duty cycle value for the first PWM signal. PWM3 This sets the duty cycle value for the third PWM signal, where E is the PWM resolution.

[0013] As an improvement to the above scheme, the step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal includes: when the duty cycle setting of any one of the first PWM signal, the second PWM signal, and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting greater than 50% is taken as the first target PWM channel, the PWM channel corresponding to a PWM signal with a duty cycle setting less than 50% is taken as the second target PWM channel, and the PWM channel corresponding to another PWM signal with a duty cycle setting less than 50% is taken as the third target PWM channel; the effective level of the first target PWM channel is adjusted to a first level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to a second level.

[0014] As an improvement to the above scheme, the step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal includes: when the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, keeping the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel unchanged.

[0015] As an improvement to the above scheme, when the first level is high and the second level is low, the step of adjusting the before and after comparison values ​​of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal includes: according to the formula CCRa=(T / 2-D PWM’ )×E, calculate the first target comparison value CCRa of the first target PWM channel in the first half cycle; according to the formula CCRb=(T / 2-D PWM’ )×E, calculate the second pre-target comparison value CCRb of the first half-cycle of the second target PWM channel; according to the formula CCRc=(T / 2)×E, calculate the third pre-target comparison value CCRc of the first half-cycle of the third target PWM channel; according to the formula CCRaFALL=(T / 2-D PWM” Calculate the first post-target comparison value CCRbFALL for the second half-cycle of the first target PWM channel according to the formula CCRbFALL = (T / 2) × E; calculate the second post-target comparison value CCRbFALL for the second half-cycle of the second target PWM channel according to the formula CCRbFALL = (T / 2 - D) × E; calculate the second post-target comparison value CCRbFALL for the second half-cycle of the second target PWM channel according to the formula CCRbFALL = (T / 2 - D) × E; PWM”)×E, calculate the third post-target comparison value CCRcFALL of the second half-cycle of the third target PWM channel; where T is 100%, D PWM’ For a PWM signal with a duty cycle setting value less than 50%, D PWM” The duty cycle setting value for another PWM signal with a duty cycle setting value less than 50%, where E is the resolution of the PWM.

[0016] As an improvement to the above scheme, when the first level is low and the second level is high, the step of adjusting the before and after comparison values ​​of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal includes: according to the formula CCRa = D PWM’ ×E, calculate the first target comparison value CCRa of the first target PWM channel in the first half-cycle; according to the formula CCRb=D PWM’ ×E, calculate the second pre-target comparison value CCRb of the first half-cycle of the second target PWM channel; according to the formula CCRc=0, calculate the third pre-target comparison value CCRc of the first half-cycle of the third target PWM channel; according to the formula CCRaFALL=D PWM” ×E, calculate the first post-target comparison value CCRbFALL for the second half-cycle of the first target PWM channel; according to the formula CCRbFALL=0, calculate the second post-target comparison value CCRbFALL for the second half-cycle of the second target PWM channel; according to the formula CCRcFALL=D PWM” ×E, calculate the third post-target comparison value CCRcFALL of the second half-cycle of the third target PWM channel; where, D PWM’ For a PWM signal with a duty cycle setting value less than 50%, D PWM” The duty cycle setting value for another PWM signal with a duty cycle setting value less than 50%, where E is the resolution of the PWM.

[0017] Accordingly, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-mentioned complementary method of three PWM signals.

[0018] Accordingly, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described method for complementing the three PWM signals.

[0019] This invention can be implemented using a common M0 microcontroller. Through an innovative timer configuration and duty cycle coupling mechanism, it achieves strictly alternating output of three signals and dynamically constant total duty cycle, fundamentally improving color accuracy and energy efficiency. Implementing this invention has the following beneficial effects:

[0020] (1) Zero overlap risk, ensuring circuit safety and color mixing accuracy;

[0021] (2) Simplifies system design, reduces MCU resource consumption and external circuits, and has a relatively low cost;

[0022] (3) Hardware implementation avoids the risk of software jitter, and the high PWM output frequency ensures stable RGB lighting brightness. Attached Figure Description

[0023] Figure 1 This is a flowchart of the first embodiment of the complementary method for three PWM signals of the present invention;

[0024] Figure 2 This is a waveform diagram of the first embodiment of the three-channel PWM signal in this invention;

[0025] Figure 3 This is a flowchart of the second embodiment of the complementary method for three PWM signals of the present invention;

[0026] Figure 4 This is a waveform diagram of the second embodiment of the three-channel PWM signal in this invention;

[0027] Figure 5 This is a waveform diagram of the third embodiment of the three-channel PWM signal in this invention;

[0028] Figure 6 This is a waveform diagram of the fourth embodiment of the three-channel PWM signal in this invention;

[0029] Figure 7 This is a flowchart of the third embodiment of the complementary method for three PWM signals of the present invention;

[0030] Figure 8 This is the waveform diagram of the fifth embodiment of the three-channel PWM signal in this invention;

[0031] Figure 9 This is the waveform diagram of the sixth embodiment of the three-channel PWM signal in this invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0033] See Figure 1 , Figure 1The flowchart of a first embodiment of the complementary method for three PWM signals of the present invention is shown, which includes:

[0034] S101, set the timer's counting mode to center-aligned mode;

[0035] like Figure 2 As shown, △ABC is the triangular wave corresponding to the center alignment mode, point B is the midpoint of the triangular wave, and line segment AC is the triangular wave period (i.e., the counting period / PWM period). Among them, PWM1, PWM2 and PWM3 are the three channels of the timer that output PWM signals. After adopting the center alignment mode, the timer's counting period is divided into the first half period and the second half period by line segment BB'.

[0036] S102, initialize the first half-cycle front comparison value, the second half-cycle back comparison value, and the effective level of the first PWM channel, the second PWM channel, and the third PWM channel, so that the first PWM signal of the first PWM channel, the second PWM signal of the second PWM channel, and the third PWM signal of the third PWM channel are complementary;

[0037] It should be noted that the present invention configures timers to specify the first half-cycle comparison value, the second half-cycle comparison value, and the effective level of each PWM channel, so as to construct the waveform of the PWM signal in a targeted manner.

[0038] On the one hand, the steps for initializing the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel include:

[0039] (1) Set the effective level of the second PWM channel to the first level;

[0040] (2) Set the effective level of the first PWM channel and the third PWM channel to the second level;

[0041] For example, when the first level is high, the second level is low;

[0042] For example, when the first level is low, the second level is high.

[0043] In other words, when setting the effective level, it is only necessary to ensure that the effective level of the second PWM channel is different from the effective levels of the first PWM channel and the third PWM channel.

[0044] On the other hand, the front comparison value of the first half cycle and the back comparison value of the second half cycle of each PWM channel are configured according to the preset duty cycle setting value of each PWM signal. During configuration, the front comparison value and the back comparison value can be configured by setting the front half comparison register and the back half comparison register of each PWM channel.

[0045] For example, such as Figure 2 As shown, when the effective level of the first PWM channel is set to low, and the front comparison value in the front half comparison register is 17 and the back comparison value in the back half comparison register is 25, it means that the low level accounts for 17% and the high level accounts for 33% in the first half cycle, and the low level accounts for 25% and the high level accounts for 25% in the second half cycle. Generally, the waveform is constructed with point B' as the starting position. Therefore, in the first half cycle, a 17% low level interval is first constructed from point B' towards point A, followed by a 33% high level interval. And a 25% low level interval is first constructed from point B' towards point C, followed by a 25% high level interval.

[0046] S103, real-time acquisition of the duty cycle setting values ​​of the first PWM signal, the second PWM signal and the third PWM signal;

[0047] S104, adjust the before comparison value, after comparison value and effective level of the first PWM channel, the second PWM channel and the third PWM channel in real time according to the duty cycle setting value of the first PWM signal, the second PWM signal and the third PWM signal, so that the first PWM signal of the first PWM channel, the second PWM signal of the second PWM channel and the third PWM signal of the third PWM channel are complementary.

[0048] In actual operation, anomalies may occur when the duty cycle setting of any PWM signal exceeds 50%. Therefore, it is necessary to adjust the before-compare value, after-compare value, and effective level of the first, second, and third PWM channels in real time according to the duty cycle settings of the first, second, and third PWM signals to ensure that the first, second, and third PWM signals are complementary.

[0049] Accordingly, the step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal includes:

[0050] (1) When the duty cycle setting value of any of the first PWM signal, the second PWM signal and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting value greater than 50% is taken as the first target PWM channel, the PWM channel corresponding to the PWM signal with a duty cycle setting value less than 50% is taken as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with a duty cycle setting value less than 50% is taken as the third target PWM channel; the effective level of the first target PWM channel is adjusted to the first level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to the second level.

[0051] (2) When the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal are all less than or equal to 50%, the effective level of the first PWM channel, the second PWM channel and the third PWM channel remains unchanged.

[0052] At the same time, the before and after comparison values ​​of the first PWM channel, the second PWM channel, and the third PWM channel need to be adjusted in real time according to the two PWM signals configured as the second level, so as to ensure that the first PWM signal, the second PWM signal, and the third PWM signal are complementary.

[0053] See Figure 3 , Figure 3 A flowchart of a second embodiment of the complementary method for three PWM signals of the present invention is shown, which includes:

[0054] S201, set the timer's counting mode to center-aligned mode;

[0055] S202, initialize the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal is 100%;

[0056] S203, set the effective level of the second PWM channel to high level, and set the effective levels of the first PWM channel and the third PWM channel to low level;

[0057] S204 calculates the first half-cycle comparison value and the second half-cycle comparison value of the first PWM channel, the second PWM channel and the third PWM channel respectively according to the preset formula;

[0058] The specific calculation formula is as follows:

[0059] (1) According to the formula CCR1=(T / 2-D PWM1 )×E, calculate the first pre-compare value CCR1 (i.e., the value of the first half-compare register of the first PWM channel) for the first half-cycle; where T is 100%, D PWM1 This is the duty cycle setting value for the first PWM signal, where E is the PWM resolution. Generally, E is set to 100 or 1000, but this is not a limitation and can be set according to the actual situation.

[0060] (2) According to the formula CCR2=(T / 2-D PWM1 )×E, calculate the second front-compare value CCR2 (i.e. the value of the front-half comparator register of the second PWM channel) for the first half cycle;

[0061] (3) Calculate the third pre-compare value CCR3 (i.e. the value of the first half-compare register of the third PWM channel) in the first half cycle of the third PWM channel according to the formula CCR3=(T / 2)×E;

[0062] (4) Calculate the first back comparison value CCR1FALL (i.e. the value of the back half comparison register of the first PWM channel) in the second half cycle of the first PWM channel according to the formula CCR1FALL=(T / 2)×E.

[0063] (5) According to the formula CCR2FALL=(T / 2-D PWM3 )×E, calculate the second back-compare value CCR2FALL (i.e., the value of the back-compare register of the second PWM channel) for the second half-cycle; where, D PWM3 Set the duty cycle value for the third PWM signal;

[0064] (6) According to the formula CCR3FALL=(T / 2-D PWM3 )×E, calculate the third back-compare value CCR3FALL (i.e. the value of the back-compare register of the third PWM channel) in the second half cycle.

[0065] like Figure 2 As shown, when the duty cycle setting value D of the first PWM signal is... PWM1 The duty cycle setting value D of the third PWM signal is 33%. PWM3 When the threshold is 25%, the calculated before-comparison and after-comparison values ​​are as follows:

[0066] The first pre-compare value of the first half-cycle of the first PWM channel is: CCR1 = B'D' = (100% / 2 - 33%) × 100 = 17; the first post-compare value of the second half-cycle of the first PWM channel is: CCR1FALL = B'C = (100% / 2) × 100 = 50; since the first PWM channel is configured to be active low, the first PWM signal is low in segment B'D', high in segment D'A, and low in segment B'C.

[0067] The second pre-compare value for the first half-cycle of the second PWM channel is: CCR2 = B'D' = (100% / 2 - 33%) × 100 = 17; the second post-compare value for the second half-cycle of the second PWM channel is: CCR2FALL = B'E' = (100% / 2 - 25%) × 100 = 25; since the second PWM channel is configured to be active high, the second PWM signal is high in segment B'D', low in segment D'A, high in segment B'E', and low in segment E'C.

[0068] The value of the third pre-compare in the first half-cycle of the third PWM channel is: CCR3 = B'A = (100% / 2) × 100 = 50; the value of the third post-compare in the second half-cycle of the third PWM channel is: CCR3FALL = B'E' = (100% / 2 - 25%) × 100 = 25; since the third PWM channel is configured to be active low, the third PWM signal is low in segment B'A, low in segment B'E', and high in segment E'C.

[0069] Therefore, by configuring the values ​​of the first half and second half of the comparator registers for each channel using the above method, the three PWM signals can be made complementary.

[0070] S205, real-time acquisition of the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal;

[0071] S206, adjust the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal;

[0072] (1) When the duty cycle setting value of any of the first PWM signal, the second PWM signal and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting value greater than 50% is taken as the first target PWM channel, the PWM channel corresponding to the PWM signal with a duty cycle setting value less than 50% is taken as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with a duty cycle setting value less than 50% is taken as the third target PWM channel; the effective level of the first target PWM channel is adjusted to high level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to low level.

[0073] For example, if the duty cycle setting of the first PWM signal is greater than 50%, the effective level of the first PWM channel is adjusted to a high level, and the effective levels of the second and third PWM channels are adjusted to a low level.

[0074] For example, if the duty cycle setting of the third PWM signal is greater than 50%, the effective level of the third PWM channel will be adjusted to a high level, and the effective levels of the first PWM channel and the second PWM channel will be adjusted to a low level.

[0075] (2) When the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal are all less than or equal to 50%, the effective level of the first PWM channel, the second PWM channel and the third PWM channel remains unchanged.

[0076] S207, calculate the before and after comparison values ​​of the first PWM channel, the second PWM channel and the third PWM channel respectively according to the preset formula;

[0077] The specific calculation formula is as follows:

[0078] (1) According to the formula CCRa=(T / 2-D PWM’ )×E, calculate the first target comparison value CCRa of the first target PWM channel in the first half cycle; where T is 100%, D PWM’ E is the duty cycle setting value for a PWM signal with a duty cycle setting value of less than 50%. E is the resolution of the PWM. Generally, E is 100 or 1000, but this is not a limitation and can be set according to the actual situation.

[0079] (2) According to the formula CCRb=(T / 2-D PWM’ )×E, calculate the second pre-target comparison value CCRb for the first half cycle of the second target PWM channel;

[0080] (3) Calculate the third target comparison value CCRc of the first half cycle of the third target PWM channel according to the formula CCRc=(T / 2)×E;

[0081] (4) According to the formula CCRaFALL=(T / 2-D PWM” )×E, calculate the first post-target comparison value CCRaFALL for the second half-cycle of the first target PWM channel; where, D PWM” The duty cycle setting value for another PWM signal whose duty cycle setting value is less than 50%;

[0082] (5) Calculate the second target comparison value CCRbFALL of the second target PWM channel in the second half cycle according to the formula CCRbFALL=(T / 2)×E.

[0083] (6) According to the formula CCRcFALL=(T / 2-D PWM” )×E, calculate the third post-target comparison value CCRcFALL of the second half cycle of the third target PWM channel;

[0084] like Figure 4 As shown, when the duty cycle setting value of the first PWM signal is greater than 50% (the duty cycle setting value of the second PWM signal is D...), PWM’ The duty cycle setting value D for the third PWM signal is 15%. PWM” (25%), the first PWM channel is configured to be active high, and the second and third PWM channels are configured to be active low. The calculated before-compare and after-compare values ​​are as follows:

[0085] CCR1 = CCRa = B'D' = 35

[0086] CCR2=CCRb=B'D'=35

[0087] CCR3 = CCRc = B'A = 50

[0088] CCR1FALL=CCRaFALL=B'E'=25

[0089] CCR2FALL=CCRbFALL=B'C=50

[0090] CCR3FALL=CCRcFALL=B'E'=25

[0091] like Figure 5 As shown, when the duty cycle setting value of the second PWM signal is greater than 50% (the duty cycle setting value of the first PWM signal is D), PWM’ The duty cycle setting value D for the third PWM signal is 15%. PWM” (25%), the second PWM channel is configured to be active high, and the first and third PWM channels are configured to be active low. The calculated before-compare and after-compare values ​​are as follows:

[0092] CCR1=CCRb=B'D'=35

[0093] CCR2=CCRa=B'D'=35

[0094] CCR3 = CCRc = B'A = 50

[0095] CCR1FALL=CCRbFALL=B'C=50

[0096] CCR2FALL=CCRaFALL=B'E'=25

[0097] CCR3FALL=CCRcFALL=B'E'=25

[0098] like Figure 6 As shown, when the duty cycle setting value of the third PWM signal is greater than 50% (the duty cycle setting value of the first PWM signal is D), PWM’ The duty cycle setting value D of the second PWM signal is 15%. PWM” (25%), the third PWM channel is configured to be active high, and the first and second PWM channels are configured to be active low. The calculated before and after comparison values ​​are as follows:

[0099] CCR1=CCRb=B'D'=35

[0100] CCR2 = CCRc = B'A = 50

[0101] CCR3 = CCRa = B'D' = 35

[0102] CCR1 FALL=CCRbFALL=B'C=50

[0103] CCR2FALL=CCRcFALL=B'E'=25

[0104] CCR3FALL=CCRaFALL=B'E'=25

[0105] In other words, the present invention can calculate the before and after comparison values ​​of the first PWM channel, the second PWM channel, and the third PWM channel based on the duty cycle setting value of each PWM signal, thereby adjusting the waveforms of the first PWM signal, the second PWM signal, and the third PWM signal.

[0106] Therefore, this invention achieves strictly alternating output of three signals and dynamically constant total duty cycle through innovative timer configuration and duty cycle coupling mechanism, fundamentally eliminating the risk of high-level overlap, while simplifying system design and improving color accuracy and energy efficiency.

[0107] See Figure 7 , Figure 7 The flowchart of a third embodiment of the complementary method for three PWM signals of the present invention is shown, which includes:

[0108] S301 sets the timer's counting mode to center-aligned mode;

[0109] S302, initialize the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal is 100%;

[0110] S303 sets the effective level of the second PWM channel to low and the effective levels of the first and third PWM channels to high.

[0111] S304 calculates the first half-cycle comparison value and the second half-cycle comparison value of the first PWM channel, the second PWM channel and the third PWM channel respectively according to the preset formula;

[0112] The specific calculation formula is as follows:

[0113] (1) According to the formula CCR1=D PWM1 ×E, calculate the first pre-compare value CCR1 of the first half-cycle of the first PWM channel; where DPWM1 This is the duty cycle setting value for the first PWM signal, where E is the PWM resolution. Generally, E is set to 100 or 1000, but this is not a limitation and can be set according to the actual situation.

[0114] (2) According to the formula CCR2=D PWM1 ×E, calculate the second pre-compare value CCR2 of the first half cycle of the second PWM channel;

[0115] (3) Calculate the third pre-compare value CCR3 of the first half cycle of the third PWM channel according to the formula CCR3=0;

[0116] (4) Calculate the first post-compare value CCR1 FALL of the second half cycle of the first PWM channel according to the formula CCR1 FALL = 0;

[0117] (5) According to the formula CCR2FALL=D PWM3 ×E, calculate the second post-compare value CCR2FALL of the second half-cycle of the second PWM channel; where, D PWM3 Set the duty cycle value for the third PWM signal;

[0118] (6) According to the formula CCR3FALL=D PWM3 ×E, calculate the third post-compare value CCR3FALL for the second half of the cycle of the third PWM channel;

[0119] like Figure 8 As shown, when the duty cycle setting value D of the first PWM signal is... PWM1 The duty cycle setting value D of the third PWM signal is 33%. PWM3 When the value is 20%, the calculated before-comparison and after-comparison values ​​are as follows:

[0120] The first pre-compare value of the first half-cycle of the first PWM channel is: CCR1 = B'D' = 33% × 100 = 33; the first post-compare value of the second half-cycle of the first PWM channel is: CCR1 FALL = 0; since the first PWM channel is configured to be active high, the first PWM signal is high in segment B'D', low in segment D'A, and low in segment B'C.

[0121] The second pre-compare value for the first half-cycle of the second PWM channel is: CCR2 = B'D' = 33% × 100 = 33; the second post-compare value for the second half-cycle of the second PWM channel is: CCR2FALL = B'E' = 20% × 100 = 20; since the second PWM channel is configured to be active low, the second PWM signal is low in segment B'D', high in segment D'A, low in segment B'E, and high in segment E'C.

[0122] The third pre-compare value of the first half-cycle of the third PWM channel is: CCR3 = 0; the third post-compare value of the second half-cycle of the third PWM channel is: CCR3FALL = B'E' = 20% × 100 = 20; since the third PWM channel is configured to be active high, the third PWM signal is low in segment B'A, high in segment B'E', and low in segment E'C.

[0123] Therefore, by configuring the values ​​of the first half and second half of the comparator registers for each channel using the above method, the three PWM signals can be made complementary.

[0124] S305, real-time acquisition of the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal;

[0125] S306, adjust the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal;

[0126] (1) When the duty cycle setting value of any of the first PWM signal, the second PWM signal and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting value greater than 50% is taken as the first target PWM channel, the PWM channel corresponding to the PWM signal with a duty cycle setting value less than 50% is taken as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with a duty cycle setting value less than 50% is taken as the third target PWM channel; the effective level of the first target PWM channel is adjusted to low level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to high level.

[0127] (2) When the duty cycle settings of the first PWM signal, the second PWM signal and the third PWM signal are all less than or equal to 50%, the effective level of the first PWM channel, the second PWM channel and the third PWM channel remains unchanged.

[0128] S307, calculate the before and after comparison values ​​of the first PWM channel, the second PWM channel and the third PWM channel respectively according to the preset formula;

[0129] The specific calculation formula is as follows:

[0130] (1) According to the formula CCRa=D PWM’ ×E, calculate the first pre-target comparison value CCRa of the first target PWM channel in the first half-cycle; where, D PWM’E is the duty cycle setting value for a PWM signal with a duty cycle setting value of less than 50%. E is the resolution of the PWM. Generally, E is 100 or 1000, but this is not a limitation and can be set according to the actual situation.

[0131] (2) According to the formula CCRb=D PWM’ ×E, calculate the second target comparison value CCRb for the first half cycle of the second target PWM channel;

[0132] (3) Calculate the third target comparison value CCRc of the first half cycle of the third target PWM channel according to the formula CCRc=0;

[0133] (4) According to the formula CCRaFALL=D PWM” ×E, calculate the first post-target comparison value CCRaFALL for the second half-cycle of the first target PWM channel; where, D PWM” The duty cycle setting value for another PWM signal whose duty cycle setting value is less than 50%;

[0134] (5) Calculate the second target comparison value CCRbFALL of the second target PWM channel in the second half cycle according to the formula CCRbFALL=0;

[0135] (6) According to the formula CCRcFALL=D PWM” ×E, calculate the third post-target comparison value CCRcFALL of the second half cycle of the third target PWM channel;

[0136] like Figure 9 As shown, when the duty cycle setting value of the first PWM signal is greater than 50% (the duty cycle setting value of the second PWM signal is D...), PWM’ The duty cycle setting value D for the third PWM signal is 15%. PWM” (25%), the first PWM channel is configured to be active low, and the second and third PWM channels are configured to be active high. The calculated before-compare and after-compare values ​​are as follows:

[0137] CCR1 = CCRa = B'D' = 15

[0138] CCR2=CCRb=B'D'=15

[0139] CCR3 = CCRc = 0

[0140] CCR1 FALL=CCRaFALL=B'E'=25

[0141] CCR2FALL = CCRbFALL = 0

[0142] CCR3FALL=CCRcFALL=B'E'=25

[0143] As can be seen from the above, this invention can be implemented using a common M0 microcontroller. This invention, through a hardware timer, can achieve strict alternation and dynamic coordinated control of three PWM signals, possessing the following core advantages:

[0144] (1) Zero overlap risk, ensuring circuit safety and color mixing accuracy;

[0145] (2) Simplifies system design, reduces MCU resource consumption and external circuits, and has a relatively low cost;

[0146] (3) Hardware implementation avoids the risk of software jitter, and the high PWM output frequency ensures stable RGB lighting brightness.

[0147] Accordingly, the present invention also discloses a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-mentioned complementary method of three PWM signals.

[0148] Meanwhile, the present invention also discloses a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned complementary method of the three PWM signals.

[0149] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for complementing three PWM signals, characterized in that, include: Set the timer's counting mode to center-aligned mode, and divide the timer's counting period into a first half period and a second half period. The first, second, and third PWM channels are initialized with their first half-cycle pre-compare values, second half-cycle post-compare values, and valid levels to make the first PWM signal of the first PWM channel, the second PWM signal of the second PWM channel, and the third PWM signal of the third PWM channel complementary. The steps of initializing the valid levels of the first, second, and third PWM channels include: setting the valid level of the second PWM channel to a first level; and setting the valid levels of the first and third PWM channels to a second level. Wherein, when the first level is high, the second level is low; and when the first level is low, the second level is high. When initializing the first half-cycle's front comparison value and the second half-cycle's back comparison value of the first, second, and third PWM channels, the duty cycle settings of the first, second, and third PWM signals are initialized so that the duty cycle settings of the first, second, and third PWM signals are all less than 50%, and the sum of the duty cycle settings of the first, second, and third PWM signals is 100%. The duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are acquired in real time. The first PWM signal, the second PWM signal, and the third PWM signal are adjusted in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal, so that the first PWM signal, the second PWM signal, and the third PWM signal are complementary. The step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal includes: when the duty cycle setting of any one of the first PWM signal, the second PWM signal, and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting greater than 50% is designated as the first target PWM channel, the PWM channel corresponding to a PWM signal with a duty cycle setting less than 50% is designated as the second target PWM channel, and the PWM channel corresponding to another PWM signal with a duty cycle setting less than 50% is designated as the third target PWM channel; the effective level of the first target PWM channel is adjusted to a first level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to a second level. When the first level is high and the second level is low, the steps of adjusting the before and after comparison values ​​of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal include: according to the formula CCRa=(T / 2-D PWM’ )×E, calculate the first target comparison value CCRa of the first target PWM channel in the first half cycle; according to the formula CCRb=(T / 2-D PWM’ Calculate the second target comparison value CCRb for the first half-cycle of the second target PWM channel according to the formula CCRc=(T / 2)×E; calculate the third target comparison value CCRc for the first half-cycle of the third target PWM channel according to the formula CCRc=(T / 2-D)×E; PWM” Calculate the first post-target comparison value CCRbFALL for the second half-cycle of the first target PWM channel according to the formula CCRbFALL=(T / 2)×E; calculate the second post-target comparison value CCRbFALL for the second half-cycle of the second target PWM channel according to the formula CCRbFALL=(T / 2-D)×E; calculate the second post-target comparison value CCRbFALL for the second half-cycle of the second target PWM channel according to the formula CCRbFALL=(T / 2-D)×E. PWM” )×E, calculate the third post-target comparison value CCRcFALL of the second half-cycle of the third target PWM channel; where T is 100%, D PWM’ For a PWM signal with a duty cycle setting value less than 50%, D PWM” The duty cycle setting value is for another PWM signal with a duty cycle setting value less than 50%, where E is the resolution of the PWM.

2. The method for complementing three PWM signals as described in claim 1, characterized in that, When the first level is high and the second level is low, the steps for initializing the first half-cycle's front comparison value and the second half-cycle's back comparison value of the first PWM channel, the second PWM channel, and the third PWM channel include: According to the formula CCR1=(T / 2-D) PWM1 )×E, calculate the first pre-compare value CCR1 of the first half-cycle of the first PWM channel; According to the formula CCR2=(T / 2-D) PWM1 )×E, calculate the second pre-compare value CCR2 of the first half cycle of the second PWM channel; The third pre-compare value CCR3 of the first half cycle of the third PWM channel is calculated according to the formula CCR3=(T / 2)×E. Calculate the first post-compare value CCR1FALL of the second half cycle of the first PWM channel according to the formula CCR1FALL=(T / 2)×E; According to the formula CCR2FALL=(T / 2-D) PWM3 )×E, calculate the second post-compare value CCR2FALL of the second half-cycle of the second PWM channel; According to the formula CCR3FALL=(T / 2-D) PWM3 )×E, calculate the third post-compare value CCR3FALL of the second half cycle of the third PWM channel; Where T is 100%, D PWM1 D sets the duty cycle value for the first PWM signal. PWM3 This sets the duty cycle value for the third PWM signal, where E is the PWM resolution.

3. The method for complementing three PWM signals as described in claim 1, characterized in that, When the first level is low and the second level is high, the steps for initializing the first PWM channel, the second PWM channel, and the third PWM channel's first half-cycle front comparison value and second half-cycle back comparison value include: According to the formula CCR1=D PWM1 ×E, calculate the first pre-compare value CCR1 of the first half-cycle of the first PWM channel; According to the formula CCR2=D PWM1 ×E, calculate the second pre-compare value CCR2 of the first half cycle of the second PWM channel; According to the formula CCR3=0, calculate the third pre-compare value CCR3 of the first half cycle of the third PWM channel; Calculate the first post-compare value CCR1FALL of the second half cycle of the first PWM channel according to the formula CCR1FALL=0; According to the formula CCR2FALL=D PWM3 ×E, calculate the second back-compare value CCR2FALL for the second half-cycle of the second PWM channel; According to the formula CCR3FALL=D PWM3 ×E, calculate the third post-compare value CCR3FALL for the second half of the cycle of the third PWM channel; Among them, D PWM1 D sets the duty cycle value for the first PWM signal. PWM3 This sets the duty cycle value for the third PWM signal, where E is the PWM resolution.

4. The method for complementing three PWM signals as described in claim 1, characterized in that, The steps of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal include: When the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel remain unchanged.

5. The method for complementing three PWM signals as described in claim 1, characterized in that, When the first level is low and the second level is high, the steps of adjusting the before and after comparison values ​​of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal include: According to the formula CCRa=D PWM’ ×E, calculate the first target comparison value CCRa of the first target PWM channel in the first half cycle; According to the formula CCRb=D PWM’ ×E, calculate the second target comparison value CCRb for the first half cycle of the second target PWM channel; According to the formula CCRc=0, calculate the third target comparison value CCRc of the first half cycle of the third target PWM channel; According to the formula CCRaFALL=D PWM” ×E, calculate the first post-target comparison value CCRaFALL of the second half cycle of the first target PWM channel; Calculate the second target comparison value CCRbFALL for the second half-cycle of the second target PWM channel according to the formula CCRbFALL=0; According to the formula CCRcFALL=D PWM” ×E, calculate the third post-target comparison value CCRcFALL of the second half cycle of the third target PWM channel; Among them, D PWM’ For a PWM signal with a duty cycle setting value less than 50%, D PWM” The duty cycle setting value is for another PWM signal with a duty cycle setting value less than 50%, where E is the resolution of the PWM.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the complementary method of the three-channel PWM signals as described in any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the complementary method for the three PWM signals as described in any one of claims 1 to 5.

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