Signal quality optimization method, mainboard, computer and storage medium

Abstract

This application relates to the field of computer technology and discloses a method for optimizing the signal quality of an input / output link, a computer, and a storage medium. The method includes: acquiring current device information of a currently connected external device to the motherboard's input / output interface; if it is determined that the current external device is different from a historical external device and that the current external device has the function of communicating with the motherboard, then sending a first analog signal to the signal transmitting end of the motherboard's input / output link; performing analog-to-digital conversion on the second analog signal received by the signal receiving end of the input / output link using a high-speed analog-to-digital conversion module to obtain a digital signal; based on the first analog signal and the digital signal, if it is determined that the signal quality of the input / output link needs to be optimized, then normalizing and superimposing the digital signal to obtain a first eye diagram; and adjusting parameters based on the first eye diagram. Through the above method, this application can optimize the signal quality of the input / output link without relying on the internal components of the PCH.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an input / output link signal quality optimization method, a motherboard, a computer, and a storage medium. Background Technology

[0002] Devices connected to a computer via its input / output interface are called external devices. Once connected, external devices can communicate with the computer. Data transmission between external devices and the computer is primarily achieved through the computer's input / output links. However, the signal quality of these links affects the accuracy of the transmitted data. Poor signal quality can lead to data distortion and a higher bit error rate.

[0003] Therefore, to avoid data distortion during input / output link transmission, it is necessary to ensure that the signal quality of the input / output links meets requirements. When the signal quality of the input / output links is poor, it needs to be optimized to ensure accurate data transmission. Currently, there is a lack of a widely applicable signal quality optimization method for input / output links. Summary of the Invention

[0004] In view of the above problems, this application provides an input / output link signal quality optimization method, a motherboard, a computer, and a storage medium to solve the problem of the lack of a widely applicable input / output link signal quality optimization method in the prior art.

[0005] According to one aspect of the embodiments of this application, an input / output link signal quality optimization method is provided, applied to a motherboard including a high-speed analog-to-digital conversion module. The method includes: in response to an operation to start the motherboard, acquiring current device information of a currently connected external device currently connected to the motherboard's input / output interface; comparing the historical device information of a historical external device acquired during the last startup of the motherboard with the current device information to determine whether the current external device is the same as the historical external device; if the current external device is different from the historical external device, determining whether the current external device has the function of communicating with the motherboard based on the current device information; if the current external device has the function of communicating with the motherboard, sending a signal to the motherboard's input / output interface. The output link's signal transmitting end sends a first analog signal; the high-speed analog-to-digital converter performs analog-to-digital conversion on the second analog signal received by the input / output link's signal receiving end to obtain a digital signal. The second analog signal is the signal that, after being transmitted from the first analog signal to the current external device via the input / output interface, is returned to the input / output test link via the input / output interface. Based on the first analog signal and the digital signal, it is determined whether the signal quality of the input / output link needs optimization. If optimization is required, the digital signal is normalized and superimposed to obtain a first eye diagram. Parameters are adjusted based on the first eye diagram to optimize the signal quality of the input / output link.

[0006] In one alternative approach, determining whether signal quality optimization of the input / output link is required based on the first analog signal and the digital signal includes: determining bit error rate, eye diagram width variation, duty cycle distortion, and equalization-based signal center drift based on the first analog signal and the digital signal; if at least one of the bit error rate, eye diagram width variation, duty cycle distortion, and equalization-based signal center drift is abnormal, then it is determined that signal quality optimization of the input / output link is required.

[0007] In one alternative approach, adjusting the parameters based on the first eye diagram includes: determining the parameters to be adjusted from the pre-emphasis coefficient, deemphasis coefficient, continuous-time linear equalizer adjustment value, calibration delay, gain adjustment amount, and bias adjustment amount of the input / output link register based on the first eye diagram and the abnormal value of the abnormal indicator; and adjusting the parameters to be adjusted.

[0008] In one optional approach, adjusting the parameters according to the first eye diagram includes: determining a first value from a first interval using a bisection method based on the first eye diagram, and adjusting the parameters to the first value; wherein the first interval is determined by the following steps: selecting a plurality of second values ​​from a preset second interval; setting the parameters to each of the plurality of second values ​​respectively, and determining the second eye diagram corresponding to each of the second values; and determining the first interval based on the second eye diagram.

[0009] In one alternative approach, before obtaining the current device information of the currently connected external device currently connected to the input / output interface of the motherboard, the method further includes: obtaining the current state of an optimization switch; if the current state is in an on state, then performing the step of obtaining the current device information of the currently connected external device currently connected to the input / output interface of the motherboard and subsequent steps; if the current state is in a off state, then not performing the step of obtaining the current device information of the currently connected external device currently connected to the input / output interface of the motherboard and subsequent steps.

[0010] In one alternative approach, after adjusting the parameters according to the first eye diagram, the method further includes: determining whether a preset condition is met; if the preset condition is not met, proceeding to the step of sending a first analog signal to the signal transmitting end of the input / output link of the motherboard.

[0011] In one alternative approach, the preset conditions include either the number of times the step of adjusting parameters according to the first eye diagram is performed reaches a threshold or the eye diagram after adjusting the parameters meets the requirements.

[0012] According to another aspect of the embodiments of this application, a motherboard is provided, including a high-speed analog-to-digital conversion module. The motherboard further includes a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the input / output link signal quality optimization method as described above.

[0013] According to another aspect of the embodiments of this application, a computer is provided, including a motherboard as described above.

[0014] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the input / output link signal quality optimization method as described above.

[0015] In this embodiment, by utilizing a high-speed analog-to-digital converter (ADC) module instead of relying on the low-precision ADC module within the Platform Controller Hub (PCH), a high-precision digital signal can be obtained. This allows for more refined link signal quality detection based on the high-precision digital signal and the first analog signal, improving test reliability and thus enhancing the effectiveness and efficiency of input / output link signal quality optimization. Furthermore, since this application optimizes the signal quality of the input / output link without relying on devices within the PCH, its applicability is improved.

[0016] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0017] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1 A flowchart illustrating the input / output link signal quality optimization method provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of the motherboard structure provided in an embodiment of this application is shown;

[0020] Figure 3 A schematic diagram of a computer provided in an embodiment of this application is shown. Detailed Implementation

[0021] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein.

[0022] High-speed I / O (HSIO) is a high-speed input / output interface technology designed to enable high-speed data transfer between chips or devices. It meets the needs of high-performance computing, network communication, and storage scenarios by optimizing hardware design, increasing interface bandwidth, and improving signal transmission methods. High-speed I / O interfaces include, but are not limited to, Peripheral Component Interconnect Express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, SATA (Serial Advanced Technology Attachment) interfaces, and various high-speed network interfaces.

[0023] Existing HSIO tuning solutions primarily rely on the ADC sampler and digital pattern generator integrated within the PCH to test and optimize input / output link signals. However, not all platforms (especially domestic platforms, consumer-grade motherboards, or earlier architectures) support these modules. Furthermore, the ADCs integrated within the PCH typically have small bit widths (e.g., 6-8 bits) and low sampling rates, making it difficult to accurately reproduce eye diagrams and signal waveform details, affecting bit error rate and signal quality assessment. Moreover, access to the internal test logic is restricted, preventing developers from freely controlling key parameters such as sampling frequency, delay, and excitation waveforms, making debugging difficult. Simultaneously, the algorithms used for parameter adjustment in the Basic Input Output System (BIOS) firmware are usually closed, fixed logic flows, not supporting pluggable algorithm optimization and struggling to adapt to the customized needs of different platforms. The tuning process and analysis results are usually not accessible to users, lacking tuning logs and graphical representations, making it difficult for users / developers to assess tuning quality and identify problems. Some non-standard designs or third-party motherboard chipset solutions (such as non-Intel platforms or embedded devices) cannot use existing tuning mechanisms, lacking universality.

[0024] Furthermore, while dedicated signal tuning equipment can be used to perform detailed measurements and analysis of HSIO signals to adjust signal parameters for optimal performance, such equipment typically includes high-precision oscilloscopes and bit error rate testers. This equipment is expensive, complex to operate, and requires professional technicians for debugging and maintenance. Therefore, there is an urgent need for a solution that can achieve high-precision and highly flexible automatic HSIO tuning without relying on PCH internal resources, simply by setting up relevant hardware modules on the computer motherboard.

[0025] Based on this, this application proposes an input / output link signal quality optimization method, applied to a motherboard including a high-speed analog-to-digital converter (ADC). During the motherboard startup phase, it is determined whether the currently connected external device is the same as the historical external device connected to the motherboard during the last startup. If they are different and the current external device has communication capabilities, a first analog signal is sent to the signal transmitting end of the input / output link. After the first analog signal is transmitted to the external device through the input / output interface and returned to the input / output link, the second analog signal received by the signal receiving end of the input / output link is converted from analog to digital by the high-speed ADC to obtain a digital signal. Based on the first analog signal and the digital signal, it is determined whether the signal quality of the input / output link needs to be optimized. If optimization is needed, the signal quality of the input / output link is optimized based on the digital signal. This method enables input / output link optimization without relying on devices integrated within the PCH, offering strong applicability.

[0026] Figure 1 This diagram illustrates a flowchart of an input / output link signal quality optimization method provided in an embodiment of this application. The method is executed by a motherboard including a high-speed analog-to-digital conversion module. This motherboard can be a motherboard in a server, computer, or other device. The motherboard can also be a motherboard including one or more processors. The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of this invention; no limitation is made here. The one or more processors included in the motherboard can be processors of the same type, such as one or more CPUs; or they can be processors of different types, such as one or more CPUs and one or more ASICs; no limitation is made here. Figure 1 As shown, the method includes the following steps:

[0027] Step 110: In response to the motherboard startup operation, obtain the current device information of the currently connected external devices that are currently connected to the motherboard's input / output interfaces.

[0028] Once the external device is connected to the motherboard, the motherboard can read the device information. This device information includes the device type and model. Different types and models of devices have different device information. In this step, obtaining the current device information of the current external device is to determine its type and model. Preferably, to facilitate subsequent use of this current device information, it is stored in the motherboard's registers after being obtained.

[0029] Step 120: Compare the historical device information of the external devices obtained during the last motherboard startup with the current device information to determine whether the current external device is the same as the historical external device. If yes, end this process; otherwise, proceed to step 130.

[0030] The HSIO register is a key component in the PCH used for configuring and managing high-speed input / output interfaces. It controls the electrical characteristics and communication protocol parameters associated with high-speed interfaces such as PCIe, SATA, and USB. By writing to the HSIO register, signal transmission rates, voltages, clock recovery mechanisms, and other parameters can be adjusted to optimize signal transmission quality. The HSIO register can adjust the drive voltage and current intensity of signals. Inappropriate voltage or current settings may result in signals that are too strong or too weak, affecting signal integrity.

[0031] Different external devices have different requirements for the parameters of the HSIO registers. For example, high-performance solid-state drives (SSDs) may require higher transfer rates and more stringent clock synchronization, while ordinary USB devices have lower parameter requirements. When the HSIO register parameters are not set correctly, signal quality deteriorates, which may lead to an increased bit error rate, manifesting as data transmission interruptions or speed reduction. In other words, a set of HSIO register parameters cannot be used for different external devices.

[0032] Since the external devices connected to the motherboard are determined based on user needs, these devices may change; that is, the external devices connected to the motherboard may differ at different times. When the external device changes, the parameters of the HSIO register need to be adjusted promptly so that the adjusted parameters are compatible with the current external device connected to the motherboard. Therefore, preferably, the user should execute the following after each motherboard startup: Figure 1 In the provided embodiment, if the external device changes (i.e., the determination result in step 120 is negative), the process proceeds to step 130 to further determine whether the parameters of the HSIO register need to be adjusted. If the parameters of the HSIO register need to be adjusted, they are adjusted promptly to ensure that the parameters of the HSIO register are compatible with the current external device connected to the motherboard. If the external device does not change (i.e., the determination result in step 120 is positive), there is no need to adjust the parameters of the HSIO register, and therefore the process ends directly.

[0033] As described in step 110, since the device information is stored in the register when step 110 is executed, the device information obtained when step 110 was executed last time is the historical device information of the historical external device. Therefore, in this step, the historical device information can be obtained from the register and compared with the current device information obtained when step 110 is executed this time, so as to determine whether the current external device is the same as the historical external device.

[0034] Step 130: Determine whether the current external device has the function of communicating with the motherboard based on the current device information. If not, end this process; if yes, proceed to step 140.

[0035] The motherboard's input / output interfaces not only handle data transmission but also power external devices. For example, the motherboard's power supply module can power external devices via a USB interface. Therefore, this step first determines whether the external device has the capability to communicate with the motherboard. If the external device does not have this capability, there is no need to optimize the signal quality of the input / output link; that is, if the result of this step is negative, the process ends. For example, if the external device is a fan, and the motherboard powers the fan via USB, since the fan does not have communication capabilities, the motherboard and fan will not transmit data through the input / output link. Therefore, there is no need to perform the subsequent steps to optimize the signal quality of the input / output link, and the process ends directly. If the external device does have the capability to communicate with the motherboard, the subsequent input / output link signal quality optimization process continues.

[0036] Step 140: Send the first analog signal to the signal transmitting end of the input / output link of the motherboard.

[0037] The first analog signal is a test signal, such as PRBS7 / 15 / 31, a specific jitter waveform, or a signal for low-speed to high-speed switching modes. After receiving the first analog signal, the signal transmitter of the input / output link sends it to the current external device. After receiving the signal, the current external device returns it to the signal receiver of the input / output link. For ease of distinction, in this embodiment, the analog signal received by the signal receiver of the input / output link is defined as the second analog signal.

[0038] In some embodiments, to overcome the problem of insufficient internal PCH resources, a dedicated test module can be added to the motherboard. This module is independent of the PCH's internal analog-to-digital converter module and digital mode generator. This module may include a programmable excitation circuit and a unit for implementing link loopback functionality. The programmable excitation circuit is capable of injecting a test signal (i.e., a first analog signal) of a predetermined test mode (such as PRBS7 / 15 / 31, a specific jitter waveform, and a low-speed to high-speed switching mode) into the target HSIO link. The unit for implementing link loopback functionality is integrated in a dedicated SerDes or buffer, which supports closed-loop testing. The BIOS communicates with this module via MMIO or I2C / LPC bus to configure excitation parameters and initiate test signal output in real time. Compared to conventional solutions that rely on internal PCH functions, this embodiment of the application, by setting up this module, can achieve greater flexibility and adjustability, supporting more complex test modes and extended test scenarios.

[0039] Step 150: The second analog signal received by the signal receiver of the input-output link is converted into a digital signal by a high-speed analog-to-digital converter.

[0040] After acquiring the second analog signal, the high-speed analog-to-digital converter module converts it into a high-precision digital waveform, which is then uploaded to a reserved buffer in the BIOS memory via SPI, I2C, or a custom USB interface. The sampling time window can cover thousands to tens of thousands of bits to ensure sufficient link characteristic data is captured.

[0041] Step 160: Based on the first analog signal and the digital signal, determine whether the signal quality of the input / output link needs to be optimized. If not, end this process; if yes, proceed to step 170.

[0042] Specifically, it can be determined whether the signal quality of the input and output links needs to be optimized through the following steps a1 to a2.

[0043] Step a1: Based on the first analog signal and the digital signal, determine the bit error rate, eye diagram width change, duty cycle distortion, and signal center drift after equalization.

[0044] Specifically, by comparing the digital signal obtained in step 150 with the digital signal corresponding to the first analog signal, the bit error rate, duty cycle distortion, and equalization signal center drift can be determined.

[0045] The high-speed analog-to-digital converter (ADC) performs analog-to-digital conversion on the analog differential signal received at the signal receiver of the input / output link, thus obtaining a series of digital samples (i.e., digital signals). An eye diagram is a graph formed by superimposing digital signal waveforms from multiple bit periods. Here, "superimposition" refers to overlaying or accumulating the normalized sampled waveforms corresponding to multiple consecutive bit periods (Unit Interval, UI) on the same time axis. Eye diagram width variation refers to the change in the horizontal opening (eye width) of the eye diagram over time or under varying conditions.

[0046] Step a2: If at least one of the following abnormal indicators is present: bit error rate, eye diagram width variation, duty cycle distortion, and signal center drift after equalization, then it is determined that the signal quality of the input and output links needs to be optimized.

[0047] If at least one of the following indicators—bit error rate, eye diagram width change, duty cycle distortion, and signal center drift after equalization—exceeds the preset standard (indicators exceeding the preset standard are considered abnormal indicators), it indicates that the signal quality of the current input / output link is substandard, and therefore the signal quality of the link needs to be optimized.

[0048] Step 170: Normalize and superimpose the digital signal to obtain the first eye diagram.

[0049] As mentioned earlier, the first eye diagram can be obtained by overlaying or accumulating the normalized sampled waveforms corresponding to multiple consecutive bit periods (Unit Interval, UI) on the same time axis.

[0050] It's worth noting that after acquiring the digital signal, an eye diagram can be constructed based on bit positioning and jitter accumulation. After the high-speed analog-to-digital converter obtains the digital signal within a time window, the BIOS's built-in signal reconstruction module normalizes and superimposes the data to generate an eye diagram. This eye diagram visually reflects the amplitude and timing distribution of the signal within different time windows. The eye diagram mainly includes the following key parameters: Eye Height, representing the vertical gap between the upper and lower edges of the eye diagram, is an indicator of the signal's noise immunity. A larger eye height indicates sufficient noise margin and better signal stability; Eye Width, representing the horizontal width of the opening in the eye diagram, reflects the timing margin of data sampling. Insufficient eye width may lead to clock errors during data sampling; Rise / Fall Time, i.e., the transition time of the signal from low to high (or vice versa), excessively long transition times may cause signal edge distortion; Jitter, referring to the fluctuation of the signal edges over time, excessive jitter will affect the accuracy of data sampling. The deviations between the actual measured values ​​of these parameters and the preset target values ​​constitute the error signals for subsequent optimization.

[0051] Step 180: Adjust parameters based on the first eye diagram to optimize the signal quality of the input / output links.

[0052] During optimization, the goal is to achieve the optimal eye diagram. First, target eye height and target eye width can be set. Specifically, an ideal eye height and eye width value (i.e., target value) is preset. If the actual measured value is lower than the target value, it indicates insufficient signal quality. Target edge delay and rise / fall time are then set, aiming to make edge transitions as fast and stable as possible to avoid timing ambiguity. Jitter control parameters are set, aiming to control jitter within an acceptable range. If the actual eye height is lower than its corresponding target value, it may be necessary to increase the signal pre-emphasis or gain to increase the signal amplitude, thereby widening the vertical opening of the eye diagram. If the eye width is insufficient, it may be necessary to adjust the clock delay or balance the rise / fall time of the signal to provide a wider sampling window.

[0053] Since the eye diagram is affected by multiple parameters, when performing step 180, the parameters to be adjusted can first be determined from the pre-emphasis coefficient, deemphasis coefficient, continuous-time linear equalizer adjustment value, calibration delay, gain adjustment amount, and bias adjustment amount of the input / output link register based on the first eye diagram and the abnormal values ​​of the abnormal indicators. Then, the parameters to be adjusted are adjusted. Since the eye height of the first eye diagram is related to the gain adjustment amount and bias adjustment amount of the HSIO register, the eye width of the first eye diagram is related to the pre-emphasis coefficient and deemphasis coefficient of the HSIO register, and the area of ​​the first eye diagram is related to the continuous-time linear equalizer adjustment value and calibration delay of the HSIO register, if any of the parameters of the eye height, eye width, and area of ​​the first eye diagram does not match the preset value, then the relevant parameter can be adjusted.

[0054] When adjusting parameters, a first value can be determined from the first interval using the first eye diagram and the bisection method. The parameter to be adjusted is then set to this first value, thereby optimizing the signal quality of the input-output link. The first interval is a pre-determined interval as needed. For example, the midpoint of the first interval can also be used as the first value.

[0055] When adjusting parameters, each adjustment checks whether preset conditions are met. If the preset conditions are not met, the process proceeds to step 140 to continue adjusting the parameters; if the preset conditions are met, the process ends. These preset conditions include either the number of times step 180 is executed reaching a threshold or the eye diagram after parameter adjustment meeting requirements. Since signal quality optimization of the link is typically performed during the motherboard startup phase, in this embodiment, if the eye diagram does not meet requirements when the number of times step 180 is executed reaches the threshold, the process also ends. This avoids excessive time consumption due to multiple parameter adjustments, which could lead to a prolonged motherboard startup phase.

[0056] In some embodiments, an eye diagram is generated and displayed after each parameter adjustment, providing a visual representation of features such as eye height, eye width, opening angle, and trajectory offset, facilitating eye diagram analysis. Furthermore, during multiple parameter adjustments, the required tuning parameters are automatically calculated using PID control algorithms or other optimization algorithms (such as grid search or bisection). After each parameter adjustment and re-determining of the eye diagram, the latest eye diagram is displayed in real time. In this embodiment, because it not only relies on digital error rate statistics but also introduces real-time eye diagram generation as visual feedback, and employs specific algorithms to automatically explore the parameter space, fine-tuning is achieved, significantly improving the overall signal tuning accuracy.

[0057] To determine a more accurate first interval and improve the efficiency of optimizing the signal quality of the input / output links, the first interval is preferably determined by the following steps b1 to b4.

[0058] Step b1: Select multiple second values ​​from the preset second interval.

[0059] Taking the parameter to be adjusted as an example, the second interval is the allowable adjustment range of the parameter. The second value can be a typical value, such as the minimum, median, or maximum value in the second interval. Here, we will use the parameter to be adjusted as p as an example. If the allowable adjustment range of p is [L, U] (assuming the range is [-4dB, 0dB]), then in this step, we can determine multiple second values ​​as -4dB, -3dB, -2dB, and -1dB.

[0060] Step b2: Set the parameter to each of the multiple second values, and determine the corresponding second eye diagram when the parameter is set to each of the second values.

[0061] After setting the parameter to be adjusted to one of the second values, the second eye diagram after setting the parameter to the second value can be determined. The method for determining the second eye diagram can be found in steps 140-170, and will not be repeated here. By setting the parameter to be adjusted one by one to each of the various second values, the corresponding second eye diagram for each value can be determined.

[0062] Step b3: Determine the first interval based on the second eye diagram.

[0063] In this step, one can select the second eye diagram that best meets the requirements from the multiple second eye diagrams determined in step b2, and then determine the first interval based on this second eye diagram, with the second value corresponding to the second eye diagram being the midpoint of the determined first interval. The range of the first interval is smaller than that of the second interval.

[0064] Alternatively, an objective function E(p) can be established (e.g., a combination of indicators such as eye diagram opening index and bit error rate). This objective function reflects the impact of parameter p on system performance, thereby guiding the subsequent search of the first interval. The best-performing second eye diagram (i.e., the second eye diagram that best meets the requirements) is selected from multiple second eye diagrams. If the second value corresponding to the best-performing second eye diagram is -2dB, it means that the link performance is best when p is around -2dB. Therefore, the near-optimal region is likely to be [-2.5, -1.5], that is, the first interval is [-2.5, -1.5].

[0065] Then, the parameter p is further adjusted to the midpoint M1 of the first interval [L1, U1] and its nearest points (e.g., (L1+M1) / 2, (M1+U1) / 2). Eye diagrams are then determined for each of these settings, and the objective function value E corresponding to each of the above values ​​for parameter p is recorded. The objective function values ​​E are compared, and the best-performing eye diagram is selected based on the comparison results. The first interval is then narrowed based on the parameter p corresponding to the best-performing eye diagram. The above steps are repeated to gradually narrow the interval where parameter p is optimal, thus allowing for a more accurate determination of the first value from the finally determined, smaller first interval.

[0066] It is worth noting that, as mentioned earlier, the eye diagram is affected by multiple parameters. Therefore, if a certain indicator of the eye diagram is affected by multiple parameters at the same time, an alternating optimization method can be used when adjusting the parameters. That is, fix other parameters, perform adaptive search on only one parameter at a time, and then switch to the next parameter, iterating repeatedly until the overall objective function converges to the ideal state.

[0067] In this embodiment, by utilizing a high-speed analog-to-digital converter (ADC) module instead of relying on the low-precision ADC module within the PCH, a high-precision digital signal can be obtained. This allows for more refined link signal quality detection based on the high-precision digital signal and the first analog signal, improving test reliability and thus enhancing the effectiveness and efficiency of input / output link signal quality optimization. Furthermore, since this application optimizes the signal quality of the input / output link without relying on devices within the PCH, its applicability is improved.

[0068] Since the optimization of input / output link signal quality is completed during the motherboard startup phase, the efficiency of this optimization directly affects the motherboard startup efficiency. To improve motherboard startup efficiency, in this embodiment, during the execution... Figure 1 Before providing the embodiments, the following steps c1 to c2 are performed first.

[0069] Step c1: Obtain the current state of the optimization switch.

[0070] The optimization switch can be a physical switch or a virtual switch implemented in software. Users can set the state of the optimization switch based on whether the external device changes. If the external device changes and optimization of the input / output link signal quality is required, the optimization switch can be set to the "on" state; if the external device does not change or does not have the function of communicating with the motherboard, and optimization of the input / output link signal quality is not required, the optimization switch can be set to the "off" state.

[0071] Step c2: Determine if the current state is open. If yes, proceed to step 110. If no, end this process.

[0072] If the current state is open, it means that execution is required. Figure 1 The provided embodiments optimize the signal quality of the input / output links; if the previous state was off, it means that no action is required. Figure 1 In the provided embodiments, if there is no need to optimize the signal quality of the input / output links, then this process ends.

[0073] In this embodiment of the application, by setting an optimization switch, during execution... Figure 1 Before providing the implementation, the current state of the optimization switch is determined. Execution is only performed if the current state is "on". Figure 1 The provided embodiments can meet user needs and avoid performing operations when there is no need to optimize the signal quality of the input / output links. Figure 1 The provided embodiment results in an excessively long motherboard startup phase.

[0074] Figure 2 The diagram shows a structural schematic of a motherboard provided in an embodiment of this application. The specific implementation of the motherboard in this application is not limited.

[0075] like Figure 2 As shown, the motherboard may include: a processor 202, a memory 204, and a high-speed analog-to-digital converter 208.

[0076] The memory 204 is used to store the computer program 206. The memory 204 may include high-speed RAM, and may also include non-volatile memory, such as at least one disk storage device. The computer program 206 may include computer-executable instructions.

[0077] Processor 202 executes computer program 206 to implement the above-described input / output link signal quality optimization embodiment. Processor 202 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The motherboard 200 includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0078] Figure 3 The illustration shows a schematic diagram of a computer provided in an embodiment of this application. The specific embodiments of this application do not limit the specific implementation of the computer. Figure 3 As shown, computer 10 includes motherboard 200.

[0079] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described input / output link signal quality optimization method embodiment.

[0080] This application provides a computer program that can be executed by a processor to implement the above-described input / output link signal quality optimization method embodiment.

[0081] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described input / output link signal quality optimization method embodiment.

[0082] In the several embodiments provided in this application, any function, if implemented as a software functional module / unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the technical solution of this application can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or other electronic device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0083] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, the embodiments of this application are not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application.

[0084] It should be noted that the above embodiments are illustrative of this application and not restrictive, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In claims enumerating several means, several units or modules of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for optimizing the signal quality of an input / output link, characterized in that, Applied to a motherboard including a high-speed analog-to-digital conversion module, the method includes: In response to the operation of starting the motherboard, obtain the current device information of the currently connected external device that is currently connected to the input / output interface of the motherboard; The historical device information of the external devices obtained when the motherboard was last started is compared with the current device information to determine whether the current external device is the same as the historical external device. If the current external device is different from the historical external device, then determine whether the current external device has the function of communicating with the motherboard based on the current device information; If the current external device has the function of communicating with the motherboard, then a first analog signal is sent to the signal transmitting end of the input / output link of the motherboard; The high-speed analog-to-digital conversion module performs analog-to-digital conversion on the second analog signal received at the signal receiving end of the input-output link to obtain a digital signal. The second analog signal is the signal that was transmitted from the first analog signal to the current external device through the input-output interface and then returned to the input-output test link by the input-output interface. Based on the first analog signal and the digital signal, determine whether it is necessary to optimize the signal quality of the input-output link; If it is necessary to optimize the signal quality of the input-output link, the digital signal is normalized and superimposed to obtain the first eye diagram; The parameters are adjusted based on the first eye diagram to optimize the signal quality of the input / output link.

2. The method according to claim 1, characterized in that, The step of determining whether the signal quality of the input-output link needs to be optimized based on the first analog signal and the digital signal includes: Based on the first analog signal and the digital signal, determine the bit error rate, eye diagram width change, duty cycle distortion, and equalization signal center drift; If at least one of the following abnormal indicators exists: bit error rate, eye diagram width variation, duty cycle distortion, and equalization signal center drift, then it is determined that the signal quality of the input / output link needs to be optimized.

3. The method according to claim 2, characterized in that, The step of adjusting parameters according to the first eye diagram includes: Based on the first eye diagram and the abnormal values ​​of the abnormal indicators, the parameters to be adjusted are determined from the pre-emphasis coefficient, deemphasis coefficient, continuous-time linear equalizer adjustment value, calibration delay, gain adjustment amount, and bias adjustment amount of the input / output link register. Adjust the parameter to be adjusted.

4. The method according to claim 1, characterized in that, The step of adjusting parameters according to the first eye diagram includes: Based on the first eye diagram, a first value is determined from the first interval using the bisection method, and the parameter is adjusted to the first value; The first interval is determined through the following steps: Select multiple second values ​​from the preset second interval; The parameter is set to each of the plurality of second values, and the second eye diagram corresponding to each of the parameter values ​​is determined. The first interval is determined based on the second eye diagram.

5. The method according to claim 1, characterized in that, Before obtaining the current device information of the currently connected external device currently connected to the input / output interface of the motherboard, the method further includes: Get the current state of the optimization switch; If the current state is open, then the step of obtaining the current device information of the currently connected external device currently connected to the input / output interface of the motherboard and subsequent steps are executed. If the current state is closed, then the step of obtaining the current device information of the currently connected external device currently connected to the input / output interface of the motherboard and subsequent steps will not be executed.

6. The method according to claim 1, characterized in that, After adjusting the parameters according to the first eye diagram, the method further includes: Determine whether the preset conditions are met; If the preset conditions are not met, the process proceeds to the step of sending a first analog signal to the signal transmitting end of the input / output link of the motherboard.

7. The method according to claim 6, characterized in that, The preset conditions include the number of times the step of adjusting parameters according to the first eye diagram is performed reaches a threshold, or the eye diagram after adjusting the parameters meets the requirements.

8. A motherboard, comprising a high-speed analog-to-digital converter module, a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the input / output link signal quality optimization method as described in any one of claims 1 to 7.

9. A computer, characterized in that, The computer includes the motherboard as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the input / output link signal quality optimization method according to any one of claims 1 to 7.

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