A method and system for multi-lane communication synchronization based on high-speed serial bus

Abstract

The application discloses a kind of multi-channel communication synchronization method and system based on high-speed serial bus, wherein synchronization method includes using multi-channel high-speed serial bus to connect multiple devices respectively to constitute star topology, the communication specification of configuration serializer is made, so that the communication specification of each serializer is consistent and code phase is synchronized;Through bit alignment and frame alignment, the communication link establishment of receiving end and sending end is realized;Wherein, the frame alignment includes measuring the random phase of the recovery clock of receiving end;Synchronization clock is obtained after phase modulation is carried out to the recovery clock of receiving end according to random phase;After receiving end receives command frame, data is converted to synchronous clock domain to process;Wherein, inter-channel synchronization takes sending end reference clock as reference, and the synchronization accuracy is the time corresponding to the inverse of the line rate of high-speed serial bus.The application can reduce the use of wiring resources, facilitate equipment expansion and improve space utilization;At the same time, high data throughput and high synchronization between branch nodes are realized.

Description

Technical Field

[0001] This invention relates to the technical field of multi-channel communication synchronization, and specifically to a multi-channel communication synchronization method and system based on a high-speed serial bus. Background Technology

[0002] With the increasing informatization and integration of electronic devices, multi-module integrated design has become a major development trend. Such devices often employ a topological connection structure; for example, a central node connects to and controls multiple branch nodes via a bus. This approach not only accommodates various functional modules and saves costs but also enables rapid management and response through a unified central node. For instance, in a multi-channel acquisition instrument, the central control console is the central node, and the multi-functional acquisition card is the branch node. The central control console controls the acquisition card via the bus to perform the corresponding acquisition and complete the feedback of sampled data. Furthermore, modern equipment demands increasingly higher time synchronization accuracy from branch nodes, making it applicable in scenarios such as precise synchronous sampling, synchronous imaging, synchronous triggering, and synchronous sampling.

[0003] Existing technologies mostly employ a data bus + synchronization signal line approach to achieve data and synchronization signal transmission. This can be achieved through star or chain topologies to connect the central node to each branch node. The data bus is used for data transmission, while the synchronization signal line ensures synchronization performance. In a star topology, it's generally necessary to ensure that the synchronization signal lines at each branch node are of equal length to achieve high-precision synchronization. When using PCB traces as the bus medium, more trace resources mean a larger board area and a requirement for connectors with more pins when crossing connectors. When using fiber optic cables or twisted-pair cables as the bus medium, the independent data bus and synchronization signal lines require more flywire space and more cables, causing inconvenience for installation and expansion. In a chain topology, the synchronization signal is transmitted within the signal chain, and the signal itself, as an electromagnetic wave, propagates in the medium at a corresponding transmission rate, such as 6 inch / ns in FR4 PCB traces. Therefore, the synchronization performance at the beginning and end of the signal chain increases with the chain length, making high-precision (nanosecond level and above) synchronization impossible. Furthermore, if a chain topology is used for the data bus, it compresses the equivalent data bandwidth of each node, reducing data throughput.

[0004] In summary, there is a need to design a multi-channel communication synchronization method and system based on a high-speed serial bus to solve the aforementioned problems in the prior art. Summary of the Invention

[0005] To address the problems in the prior art, this invention provides a multi-channel communication synchronization method and system based on a high-speed serial bus, which solves the problem of integrated communication synchronization of multiple service channels in multi-channel electronic devices.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A multi-channel communication synchronization method based on a high-speed serial bus includes: A star topology is formed by connecting multiple devices using a multi-channel high-speed serial bus. The communication specifications of the serializers are configured to ensure that the communication specifications of each serializer are consistent and the inter-symbol phase is synchronized. Communication link establishment between the receiver and the transmitter is achieved through bit alignment and frame alignment; wherein, the frame alignment includes measuring the random phase of the receiver's recovery clock; The synchronous clock is obtained by phase modulation of the recovered clock at the receiving end based on the random phase. After receiving the command frame, the receiving end converts the data to the synchronous clock domain for processing. Among them, the synchronization between channels is based on the reference clock of the transmitting end, and the synchronization accuracy is the time corresponding to the reciprocal of the line rate of the high-speed serial bus.

[0007] In some embodiments of the present invention, the frame alignment process includes: The sender and receiver set an idle code; Compare the initial frame data intercepted by the receiving end with the idle code; Determine whether frame alignment has been achieved based on the comparison results.

[0008] In some embodiments of the present invention, determining whether frame alignment has been achieved based on the comparison result includes: Frame alignment is achieved when the initial frame data matches the idle code; When the initial frame data does not match the idle code, the sliding state machine is used to gradually obtain the current frame data by sliding in units of frame data. The current frame data is then compared with the idle code until the current frame data matches the idle code, thus achieving frame alignment.

[0009] In some embodiments of the present invention, the random phase of the recovered clock of the measurement receiver includes: During the process of the sliding state machine performing sliding step to capture frame data to complete frame alignment, the number of sliding steps of the sliding state machine is recorded, and the frame data corresponding to the number of sliding steps is the random phase of the recovery clock.

[0010] In some embodiments of the present invention, obtaining a synchronous clock by phase modulation of the recovered clock at the receiving end includes: A synchronous clock is obtained by adjusting the random phase of the recovered clock using a phase-locked loop or a time delay unit.

[0011] In some embodiments of the present invention, the consistent communication specifications include that the serial signals of multiple serializers have the same baud rate and the same encoding type.

[0012] In some embodiments of the present invention, the bit alignment is achieved by aligning the line rate of the bit stream using the clock data recovery module of the receiving end; at the same time, the reference clock is decoded and deserialized to obtain the recovered clock.

[0013] In some embodiments of the present invention, a multi-channel communication synchronization system based on a high-speed serial bus is provided, comprising: The transmitting end, which is located at the central node, is used to convert parallel multi-bit signals into a serial signal code stream containing a reference clock through an encoder and serializer. The receiving end, which is located at the branch node, is used to lock the received serial signal by the clock data recovery module, perform bit alignment, and convert it into a parallel signal that conforms to the encoded information. A sliding state machine is used to frame align the bit-aligned signal and measure the phase deviation of the recovery clock relative to the reference clock during the frame alignment process. The control module is used to configure the communication specifications of the serializer between the transmitting end and the receiving end.

[0014] In some embodiments of the present invention, the control module is further configured to measure the phase difference between the recovery clock and the reference clock based on the movement step size of the sliding state machine; and to adjust the phase of the recovery clock based on the phase difference measurement result.

[0015] In some embodiments of the present invention, the control module is further configured to perform clock domain switching on subsequent communication data after the transmitting end and the receiving end have established a communication link.

[0016] The technical solution of the present invention has the following technical effects compared with the prior art: This invention achieves communication between the central node and branch nodes in a star topology, as well as synchronization between branch nodes, using only a single high-speed serial bus. This reduces the use of wiring resources, facilitates device expansion, and improves space utilization. At the same time, it achieves high data throughput and high synchronization between branch nodes. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the multi-channel communication synchronization method described in the embodiment.

[0019] Figure 2 This is a schematic diagram of the structure of the transmitter and receiver of the synchronization system in the embodiment. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0025] The following disclosure provides many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0026] Example 1, referring to Figure 1 As shown, a multi-channel communication synchronization method based on a high-speed serial bus includes: Step S1: Use a multi-channel high-speed serial bus to connect multiple devices to form a star topology. In this embodiment, a star topology is used, that is, the distance from each branch node to the central node is the same. Use serializers of the same length to connect the central node and each branch node. While realizing data communication between the central node and the branch nodes, high-precision time synchronization between the branch nodes is also realized.

[0027] Configure the communication specifications of the serializers to ensure that the communication specifications of each serializer are consistent. Multiple high-speed serial code streams emitted by the central node must use the same baud rate, the same encoding type, and be completely synchronized in phase between codes; this can be specifically achieved through FPGA or other chip devices.

[0028] Since all serializers have the same bus physical length, various bus transmission media are used, such as single optical fiber, PCB wiring, coaxial cable, twisted pair, etc.

[0029] The bitstream sent by the central node will arrive at the receiving end of the branch node after the same time delay.

[0030] Step S2: Establish communication link between the receiver and the transmitter through bit alignment and frame alignment; Step S21: The bit alignment is achieved by using the clock data recovery module at the receiving end to align the line rate of the bit stream; at the same time, the reference clock is decoded and deserialized to obtain the recovered clock.

[0031] For example, if the baud rate at both the transmitting and receiving ends is set to 10.3125Gbps and the 64b / 66b encoding standard is used, then the baud rate of 10.3125Gbps is equivalent to a line rate of 10.3125GHz. After decoding at the receiving end, the data rate is 10.3125GHz * 64 / 66 = 10GHz. Deserialization involves reducing the serial data by its bit width to obtain parallel data and simultaneously reducing the clock frequency to facilitate system processing. In the example above, 64b is the parallel data bit width, so the recovered clock frequency after deserialization is 10GHz / 64 = 156.25MHz.

[0032] Specifically, the transmitting end converts the parallel multi-bit signal (the number of bits can vary under different line rates and encoding configurations) into a serial signal code stream containing transmission reference clock information through encoding, serializer, etc.; the line rate of the code stream is N times the transmission reference clock frequency, such as 10 times, 66 times, etc. To ensure signal transmission quality, the general form of the serial signal is differential line pairs. After receiving the RX+ / - signal, the receiver locks it through the clock data recovery module. It can extract the clock frequency information from the edge information of the code stream and complete the bit alignment. The extracted clock frequency is the transmission reference clock frequency. The deserializer converts the bit-synchronized code stream into a parallel signal that conforms to the encoded information.

[0033] The recovery clock is synchronized with the reference clock of the transmitting end, but the phase relationship is random. The bit stream sent by the transmitting end is sent frame by frame in chronological order. Bit alignment cannot guarantee that the bit stream of the whole frame will be aligned, so frame alignment is required.

[0034] Step S22, the frame alignment process includes: S221. The sending and receiving ends set the idle code; Specifically, before establishing a communication link, an idle code is defined in advance using control chips, etc. S222. Compare the initial frame data intercepted by the receiving end with the idle code; the frame data initially intercepted by the deserializer at the receiving end is used as the initial frame data and compared with the preset idle code.

[0035] S223. Determine whether frame alignment has been achieved based on the comparison results.

[0036] When the initial frame data matches the idle code, frame alignment is achieved, and data communication can then proceed. When the initial frame data does not match the idle code, the sliding state machine is used to slide and extract the current frame data with a data step size of 1 bit. The current frame data is then compared with the idle code. If the current frame data matches the idle code, the frame is aligned. If they do not match, the sliding state machine continues to slide and extract the frame data with a data step size of 1 bit. At the same time, the comparison with the idle code continues until the data frame and the idle frame match and the frame alignment is completed.

[0037] Step S224: Measure the random phase of the recovered clock at the receiving end; During the process of the sliding state machine performing sliding step to capture frame data to complete frame alignment, the number of sliding steps of the sliding state machine is recorded, and the frame data corresponding to the number of sliding steps is the phase difference between the reference clock and the recovery clock.

[0038] Step S3: After phase modulation of the recovered clock at the receiving end according to the random phase, a synchronous clock is obtained; Specifically, a synchronous clock is obtained by adjusting the phase difference of the recovered clock through a phase-locked loop or a time delay unit; Since the unit of the sliding step is 1 bit of the serial bit stream, the phase difference accuracy is the time corresponding to the reciprocal of the serializer line rate.

[0039] If the number of phase shifts during a link establishment is 10, then the phase difference due to clock lag is (10 / 66)*(1 / 156.25MHz) = 0.97ns, and the accuracy of this phase measurement result is 1 / 10.3125GHz = 97ps.

[0040] Each branch node can obtain its own synchronization clock.

[0041] Step S4: After receiving the command frame, the receiving end converts the data to the synchronous clock domain for processing. Specifically, after establishing communication and completing phase modulation of the recovery clock, the central node can simultaneously send start command frames to the branch nodes. Upon receiving the command frame, the branch nodes convert the data to the synchronization clock domain and perform the corresponding operations. In this way, multiple branch nodes achieve command reception and synchronous execution, realizing integrated communication synchronization.

[0042] The technical solution of the present invention has the following technical effects compared with the prior art: This invention achieves communication between the central node and branch nodes in a star topology, as well as synchronization between branch nodes, using only a single high-speed serial bus. This reduces the use of wiring resources, facilitates device expansion, and improves space utilization. At the same time, it achieves high data throughput and high synchronization between branch nodes.

[0043] Example 2, refer to Figure 2 As shown, a multi-channel communication synchronization system based on a high-speed serial bus includes: The transmitting end, which is located at the central node, is used to convert parallel multi-bit signals into a serial signal code stream containing a reference clock through an encoder and serializer. The data at the transmitting end is encoded and scrambled before being transmitted through a serializer, equalizer, and driver. The line rate of the serial signal stream is N times the reference clock transmission frequency, such as 10 times, 66 times, etc. To ensure signal transmission quality, the serial signal is generally in the form of differential pairs.

[0044] The receiving end, which is located at the branch node, is used to convert the received serial signal into a parallel signal that conforms to the encoded information after being locked by the clock data recovery module (i.e., CDR) after passing through the receiver and equalizer. A sliding state machine is used to perform frame alignment on bit-aligned signals; and the phase deviation of the recovery clock relative to the transmit reference clock is measured during the frame alignment process. Specifically, the sliding state machine controls the deserializer to slide and capture data frames to achieve frame alignment, and records the number of shifts required to complete frame alignment. The number of slides corresponds to the phase difference between the receiver's recovered clock and the transmitter's reference clock; The control module is used to configure the communication specifications of the serializers of the transmitting end and the receiving end; the consistent communication specifications include that the serial signals of multiple serializers have the same baud rate, the same encoding type, and inter-code phase synchronization; The control module is also used to measure the phase difference between the recovery clock and the transmitting reference clock based on the movement step size of the sliding state machine; and to adjust the phase of the recovery clock based on the phase difference measurement result.

[0045] The control module is also used to switch the clock domain for subsequent communication data after the transmitting end and the receiving end have established a communication link.

[0046] The control module can be an FPGA or a dedicated chip.

[0047] The technical solution of the present invention has the following technical effects compared with the prior art: The central node and branch nodes are connected only through a single high-speed serial bus, requiring less wiring resources, which facilitates equipment expansion and improves space utilization. High-speed serial buses typically have high data baud rates, making them particularly suitable for applications with large data volumes. High synchronization accuracy: Under the premise that the physical length of the high-speed serial bus is the same, the higher the line rate, the higher the synchronization accuracy.

[0048] Example 3: In this example, a computer-readable storage medium is provided, which stores computer-executable instructions. When executed by a processor, the computer-executable instructions are used to implement the synchronization method in Example 1.

[0049] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0050] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0051] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0052] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0053] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0054] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-channel communication synchronization method based on a high-speed serial bus, characterized in that, include: A star topology is formed by connecting multiple devices using a multi-channel high-speed serial bus. The communication specifications of the serializers are configured to ensure that the communication specifications of each serializer are consistent and the inter-symbol phase is synchronized. Communication between the receiver and transmitter is established through bit alignment and frame alignment; the frame alignment process includes: The sender and receiver set an idle code; Compare the initial frame data intercepted by the receiving end with the idle code; Determine whether frame alignment has been achieved based on the comparison results; Frame alignment is achieved when the initial frame data matches the idle code; When the initial frame data does not match the idle code, the sliding state machine is used to gradually slide and capture the current frame data in units of frame data. The current frame data is then compared with the idle code until the current frame data matches the idle code, thus achieving frame alignment. The frame alignment further includes measuring the random phase of the recovery clock at the receiving end: during the process of the sliding state machine performing sliding interception of frame data to complete frame alignment, the number of sliding steps of the sliding state machine is recorded, and the frame data corresponding to the number of sliding steps is the random phase of the recovery clock. The synchronous clock is obtained by phase modulation of the recovered clock at the receiving end based on the random phase. After receiving the command frame, the receiving end converts the data to the synchronous clock domain for processing. Among them, the synchronization between channels is based on the reference clock of the transmitting end, and the synchronization accuracy is the time corresponding to the reciprocal of the line rate of the high-speed serial bus.

2. The multi-channel communication synchronization method based on a high-speed serial bus according to claim 1, characterized in that, The process of obtaining a synchronized clock by phase modulation of the recovered clock at the receiving end includes: A synchronous clock is obtained by adjusting the random phase of the recovered clock using a phase-locked loop or a time delay unit.

3. The multi-channel communication synchronization method based on a high-speed serial bus according to claim 1, characterized in that, The consistent communication specifications include that the serial signals of multiple serializers have the same baud rate and the same encoding type.

4. The multi-channel communication synchronization method based on a high-speed serial bus according to claim 1, characterized in that, The bit alignment is achieved by using the clock data recovery module at the receiving end to align the line rate of the bit stream; at the same time, the reference clock is decoded and deserialized to obtain the recovered clock.

5. A multi-channel communication synchronization system based on a high-speed serial bus, characterized in that, To implement the synchronization method according to any one of claims 1-4, comprising: The transmitting end, which is located at the central node, is used to convert parallel multi-bit signals into a serial signal code stream containing a reference clock through an encoder and serializer. The receiving end, which is located at the branch node, is used to lock the received serial signal by the clock data recovery module, perform bit alignment, and convert it into a parallel signal that conforms to the encoded information. A sliding state machine is used to frame align the bit-aligned signal and measure the phase deviation of the recovery clock relative to the reference clock during the frame alignment process. The control module is used to configure the communication specifications of the serializer between the transmitting end and the receiving end.

6. A multi-channel communication synchronization system based on a high-speed serial bus according to claim 5, characterized in that, The control module is also used to measure the phase difference between the recovery clock and the reference clock based on the movement step size of the sliding state machine; and to adjust the phase of the recovery clock based on the phase difference measurement result.

7. A multi-channel communication synchronization system based on a high-speed serial bus according to claim 5, characterized in that, The control module is also used to switch the clock domain for subsequent communication data after the transmitting end and the receiving end have established a communication link.

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