Test structure, layout and manufacturing method for flash memory

Abstract

The application provides a test structure, a layout and a manufacturing method of a flash memory, comprising a substrate, a plurality of parallel word lines extending along an X direction and a plurality of parallel Y active areas extending along a Y direction. An X active area is arranged between two adjacent Y active areas, and the X active area and the Y active areas on both sides are connected to form an H area. The upper side of the H area comprises a first floating gate at the upper left corner, a second floating gate at the lower left corner, a third floating gate at the upper right corner and a fourth floating gate at the lower right corner. The first floating gate and the second floating gate are connected and led out through a first contact hole; the third floating gate and the fourth floating gate are connected and led out through a second contact hole; one of the first contact hole and the second contact hole is connected to a high voltage, and the other is connected to a low voltage, so that the leakage or breakdown voltage between the floating gates of the two adjacent storage units in the H area can be effectively monitored; problems can be found, and timely rework and rectification can be performed to avoid bit line failure and programming failure.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically relating to a flash memory test structure, layout, and manufacturing method. Background Technology

[0002] Flash memory, due to its advantages of high density, low cost, and electrically programmable and erasable capabilities, has been widely adopted as the optimal choice for non-volatile memory applications. Generally, floating-gate flash memory has similar basic memory cells; they all have a stacked gate structure, which includes a floating gate and at least a control gate covering the floating gate. The control gate is coupled to control the storage and release of electrons in the floating gate.

[0003] Flash memory comprises multiple storage cells arranged in an array, such as Figure 1 As shown, the region with lateral connection between two adjacent columns of active areas is H-shaped and defined as the H region (the region within the blue box). With the increasing miniaturization of semiconductor devices, the spacing between adjacent memory cells also decreases. The floating gates (e.g., FG1 and FG3, FG2 and FG4) of two adjacent columns of memory cells should ideally be regular rectangles. However, the difficulty in controlling the small-size etching process, and the inherent pattern alignment deviations during lithography, can lead to asymmetry in the actual H region (H structure). This results in a tendency for the final floating gate shape to be arc-shaped, potentially causing bridging risks and defects. Between the floating gates (e.g., FG1 and FG3) of two adjacent columns of memory cells is a bowl-shaped dielectric layer. The arc-shaped sharp corners of the first floating gate FG1 and the third floating gate FG3 at the bottom of the bowl are close to being connected. If the first floating gate FG1 and the third floating gate FG3 are connected at their curved corners, on the one hand, the polysilicon of the floating gates will be conductive, causing both the first floating gate FG1 and the third floating gate FG3 to be either connected to or short-circuited with the bit line BL, resulting in the failure of the bit line BL; on the other hand, there will be leakage between the first floating gate FG1 and the third floating gate FG3 of each of the two independent memory cells, leading to programming failure. Currently, there is no effective method to monitor the connection (short circuit) between two adjacent independent floating gate columns within the H region. Summary of the Invention

[0004] The purpose of this invention is to provide a test structure, layout and manufacturing method for flash memory, which can effectively monitor the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region; detect problems, rework and rectify them in time, and avoid bit line BL failure and programming failure.

[0005] This invention provides a test structure for flash memory, comprising:

[0006] The substrate has mutually perpendicular X and Y directions defined in a plane parallel to the substrate.

[0007] Multiple rows of parallel word lines extending along the X direction are located above the substrate, and each row of word lines has stacked floating gates and control gates on both sides along the Y direction;

[0008] Multiple parallel Y-direction active regions extending along the Y direction are located in the substrate. An X-direction active region is disposed between two adjacent columns of Y-direction active regions. The X-direction active regions and the Y-direction active regions of the adjacent regions on both sides are connected to form an H region. The H region includes a first floating gate in a first memory cell located in the upper left corner, a second floating gate in a second memory cell located in the lower left corner, a third floating gate in a third memory cell located in the upper right corner, and a fourth floating gate in a fourth memory cell located in the lower right corner.

[0009] The first floating gate and the second floating gate of two adjacent rows of memory cells in the nth column of the H region are connected to each other and led out through the first contact hole; and the third floating gate and the fourth floating gate of two adjacent rows of memory cells in the (n+1)th column of the H region are connected to each other and led out through the second contact hole.

[0010] Of the first contact hole and the second contact hole, one is used to connect to a high voltage and the other is used to connect to a low voltage, in order to test the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region.

[0011] Furthermore, the H regions are used as units to form reconstructed rows and columns, with the H regions interleaved in the reconstructed rows and columns.

[0012] Furthermore, in the odd-numbered reconstruction columns, the H region is distributed in the odd-numbered reconstruction rows, and in the even-numbered reconstruction columns, the H region is distributed in the even-numbered reconstruction rows; or in the even-numbered reconstruction columns, the H region is distributed in the odd-numbered reconstruction rows, and in the odd-numbered reconstruction columns, the H region is distributed in the even-numbered reconstruction rows.

[0013] Furthermore, the test structure includes multiple H regions, each H region leading to a first contact hole and a second contact hole. The multiple first contact holes are all electrically connected through a first conductor layer; the multiple second contact holes are all electrically connected through a second conductor layer; leakage current between two adjacent columns of floating grids within any H region can be tested.

[0014] Furthermore, of the first contact hole and the second contact hole, one is used to connect to a high voltage and the other is used to connect to a low voltage. The high voltage range is 6V to 12V, and the low voltage is approximately 0V.

[0015] Furthermore, the test structure includes the storage cells arranged in an array;

[0016] The test structure includes multiple rows of parallel floating grid pattern areas extending along the X direction; each row of the floating grid pattern area includes the word line and the floating grid and the control grid stacked on both sides of the word line in the Y direction;

[0017] The overlapping area between the Y-direction active region and the floating gate pattern region is the storage unit;

[0018] The first contact hole is located within the gap between two adjacent columns of the Y-direction active regions; the second contact hole is also located within the gap between two adjacent columns of the Y-direction active regions.

[0019] The present invention also provides a test structure layout for flash memory, defining mutually perpendicular X and Y directions in a plane parallel to the substrate; including:

[0020] The floating grid layer includes multiple rows of parallel floating grid graphic areas extending along the X direction; each row of the floating grid graphic area includes a word line and floating grids and control grids stacked on both sides of the word line in the Y direction;

[0021] An active area layout layer includes multiple columns of parallel Y-direction active areas extending along the Y direction. An X-direction active area is provided between two adjacent columns of Y-direction active areas. The X-direction active areas and the Y-direction active areas of the adjacent areas on both sides are connected to form an H region. The H region includes a first floating gate in a first memory cell located in the upper left corner, a second floating gate in a second memory cell located in the lower left corner, a third floating gate in a third memory cell located in the upper right corner, and a fourth floating gate in a fourth memory cell located in the lower right corner.

[0022] A control gate removal layer is formed, comprising several sub-removal regions distributed along the X direction, the sub-removal regions being located on both sides of the X-direction active region; the control gate material layer of the sub-removal regions is etched away; the sub-removal regions expose floating gate connection regions, the floating gate connection regions comprising floating gate connection region one and floating gate connection region two; floating gate connection region one is the connection region of the first and second floating gates of two adjacent rows of memory cells in the nth column directly above the H region, each near the X-direction active region; floating gate connection region two is the connection region of the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column directly above the H region, each near the X-direction active region.

[0023] A contact hole plate layer, comprising: a first contact hole and a second contact hole; wherein, the sub-clearing area covers the first contact hole and the second contact hole; a floating gate connection area one is led out through the first contact hole; and a floating gate connection area two is led out through the second contact hole; of the first contact hole and the second contact hole, one is connected to a high voltage and the other is connected to a low voltage, to test the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region;

[0024] The control gate contact hole plate layer includes several sub-retention areas distributed in strips along the Y direction, and the floating gate material layer of the sub-retention areas is retained until the final state; the sub-retention areas cover all the first contact holes in the same column and cover all the second contact holes in the same column.

[0025] The present invention also provides a method for fabricating a test structure for flash memory, comprising:

[0026] S1. A substrate is provided, and mutually perpendicular X and Y directions are defined in a plane parallel to the substrate; multiple rows of parallel Y-direction active regions extending along the Y direction are formed in the substrate, and an X-direction active region is disposed between two adjacent rows of Y-direction active regions. The X-direction active regions and the Y-direction active regions in the adjacent regions on both sides are connected to form the H region.

[0027] S2. A stacked layer comprising a floating gate material layer, a spacer layer, a control gate material layer and a first sidewall is sequentially formed on the substrate; multiple rows of parallel word lines extending along the X direction are formed in the stacked layer;

[0028] S3. Etch away the control gate material layer and the spacer layer located in the floating gate connection region; the floating gate connection region includes floating gate connection region one and floating gate connection region two; floating gate connection region one is the connection region of the first and second floating gates of two adjacent rows of memory cells in the nth column directly above the H region, each close to the X-direction active region; floating gate connection region two is the connection region of the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column directly above the H region, each close to the X-direction active region;

[0029] S4. Etch the control gate material layer, the spacer layer, and the floating gate material layer to form a floating gate and a control gate;

[0030] S5. A dielectric layer is formed covering the word line, the floating gate, and the control gate. A first contact hole and a second contact hole are etched in the dielectric layer. The first contact hole leads out to the first floating gate connection area, and the second contact hole leads out to the second floating gate connection area.

[0031] Furthermore, step S3 specifically includes:

[0032] S31. A first photoresist layer is formed, which covers the word lines and exposes the floating gate connection area;

[0033] S32. Using the first photoresist layer as a mask, etch away the control gate material layer and spacer layer located in the floating gate connection region;

[0034] S33. The first photoresist layer is removed by an ashing process.

[0035] Furthermore, step S4 specifically includes:

[0036] S41. A second photoresist layer is formed, which covers the word line, the floating gate material layer of the floating gate connection area, and the gap between two adjacent memory cells.

[0037] S42. Using the second photoresist layer as a mask, etch away the exposed control gate material layer, the spacer layer, and the floating gate material layer to form the floating gate and the control gate;

[0038] S43. The second photoresist layer is removed by an ashing process.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] This invention provides a test structure, layout, and fabrication method for flash memory, comprising: a substrate, multiple rows of parallel word lines extending along the X direction located above the substrate, and multiple columns of parallel Y-direction active regions extending along the Y direction located within the substrate. An X-direction active region is disposed between two adjacent columns of Y-direction active regions, and the X-direction active regions are connected to the adjacent Y-direction active regions on both sides to form an H region; directly above the H region are a first floating gate located at the upper left corner, a second floating gate located at the lower left corner, a third floating gate located at the upper right corner, and a fourth floating gate located at the lower right corner. The first and second floating gates of two adjacent rows of memory cells in the nth column of the H region are connected and led out through the first contact hole; the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column of the H region are connected and led out through the second contact hole; of the first and second contact holes, one is used to connect to a high voltage and the other is used to connect to a low voltage, which can effectively monitor the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region; due to the inherent pattern alignment deviation during the operation of the lithography machine, the H region (H structure) in the actual structure may be asymmetrical, which may lead to bridging risk and bridging defects. The test structure of the flash memory of this invention is specifically designed to test for such bridging defects, and if problems are found, timely rework and rectification can be carried out to avoid bit line (BL) failure and programming failure. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a flash memory structure.

[0042] Figure 2 This is a test layout diagram of the flash memory according to an embodiment of the present invention.

[0043] Figure 3 For along Figure 2 A schematic cross-sectional view of Y1Y2.

[0044] Figure 4 This is a top view schematic diagram of the flash memory test structure according to an embodiment of the present invention.

[0045] Figure 5 This is a schematic diagram of the process for fabricating a test structure for flash memory according to an embodiment of the present invention.

[0046] Figure 6 This is a schematic diagram of the word lines formed in the flash memory test structure fabrication method of this embodiment of the invention.

[0047] Figure 7 This is a schematic diagram of the flash memory test structure fabrication method according to an embodiment of the present invention after the formation of the first photoresist layer.

[0048] Figure 8 This is a schematic diagram showing the control gate material layer and spacer layer after etching in the floating gate connection region during the fabrication method of the flash memory test structure according to an embodiment of the present invention.

[0049] Figure 9 This is a schematic diagram of the second photoresist layer after it has been formed in the flash memory test structure fabrication method of this embodiment of the invention.

[0050] Figure 10 This is a schematic diagram showing the formation of the floating gate and control gate in the flash memory test structure fabrication method of this embodiment of the invention.

[0051] Figure 11 This is a schematic diagram showing the formation of the first contact hole in the flash memory test structure fabrication method according to an embodiment of the present invention.

[0052] The reference numerals in the attached figures are as follows:

[0053] 10-Substrate; 11-First memory cell; 12-Second memory cell; 20-H region; 21-Y-direction active region; 22-X-direction active region; 30-Floating gate pattern region; 31-Word line; 32-Word line isolation layer; 33-First sidewall; 41-First contact hole; 42-Second contact hole; 51-First photoresist layer; 52-Second photoresist layer; FG1-First floating gate; FG2-Second floating gate; FG3-Third floating gate; FG4-Fourth floating gate; 60-Floating gate material layer; 70-Spacer layer; 80-Control gate material layer; A-Floating gate connection region; B-Sub-retention region; C-Sub-clearing region. Detailed Implementation

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0055] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0057] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0059] Figure 2 This is a test layout diagram of the flash memory according to an embodiment of the present invention. Figure 3 For along Figure 2 A schematic cross-sectional view of Y1Y2. Figure 4 This is a top view schematic diagram of the flash memory test structure according to an embodiment of the present invention.

[0060] This invention provides a test structure for flash memory, such as... Figures 2 to 4 As shown, it includes:

[0061] Substrate 10, the X and Y directions are defined perpendicularly to each other in the plane parallel to substrate 10; the direction perpendicular to the substrate is defined as the Z direction;

[0062] Multiple rows of parallel word lines 31 extending along the X direction are located above the substrate 10. Each row of word lines 31 has floating gates and control gates CG1 stacked from bottom to top along the Z direction on both sides along the Y direction.

[0063] Multiple rows of parallel Y-direction active regions 21 are located in the substrate 10, and X-direction active regions 22 are disposed between two adjacent rows of Y-direction active regions 21. The X-direction active regions 22 and the adjacent Y-direction active regions 21 on both sides are connected to form H region 20. The area directly above H region includes a first floating gate FG1 in the first memory cell 11 located in the upper left corner, a second floating gate FG2 in the second memory cell 12 located in the lower left corner, a third floating gate FG3 in the third memory cell located in the upper right corner, and a fourth floating gate FG4 in the fourth memory cell located in the lower right corner.

[0064] The first floating gate FG1 and the second floating gate FG2 of two adjacent rows of memory cells in the nth column of the H region are connected to each other and led out through the first contact hole 41; and the third floating gate FG3 and the fourth floating gate FG4 of two adjacent rows of memory cells in the (n+1)th column of the H region are connected to each other and led out through the second contact hole 42.

[0065] Of the first contact hole 41 and the second contact hole 42, one is used to connect to a high voltage and the other is used to connect to a low voltage, in order to test the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in region H 20.

[0066] Specifically, the substrate 10 may be made of silicon. In other embodiments, the substrate 10 may be made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator, or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements may include InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0067] The test structure includes an array of memory cells; the test structure includes multiple rows of parallel floating gate pattern regions 30 extending along the X direction; each row of floating gate pattern regions 30 includes word lines 31 and floating gates and control gates stacked on both sides of the word lines in the Y direction; the area where the Y-direction active region 21 overlaps with the floating gate pattern region 30 is the memory cell.

[0068] The rows and columns are constructed using H regions in units of 20, with the H regions interleaved in the constructed rows and columns. For example, in an odd number of constructed columns, the H regions are distributed in an odd number of constructed rows, and in an even number of constructed columns, the H regions are distributed in an even number of constructed rows; or in an even number of constructed columns, the H regions are distributed in an odd number of constructed rows, and in an odd number of constructed columns, the H regions are distributed in an even number of constructed rows.

[0069] The test structure includes multiple H regions 20, which are areas where two adjacent columns of Y-direction active regions 21 are laterally (X-direction) connected. Each H region 20 leads to a first contact hole 41 and a second contact hole 42. Multiple first contact holes 41 are electrically connected through a first conductive layer; multiple second contact holes 42 are electrically connected through a second conductive layer. In this way, leakage current between adjacent columns of floating gates within any H region can be tested. If leakage current is detected, it indicates a problem with the flash memory product's manufacturing process, requiring immediate rework and rectification. Of the first and second contact holes, one is used to connect to a high voltage, and the other to a low voltage. The high voltage range is 6V to 12V; the low voltage is approximately 0V. The first contact hole located in the dielectric layer is filled with a metal layer as a first solder pad, and the second contact hole located in the dielectric layer is filled with a metal layer as a second solder pad. A first interconnect metal layer covers the dielectric layer and fills the first contact holes, achieving interconnection of all first contact holes. A second interconnect metal layer covers the dielectric layer and fills the second contact holes, achieving interconnection of all second contact holes. The first interconnect metal layer and the second interconnect metal layer can be formed using the same metal layer process, but they are not connected to each other.

[0070] Each line of text 31 has floating grids and control grids CG1 stacked from bottom to top along the Z direction on both sides along the Y direction, and a first side wall 33. A second side wall 34 can be formed subsequently, covering the floating grids, control grids, and the sidewalls of the first side wall 33.

[0071] In the same wafer, most of the wafer area is used to manufacture flash memory products, and a small portion of the wafer area is used to manufacture the test structure of the flash memory in this invention, in order to monitor the manufacturing process of the flash memory products, especially to detect the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region.

[0072] The present invention also provides a test structure layout for flash memory, wherein mutually perpendicular X and Y directions are defined in a plane parallel to the substrate; the test structure of the flash memory described above is formed using this test structure layout.

[0073] Flash memory test architecture layout, such as Figure 2 and Figure 8 As shown, it includes:

[0074] The raster layer comprises multiple rows of parallel raster graphic areas 30 extending along the X direction; each row of raster graphic areas includes a word line and raster and control grid stacked on both sides of the word line in the Y direction.

[0075] The active area layer includes multiple parallel columns of Y-direction active areas 21 extending along the Y direction. An X-direction active area 22 is provided between two adjacent columns of Y-direction active areas 21. The X-direction active areas 22 and the adjacent Y-direction active areas 21 on both sides are connected to form an H region 20. The H region 20 includes a first floating gate FG1 in the first memory cell located in the upper left corner, a second floating gate FG2 in the second memory cell located in the lower left corner, a third floating gate FG3 in the third memory cell located in the upper right corner, and a fourth floating gate FG4 in the fourth memory cell located in the lower right corner.

[0076] The control grid removal layer comprises several sub-removal regions C distributed along the X direction. Figure 2 (Green box), Sub-cleaning region C is located on both sides of the X-direction active region 22; the control gate material layer 80 of sub-cleaning region C is etched away; sub-cleaning region C exposes floating gate connection region A, which includes floating gate connection region one and floating gate connection region two; floating gate connection region one is the connection region of the first floating gate FG1 and the second floating gate FG2 of two adjacent rows of memory cells in the nth column directly above the H region, respectively, close to the X-direction active region 22; floating gate connection region two is the connection region of the third floating gate FG3 and the fourth floating gate FG4 of two adjacent rows of memory cells in the (n+1)th column directly above the H region, respectively, close to the X-direction active region 22.

[0077] Specifically, in combination Figure 2 , Figure 7 and Figure 8 Using a control gate removal layer as a photomask, a patterned first photoresist layer 51 is formed. During the etching of the logic area gate of the flash memory on the same wafer, the control gate material layer 80 and spacer layer 70 of the exposed area (including the floating gate connection area A) of the first photoresist layer 51 in the test area where the test structure of the flash memory of this invention is located can be simultaneously etched away, forming... Figure 8 The structure. The control grid removal layer (containing several sub-removal areas C) opens all contact hole areas in the test area.

[0078] The contact hole plate layer includes: a first contact hole 41 and a second contact hole 42; wherein, a sub-clearing region C covers the first contact hole 41 and the second contact hole 42; a floating gate connection region one is led out through the first contact hole 41; and a floating gate connection region two is led out through the second contact hole 42; of the two contact holes 41 and 42, one is connected to a high voltage and the other is connected to a low voltage, so as to test the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in region H.

[0079] The control gate contact hole layer includes several sub-reserved regions B arranged in strips along the Y direction. The floating gate material layer 60 of the sub-reserved regions B is retained until the final state of the flash memory. One sub-reserved region B covers all the first contact holes 41 in the same column, and another sub-reserved region B covers all the second contact holes 42 in the same column. Specifically, the sub-reserved regions B cover all the required contact holes in strips along the Y direction. During the etching of the control gate material layer 80 and the floating gate material layer 60 in the normal flash memory area, photoresist protects the floating gate material layer 60 of the sub-reserved regions B from etching. The floating gate material layer 60 retained in the sub-reserved regions B is used for the connection of subsequent contact holes.

[0080] This invention also provides a method for fabricating a test structure for flash memory, such as... Figure 5 As shown, it includes:

[0081] S1. Provide a substrate, and define mutually perpendicular X and Y directions in a plane parallel to the substrate; form multiple rows of parallel Y-direction active regions extending along the Y direction in the substrate, and set an X-direction active region between two adjacent rows of Y-direction active regions, and connect the X-direction active regions with the Y-direction active regions in the adjacent regions on both sides to form the H region.

[0082] S2. A stacked layer comprising a floating gate material layer, a spacer layer, a control gate material layer and a first sidewall is sequentially formed on the substrate; multiple rows of parallel word lines extending along the X direction are formed in the stacked layer;

[0083] S3. Etch away the control gate material layer and spacer layer located in the floating gate connection region; the floating gate connection region includes floating gate connection region one and floating gate connection region two; floating gate connection region one is the connection region of the first and second floating gates of two adjacent rows of memory cells in the nth column directly above the H region, each close to the X-direction active region; floating gate connection region two is the connection region of the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column directly above the H region, each close to the X-direction active region.

[0084] S4. Etch the control gate material layer, spacer layer and floating gate material layer to form the floating gate and control gate;

[0085] S5. Form a dielectric layer covering word lines, floating gates and control gates, and etch a first contact hole and a second contact hole in the dielectric layer; the first contact hole leads out to floating gate connection area one, and the second contact hole leads out to floating gate connection area two.

[0086] The following describes in detail, with reference to the accompanying drawings, the steps of fabricating the flash memory test structure according to an embodiment of the present invention.

[0087] like Figure 6 and Figure 2 As shown, a substrate is provided, and mutually perpendicular X and Y directions are defined in a plane parallel to the substrate 10; multiple rows of parallel Y-direction active regions 21 extending along the Y direction are formed in the substrate 10, and an X-direction active region 22 is disposed between two adjacent rows of Y-direction active regions 21. The X-direction active regions 22 and the adjacent Y-direction active regions 21 on both sides are connected and form an H region 20.

[0088] A floating gate material layer 60, a spacer layer 70, a control gate material layer 80, and a first sidewall are sequentially formed on a substrate. Multiple rows of parallel word lines 31 extending along the X-direction are also formed on the substrate. The word lines 31 are located within the accommodating space formed by the floating gate material layer 60, the spacer layer 70, the control gate material layer 80, and the first sidewall. A word line isolation layer 32 may also be formed on the surface of the word lines 31 to protect them. The processes for forming the floating gate material layer 60 and the control gate material layer 80 can both be deposition processes, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. The spacer layer 70 is, for example, an ONO layer (bottom oxide layer, silicon nitride layer, and top oxide layer).

[0089] like Figure 7 and Figure 2As shown, a first photoresist layer 51 is formed, which covers the word line 31 and exposes the floating gate connection area A. The floating gate connection area A includes a first floating gate connection area and a second floating gate connection area. The first floating gate connection area is the connection area of ​​the first floating gate FG1 and the second floating gate FG2 of two adjacent rows of memory cells in the nth column directly above the H region, respectively, close to the active area 22 in the X direction. The second floating gate connection area is the connection area of ​​the third floating gate FG3 and the fourth floating gate FG4 of two adjacent rows of memory cells in the (n+1)th column of the H region, respectively, close to the active area in the X direction.

[0090] like Figure 7 and Figure 8 As shown, using the first photoresist layer 51 as a mask, the control gate material layer 80 and the spacer layer 70 located in the floating gate connection region A are etched away; then, the first photoresist layer 51 can be removed by an ashing process.

[0091] like Figure 9 As shown, a second photoresist layer 52 is formed, which covers the word line 31, the floating gate material layer 60 of the floating gate connection area A, and the gap between two adjacent memory cells.

[0092] like Figure 10 As shown, using the second photoresist layer 52 as a mask, the exposed control gate material layer 80, spacer layer 70 and floating gate material layer 60 are etched away to form a floating gate and a control gate; then, the second photoresist layer 52 can be removed by an ashing process.

[0093] This invention refines and modifies the first photoresist layer 51 and the second photoresist layer 52. The first and second photoresist layers 51 and 52 were already present in the original process. This invention achieves a layout change by refining and modifying the first and second photoresist layers 51 and 52 without adding new photomask layers. This layout change enables the implementation of the flash memory testing structure of this invention. For example... Figure 11 As shown, a dielectric layer (not shown) is formed covering the word line 31, the floating gate, and the control gate. A first contact hole 41 and a second contact hole (not shown) are etched in the dielectric layer. The first contact hole 41 leads out to the first floating gate connection area, and the second contact hole leads out to the second floating gate connection area.

[0094] In the original flash memory chip, the floating gate was surrounded by a dielectric layer or covered by a control gate. The floating gate was not directly connected to the contact hole, and voltage could not be directly applied to the floating gate. Generally, the potential on the floating gate was affected by the potential of the control gate, so the floating gate potential was limited and could not be made higher.

[0095] This invention connects contact holes (i.e., the first contact hole 41 and the second contact hole) directly to two bridged floating gates by combining the layout of photomask layers. This does not increase the number of photomask layers, i.e., it does not add an extra photomask. Moreover, voltage can be directly applied to the floating gate through the contact holes. The potential on the floating gate is no longer affected by the control gate potential, etc., so the floating gate potential can be appropriately increased as needed.

[0096] In summary, this invention provides a flash memory test structure and its fabrication method, comprising: a substrate, multiple rows of parallel word lines extending along the X direction located above the substrate, and multiple columns of parallel Y-direction active regions extending along the Y direction located within the substrate. An X-direction active region is disposed between two adjacent columns of Y-direction active regions, and the X-direction active regions are connected to the adjacent Y-direction active regions on both sides to form an H region; directly above the H region are a first floating gate located at the upper left corner, a second floating gate located at the lower left corner, a third floating gate located at the upper right corner, and a fourth floating gate located at the lower right corner. The first and second floating gates of two adjacent rows of memory cells in the nth column of region H are connected and led out through the first contact hole; the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column of region H are connected and led out through the second contact hole; of the first and second contact holes, one is used to connect to a high voltage and the other is used to connect to a low voltage, which can effectively monitor the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in region H; if a problem is found, it can be reworked and rectified in time to avoid bit line BL failure and programming failure.

[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0098] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A test structure for flash memory, characterized in that, include: The substrate has mutually perpendicular X and Y directions defined in a plane parallel to the substrate. Multiple rows of parallel word lines extending along the X direction are located above the substrate, and each row of word lines has stacked floating gates and control gates on both sides along the Y direction; Multiple parallel Y-direction active regions extending along the Y direction are located in the substrate. An X-direction active region is disposed between two adjacent columns of Y-direction active regions. The X-direction active regions and the Y-direction active regions of the adjacent regions on both sides are connected to form an H region. The H region includes a first floating gate in a first memory cell located in the upper left corner, a second floating gate in a second memory cell located in the lower left corner, a third floating gate in a third memory cell located in the upper right corner, and a fourth floating gate in a fourth memory cell located in the lower right corner. The first floating gate and the second floating gate of two adjacent rows of memory cells in the nth column of the H region are connected to each other and led out through the first contact hole; and the third floating gate and the fourth floating gate of two adjacent rows of memory cells in the (n+1)th column of the H region are connected to each other and led out through the second contact hole. Of the first contact hole and the second contact hole, one is connected to a high voltage and the other is connected to a low voltage to test the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region.

2. The flash memory test structure as described in claim 1, characterized in that, The H regions are used as units to form the rows and columns of the reconstruction, and the H regions are interspersed in the reconstruction rows and columns.

3. The flash memory test structure as described in claim 2, characterized in that, In the odd-numbered reconstruction columns, the H region is distributed in the odd-numbered reconstruction rows, and in the even-numbered reconstruction columns, the H region is distributed in the even-numbered reconstruction rows; Alternatively, in an even number of the reconstructed columns, the H region is distributed in an odd number of the reconstructed rows, and in an odd number of the reconstructed columns, the H region is distributed in an even number of the reconstructed rows.

4. The flash memory test structure as described in claim 1, characterized in that, The test structure includes multiple H regions, each H region leading to a first contact hole and a second contact hole. The multiple first contact holes are electrically connected through a first conductor layer; the multiple second contact holes are electrically connected through a second conductor layer; leakage current between two adjacent columns of floating grids within any H region can be tested.

5. The flash memory test structure as described in claim 1, characterized in that, Of the first contact hole and the second contact hole, one is used to connect to a high voltage and the other is used to connect to a low voltage. The high voltage range is 6V to 12V, and the low voltage is approximately 0V.

6. The flash memory test structure as described in claim 1, characterized in that, The test structure includes the storage units arranged in an array; The test structure includes multiple rows of parallel floating grid pattern areas extending along the X direction; each row of the floating grid pattern area includes the word line and the floating grid and the control grid stacked on both sides of the word line in the Y direction; The overlapping area between the Y-direction active region and the floating gate pattern region is the storage unit; The first contact hole is located within the gap between two adjacent columns of the Y-direction active regions; the second contact hole is also located within the gap between two adjacent columns of the Y-direction active regions.

7. A test structure layout for flash memory, wherein mutually perpendicular X and Y directions are defined in a plane parallel to the substrate; characterized in that, include: A raster layer, the raster layer comprising multiple rows of parallel raster graphic areas extending along the X direction; Each row of the floating grid graphic area includes word lines and floating grids and control grids stacked on both sides of the word lines in the Y direction; An active area layout layer includes multiple columns of parallel Y-direction active areas extending along the Y direction. An X-direction active area is provided between two adjacent columns of Y-direction active areas. The X-direction active areas and the Y-direction active areas of the adjacent areas on both sides are connected to form an H region. The H region includes a first floating gate in a first memory cell located in the upper left corner, a second floating gate in a second memory cell located in the lower left corner, a third floating gate in a third memory cell located in the upper right corner, and a fourth floating gate in a fourth memory cell located in the lower right corner. A control gate removal layer is formed, comprising several sub-removal regions distributed along the X direction, the sub-removal regions being located on both sides of the X-direction active region; the control gate material layer of the sub-removal regions is etched away; the sub-removal regions expose floating gate connection regions, the floating gate connection regions comprising floating gate connection region one and floating gate connection region two; floating gate connection region one is the connection region of the first and second floating gates of two adjacent rows of memory cells in the nth column directly above the H region, each near the X-direction active region; floating gate connection region two is the connection region of the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column directly above the H region, each near the X-direction active region. A contact hole plate layer, comprising: a first contact hole and a second contact hole; wherein, the sub-clearing area covers the first contact hole and the second contact hole; a floating gate connection area one is led out through the first contact hole; and a floating gate connection area two is led out through the second contact hole; of the first contact hole and the second contact hole, one is connected to a high voltage and the other is connected to a low voltage, to test the leakage current or breakdown voltage between the floating gates of two adjacent columns of memory cells in the H region; The control gate contact hole plate layer includes several sub-retention areas distributed in strips along the Y direction, and the floating gate material layer of the sub-retention areas is retained until the final state; the sub-retention areas cover all the first contact holes in the same column and cover all the second contact holes in the same column.

8. A method for fabricating a test structure for flash memory, characterized in that, include: S1. A substrate is provided, and mutually perpendicular X and Y directions are defined in a plane parallel to the substrate; multiple rows of parallel Y-direction active regions extending along the Y direction are formed in the substrate, and an X-direction active region is disposed between two adjacent rows of Y-direction active regions. The X-direction active regions and the Y-direction active regions in the adjacent regions on both sides are connected to form the H region. S2. A stacked layer comprising a floating gate material layer, a spacer layer, a control gate material layer and a first sidewall is sequentially formed on the substrate; multiple rows of parallel word lines extending along the X direction are formed in the stacked layer; S3. Etch away the control gate material layer and the spacer layer located in the floating gate connection region; the floating gate connection region includes floating gate connection region one and floating gate connection region two; floating gate connection region one is the connection region of the first and second floating gates of two adjacent rows of memory cells in the nth column directly above the H region, each close to the X-direction active region; floating gate connection region two is the connection region of the third and fourth floating gates of two adjacent rows of memory cells in the (n+1)th column directly above the H region, each close to the X-direction active region; S4. Etch the control gate material layer, the spacer layer, and the floating gate material layer to form a floating gate and a control gate; S5. A dielectric layer is formed covering the word line, the floating gate, and the control gate. A first contact hole and a second contact hole are etched in the dielectric layer. The first contact hole leads out to the first floating gate connection area, and the second contact hole leads out to the second floating gate connection area.

9. The method for fabricating the test structure of flash memory as described in claim 8, characterized in that, Step S3 specifically includes: S31. A first photoresist layer is formed, which covers the word lines and exposes the floating gate connection area; S32. Using the first photoresist layer as a mask, etch away the control gate material layer and spacer layer located in the floating gate connection region; S33. The first photoresist layer is removed by an ashing process.

10. The method for fabricating the test structure of flash memory as described in claim 8, characterized in that, Step S4 specifically includes: S41. A second photoresist layer is formed, which covers the word line, the floating gate material layer of the floating gate connection area, and the gap between two adjacent memory cells. S42. Using the second photoresist layer as a mask, etch away the exposed control gate material layer, the spacer layer, and the floating gate material layer to form the floating gate and the control gate; S43. The second photoresist layer is removed by an ashing process.

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