On-chip calibration source circuit and chip for radio frequency direct-sampling receive chain

Abstract

The application provides an on-chip calibration source circuit and a chip for a radio frequency direct sampling receiving link. The on-chip calibration source circuit comprises a clock signal output circuit and a differential current signal output circuit. The output end of the clock signal output circuit is connected to the input end of the differential current signal output circuit. The output end of the differential current signal output circuit is movably connected to the input end of a variable gain amplifier. The clock signal output circuit is used for outputting a clock signal to the differential current signal output circuit. The differential current signal output circuit is used for generating a first calibration signal according to the input clock signal and outputting the first calibration signal to the variable gain amplifier. The first calibration signal is a differential current signal. The first calibration signal is used for error calibration of the variable gain amplifier. The variable gain amplifier is used for outputting a second calibration signal to a time-interleaved analog-to-digital converter according to the first calibration signal. The second calibration signal is used for error calibration of the time-interleaved analog-to-digital converter.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to an on-chip calibration source circuit and chip for a radio frequency direct sampling receiving link. Background Technology

[0002] In recent years, with the rapid development of 5G communication, low-cost, high-performance radio frequency (RF) receiver links have become a new research hotspot with broad application prospects. Among them, the RF direct-access receiver link (RX) is gradually becoming the mainstream direction. Compared with traditional frequency conversion receiver schemes, it eliminates the need for mixers and many passive matching circuits, resulting in significant cost and size advantages and strong competitiveness.

[0003] High-speed RF direct sampling receiver links typically consist of a cascaded Digital Variable Gain Amplifier (DVGA) and a Time-Interleaved Analog-to-Digital Converter (TI-ADC). The DVGA receives the RF signal and performs amplification, attenuation, and filtering. The TI-ADC samples and quantizes the analog signal output by the DVGA, converting it into a digital signal. DVGAs often exhibit phase shift errors, while TI-ADCs typically suffer from sub-channel gain mismatch (TI gain), sub-channel sampling timing mismatch (TI skew), and sub-channel offset mismatch (TI offset), all of which affect the normal operation and performance of the RX (radio frequency converter). Therefore, error calibration is necessary.

[0004] In related technologies, commonly used calibration methods include off-chip calibration and on-chip calibration. Off-chip calibration involves injecting a required calibration signal (usually a square wave or sine wave) into the RX from an external source. However, off-chip calibration suffers from poor integration and is inconvenient to operate, requiring complex test instruments and precise manual intervention. On-chip calibration, on the other hand, typically requires calibrating the DVGA via the TI-ADC through different paths. Furthermore, the calibration source usually uses voltage signal transmission, which can lead to signal distortion during transmission. Therefore, additional AC (Alternating Current) coupling capacitors are needed when calibrating the DVGA to prevent interference with the DVGA's common-mode operating point. Summary of the Invention

[0005] This application provides an on-chip calibration source circuit and chip for a radio frequency direct sampling receiver link.

[0006] This application provides an on-chip calibration source circuit for a radio frequency direct sampling receiving link. The radio frequency direct sampling receiving link includes a variable gain amplifier and a time-interleaved analog-to-digital converter. The on-chip calibration source circuit includes a clock signal output circuit and a differential current signal output circuit. The output terminal of the clock signal output circuit is connected to the input terminal of the differential current signal output circuit. The output terminal of the differential current signal output circuit is movably connected to the input terminal of the variable gain amplifier. The output terminal of the variable gain amplifier is connected to the input terminal of the time-interleaved analog-to-digital converter.

[0007] The clock signal output circuit is used to output a clock signal to the differential current signal output circuit;

[0008] The differential current signal output circuit is used to generate a first calibration signal according to the input clock signal and output the first calibration signal to the variable gain amplifier. The first calibration signal is a differential current signal.

[0009] The first calibration signal is used to perform error calibration on the variable gain amplifier;

[0010] The variable gain amplifier is used to output a second calibration signal to the time-interleaved analog-to-digital converter based on the first calibration signal, wherein the second calibration signal is a voltage signal.

[0011] The second calibration signal is used to perform error calibration on the time-interleaved analog-to-digital converter.

[0012] This application provides a chip including a direct RF sampling receiver link and an on-chip calibration source circuit. The direct RF sampling receiver link includes a variable gain amplifier and a time-interleaved analog-to-digital converter. The on-chip calibration source circuit includes the aforementioned on-chip calibration source circuit.

[0013] According to the on-chip calibration source circuit and chip for RF direct sampling receiver links according to embodiments of this application, a first calibration signal for calibrating the RF direct sampling receiver link is generated by a differential current signal output circuit under the action of a clock signal output circuit. The first calibration signal is a differential current signal. Using differential current signal transmission reduces the requirements for the signal transmission path, effectively ensuring the quality during signal transmission and obtaining a high-quality calibration signal without distortion. Furthermore, no coupling capacitor is required on the transmission path, resulting in a small equivalent parasitic capacitance and minimal impact on the RX link. Since the variable gain amplifier is a resistive load and the time-interleaved analog-to-digital converter is a capacitive load, the first calibration signal is directly injected into the input of the variable gain amplifier to perform error calibration. Then, the first calibration signal can be recovered into a voltage signal by the variable gain amplifier and input into the time-interleaved analog-to-digital converter for error calibration. That is, the first calibration signal output by the on-chip calibration source circuit is directly injected into the input of the RX, which can complete the error calibration of the variable gain amplifier and the time-interleaved analog-to-digital converter in one step without the need for additional paths to calibrate the time-interleaved analog-to-digital converter.

[0014] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0015] In the accompanying drawings of the embodiments of this application:

[0016] Figure 1 This diagram illustrates the working principle of a time-interleaved analog-to-digital converter provided in an embodiment of this application.

[0017] Figure 2 This diagram illustrates a block diagram of an on-chip calibration source circuit for a direct RF sampling receiver link, as provided in an embodiment of this application.

[0018] Figure 3 This diagram shows a block diagram of a differential current drive circuit provided in an embodiment of this application.

[0019] Figure 4 This diagram shows a circuit structure schematic of a differential current driving circuit provided in an embodiment of this application.

[0020] Figure 5 This diagram shows a schematic of the circuit structure of a differential current signal output circuit provided in an embodiment of this application.

[0021] Figure 6 This diagram illustrates the timing of the n sets of clock signals corresponding to the n sets of differential current drive circuits in the embodiments of this application.

[0022] Figure 7The diagram shows the waveform of the signal output by the n differential current drive circuits in the embodiment of this application being recovered into a voltage signal.

[0023] Figure 8 This diagram illustrates a block diagram of another on-chip calibration source circuit provided in an embodiment of this application.

[0024] Figure 9 This diagram illustrates a block diagram of another on-chip calibration source circuit provided in an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0026] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0027] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0028] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0029] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0030] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0032] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0033] In related technologies, high-speed RF direct sampling receiver links typically consist of a cascaded variable gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC). The DVGA receives the RF signal and performs amplification, attenuation, and filtering, while the TI-ADC samples and quantizes the analog signal output by the DVGA, converting it into a digital signal.

[0034] The analog-to-digital converters (ADCs) in high-speed RF direct-access receiver links generally use TI-ADCs to improve the operating frequency. Figure 1 This illustration shows a schematic diagram illustrating the working principle of a time-interleaved analog-to-digital converter according to an embodiment of this application. Figure 1 As shown, the TI-ADC uses M sub-analog-to-digital converters (subADCs) with a sampling rate of Fs / M, sampling alternately in parallel with a fixed phase deviation of 360° / M, so that the total sampling rate can reach M times that of the subADCs. Each subADC sequentially samples, quantizes, and encodes the input signal before outputting it through a multiplexer (MUX). However, due to limitations in circuit design and manufacturing process variations, there will inevitably be mismatches and non-uniform performance among the M subADCs, which are more pronounced at high frequencies. Therefore, TI-ADCs typically suffer from errors such as sub-channel gain mismatch (TI gain), sub-channel sampling timing mismatch (TI skew), and sub-channel offset mismatch (TI offset), which severely affect performance. A wideband RF variable gain amplifier (DVGA) generally consists of an adjustable attenuator (ATT) and a low-noise amplifier (LNA). However, each gain adjustment produces a different phase shift, resulting in phase shift errors. The existence of these errors will affect the normal operation and performance of the RX, so error calibration is necessary.

[0035] In related technologies, commonly used calibration methods include off-chip calibration and on-chip calibration. Off-chip calibration involves injecting a required calibration signal (usually a square wave or sine wave) into the RX from an external source. However, off-chip calibration suffers from poor integration and is inconvenient to operate, requiring complex test instruments and precise manual intervention. On-chip calibration, on the other hand, typically requires calibrating the DVGA via the TI-ADC through different paths. Furthermore, the calibration source usually uses voltage signal transmission, which can lead to signal distortion during transmission. Therefore, additional AC (Alternating Current) coupling capacitors are needed when calibrating the DVGA to prevent interference with the DVGA's common-mode operating point.

[0036] Therefore, this application provides an on-chip calibration source circuit and chip for a direct RF acquisition receiving link, which aims to solve the technical problems existing in the above-mentioned related technologies.

[0037] Figure 2 This illustration shows a block diagram of an on-chip calibration source circuit for a direct RF sampling receiver link, as provided in an embodiment of this application. Figure 2 As shown, this application embodiment provides an on-chip calibration source circuit for error calibration of an RF direct sampling receiver link. The RF direct sampling receiver link includes a variable gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC). The on-chip calibration source circuit includes a clock signal output circuit 11 and a differential current signal output circuit 12. The output terminal of the clock signal output circuit 11 is connected to the input terminal of the differential current signal output circuit 12. The output terminal of the differential current signal output circuit 12 is movably connected to the input terminal of the variable gain amplifier 13. The output terminal of the variable gain amplifier 13 is connected to the input terminal of the time-interleaved analog-to-digital converter 14.

[0038] The clock signal output circuit 11 outputs a clock signal to the differential current signal output circuit 12; the differential current signal output circuit 12 generates a first calibration signal based on the input clock signal and outputs the first calibration signal to the variable gain amplifier 13, wherein the first calibration signal is a differential current signal; the first calibration signal is used to perform error calibration on the variable gain amplifier 13; the variable gain amplifier 13 outputs a second calibration signal to the time-interleaved analog-to-digital converter 14 based on the first calibration signal, wherein the second calibration signal is a voltage signal; the second calibration signal is used to perform error calibration on the time-interleaved analog-to-digital converter 14.

[0039] In some embodiments, in the RF direct acquisition receiving link, the output of the variable gain amplifier 13 is connected to the input of the time-interleaved analog-to-digital converter 14 via an input buffer (inbuf) 15.

[0040] The on-chip calibration source circuit provided in this application utilizes a differential current signal output circuit to generate a first calibration signal for calibrating the RF direct sampling receiving link under the action of a clock signal output circuit. This first calibration signal is a differential current signal, which reduces the requirements for the signal transmission path and effectively ensures signal quality during transmission, resulting in a high-quality, distortion-free calibration signal. Furthermore, no coupling capacitor is required on the transmission path, resulting in a small equivalent parasitic capacitance and minimal impact on the RX link. Since the variable gain amplifier is a resistive load and the time-interleaved analog-to-digital converter (ADC) is a capacitive load, the first calibration signal is directly injected into the input of the variable gain amplifier to perform error calibration. The first calibration signal is then restored to a voltage signal by the variable gain amplifier and input to the time-interleaved ADC for error calibration. In other words, the first calibration signal output from the on-chip calibration source circuit is directly injected into the RX input, allowing for one-time error calibration of both the variable gain amplifier and the time-interleaved ADC without requiring additional paths to calibrate the time-interleaved ADC.

[0041] In some embodiments, the clock signal output circuit 11 outputs a differential clock signal, which includes a first clock signal and a second clock signal. The first clock signal and the second clock signal are square wave signals that are out of phase with each other. The first calibration signal includes a first differential current signal and a second differential current signal.

[0042] In some embodiments, the differential current signal output circuit 12 includes at least one set of differential current driving circuits. In some embodiments, the differential current driving circuit is a low-voltage differential signal (LVDS) generation circuit.

[0043] Figure 3 This diagram illustrates a block diagram of a differential current drive circuit according to an embodiment of this application. Figure 3 As shown, each differential current drive circuit includes a first output circuit 121 and a second output circuit 122. The first output circuit 121 has a first output terminal, and the second output circuit 122 has a second output terminal. The first output circuit is configured to generate a first differential current signal based on a first clock signal and a second clock signal and output it to the first output terminal. The second output circuit is configured to generate a second differential current signal based on the first clock signal and the second clock signal and output it to the second output terminal.

[0044] Figure 4 This diagram illustrates a circuit structure of a differential current drive circuit according to an embodiment of this application. In some embodiments, such as... Figure 4As shown, the first output circuit 121 includes a first transistor T1 and a second transistor T2.

[0045] In this circuit, the control electrode of the first transistor T1 is connected to the output terminal of the clock signal output circuit 11, which outputs the first clock signal clk_n; the first electrode of the first transistor T1 is connected to the first power supply terminal; and the second electrode of the first transistor T1 is connected to the first output terminal Voutn of the differential current signal output circuit. Similarly, the control electrode of the second transistor T2 is connected to the output terminal of the clock signal output circuit 11, which outputs the second clock signal clk_p; the first electrode of the second transistor T2 is connected to the second power supply terminal; and the second electrode of the second transistor T2 is connected to the first output terminal Voutn of the differential current signal output circuit.

[0046] In some embodiments, such as Figure 4 As shown, the second output circuit 122 includes a third transistor T3 and a fourth transistor T4.

[0047] The control electrode of the third transistor T3 is connected to the output terminal of the clock signal output circuit 11, which outputs the second clock signal clk_p; the first electrode of the third transistor T3 is connected to the first power supply terminal; and the second electrode of the third transistor T3 is connected to the second output terminal Voutp of the differential current signal output circuit. The control electrode of the fourth transistor T4 is connected to the output terminal of the clock signal output circuit 11, which outputs the first clock signal clk_n; the first electrode of the fourth transistor T4 is connected to the second power supply terminal; and the second electrode of the fourth transistor T4 is connected to the second output terminal Voutp of the differential current signal output circuit.

[0048] In some embodiments, both the first power supply terminal and the second power supply terminal are current power supply terminals used to generate current signals.

[0049] In some embodiments, the amplitude of the first calibration signal output by the on-chip calibration source circuit can be adjusted by adjusting the current output from the first power supply terminal and the second power supply terminal in the differential current drive circuit, thereby meeting the calibration requirements.

[0050] In some embodiments, such as Figure 4As shown, each differential current drive circuit also includes a common-mode feedback circuit 123. The common-mode feedback circuit includes an operational amplifier A, whose output is connected to a first power supply terminal. Its first input terminal, Vref, serves as a reference voltage. The second input terminal, Vcom, is connected via a resistor to the first output terminal Voutn and the second input terminal Voutp of the differential current signal output circuit. Specifically, the second input terminal Vcom is connected to the first output terminal Voutn of the differential current signal output circuit via one resistor, and to the second output terminal Voutp of the differential current signal output circuit via another resistor. By configuring the common-mode feedback circuit, a stable common-mode voltage can be provided to the output of the differential current signal output circuit.

[0051] In some embodiments, the differential current signal output circuit 12 includes multiple sets of differential current driving circuits. During each error calibration, the output terminal of the clock signal output circuit 11 is connected to one set of differential current driving circuits in the differential current signal output circuit 12. The multiple sets of differential current driving circuits correspond to different frequencies of the input clock signals, and the multiple sets of differential current driving circuits correspond to different magnitudes of the output current signals. Different differential current driving circuits can be selected to provide calibration signals according to calibration requirements, thereby outputting calibration signals of different amplitudes for calibration.

[0052] Figure 5 This diagram illustrates a circuit structure of a differential current signal output circuit according to an embodiment of this application. In some embodiments, such as... Figure 5 As shown, the differential current signal output circuit 12 includes n (n greater than or equal to 2) sets of differential current drive circuits, corresponding to n current power supply terminals respectively. The magnitudes of the currents output from the n current power supply terminals are I, 2I, 4I, ..., 2I, respectively. n I. Each group of differential current drive circuits corresponds to a set of clock signals as input. Each set of clock signals includes clock signal clk_n and clock signal clk_p. Clock signals clk_n and clk_p are differential clock signals, which are square wave signals that are inversely related. The circuit structure of each group of differential current drive circuits can be referred to the above. Figure 4 The circuit structure of the differential current drive circuit is shown.

[0053] The n differential current drive circuits correspond to n different frequencies of input clock signals, denoted as clk1, clk2, ..., clkn. Figure 6 This document shows a timing diagram of n sets of clock signals corresponding to n sets of differential current drive circuits in an embodiment of this application, as follows: Figure 6 As shown, the frequency of clk2 is half that of clk1, the frequency of clk3 is one-quarter that of clk1, and so on, the frequency of clkn is half that of clk1. n-1The clock signal output by the clock signal output circuit is clk1, while clk2 to clkn can be obtained by repeatedly dividing clk1 by two using a D flip-flop.

[0054] For ease of description, Figure 5 In each differential current drive circuit, the transistors are replaced by switches. Clock signals clk_n and clk_p are used to control the switching on or off. It can be understood that when the switch controlled by clock signal clk_n is on, the switch controlled by clk_p is off, and when the switch controlled by clock signal clk_n is off, the switch controlled by clk_p is on.

[0055] In some embodiments, the differential current signals output by one set of differential current drive circuits, after being amplified by a variable gain amplifier, recover a voltage signal with a square wave waveform. Conversely, the voltage signals recovered from the signals output by n sets of differential current drive circuits, after being amplified by a variable gain amplifier, have a stepped waveform with n steps. Figure 7 This illustration shows a waveform diagram of the signals output by n sets of differential current drive circuits in an embodiment of this application being recovered into voltage signals, as shown below. Figure 7 As shown, the voltage signal recovered after the output signals of n differential current drive circuits are a stepped waveform after passing through a variable gain amplifier. The number of steps is n. If n is large enough, the stepped waveform will approach a sine wave.

[0056] In some embodiments, n sets of differential current driving circuits are used to form a differential current signal output circuit. Each set of differential current driving circuits outputs a different signal amplitude. A set of differential current driving circuits can be selected in sequence to output the required calibration signal to perform error calibration on the RF direct sampling receiving link, which can effectively improve the accuracy of calibration.

[0057] Figure 8 This diagram illustrates a block diagram of another on-chip calibration source circuit provided in an embodiment of this application. In some embodiments, such as... Figure 8As shown, an impedance adjustment circuit 16 is also connected between the differential current signal output circuit 12 and the variable gain amplifier 13. The impedance adjustment circuit 16 is used to adjust the impedance between the output terminal of the differential current signal output circuit 12 and the input terminal of the variable gain amplifier 13. The differential current signal output circuit 12 has two output terminals, namely a first output terminal and a second output terminal, and the variable gain amplifier 13 has two input terminals. The impedance adjustment circuit 16 includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to one output terminal of the differential current signal output circuit 12, and the other end of the first resistor R1 is movably connected to one input terminal of the variable gain amplifier 13. One end of the second resistor R2 is connected to the other output terminal of the differential current signal output circuit 12, and the other end of the second resistor R2 is movably connected to the other input terminal of the variable gain amplifier 13.

[0058] In some embodiments, such as Figure 8 As shown, the impedance adjustment circuit 16 also includes a third resistor R3, which is connected between the two output terminals of the differential current signal output circuit 12. One end of the third resistor R3 is connected to one output terminal of the differential current signal output circuit 12, and the other end of the third resistor R3 is movably connected to the other output terminal of the differential current signal output circuit 12.

[0059] In some embodiments, the movable connection includes a connection via a switching element. For example, such as Figure 8 As shown, the other end of the first resistor R1 is connected to one input terminal of the variable gain amplifier 13 via switch S1. Specifically, the other end of the first resistor R1 is connected to one end of switch S1, and the other end of switch S1 is connected to one input terminal of the variable gain amplifier 13. Similarly, the other end of the second resistor R2 is connected to the other input terminal of the variable gain amplifier 13 via switch S2. Specifically, the other end of the second resistor R2 is connected to one end of switch S2, and the other end of switch S2 is connected to the other input terminal of the variable gain amplifier 13. Similarly, the other end of the third resistor R3 is connected to the other output terminal of the differential current signal output circuit 12 via switch S0. Specifically, the other end of the third resistor R3 is connected to one end of switch S0, and the other end of switch S0 is connected to the other output terminal of the differential current signal output circuit 12.

[0060] In some embodiments, the first resistor R1, the second resistor R2, and the third resistor R3 can be fixed resistors or adjustable resistors.

[0061] In some embodiments, during calibration, switches S1 and S2 are closed, connecting the output of the differential current signal output circuit 12 to the input of the variable gain amplifier 13, while switch S0 is open. Switch S0 can be closed when adjusting the impedance. After calibration, when the RF direct sampling receiving link is working normally, switches S1 and S2 are open, allowing the input of the RF direct sampling receiving link, i.e., the input of the variable gain amplifier 13, to receive RF signals for normal operation.

[0062] In some embodiments, the signal sources and impedances at the input terminal of the variable gain amplifier 13 are different when the on-chip calibration source circuit is on and off. When the on-chip calibration source circuit is working, the signal is generated by the on-chip calibration source circuit; when the on-chip calibration source circuit is not working, the signal is an external radio frequency signal. Therefore, it is necessary to ensure good phase consistency in these two situations to facilitate subsequent phase calibration. During calibration, the impedance at the input terminal of the variable gain amplifier 13 can be adjusted through the impedance adjustment circuit 16, thereby improving the phase error calibration effect of the variable gain amplifier and improving the phase consistency when the calibration source is on and off.

[0063] In some embodiments, the clock signal output circuit 11 includes a digital phase locked loop (DPLL) circuit.

[0064] Figure 9 This diagram illustrates a block diagram of another on-chip calibration source circuit provided in an embodiment of this application. In some embodiments, such as... Figure 9 As shown, in order to enhance the driving capability and quality of the clock signal, a buffer circuit 17 and a duty cycle corrector (DCC) circuit 18 are connected between the clock signal output circuit 11 and the differential current signal output circuit 12. The buffer circuit 17 is configured to receive and store the clock signal output by the clock signal output circuit 11. The duty cycle corrector circuit 18 is configured to receive the clock signal from the buffer circuit 17, adjust the duty cycle of the clock signal, and output the adjusted clock signal to the differential current signal output circuit 12.

[0065] In some embodiments, to enhance the quality of the clock signal and ensure its stability, such as Figure 9 As shown, a latch circuit 19 is also connected between the duty cycle correction circuit 18 and the differential current signal output circuit 11; the latch circuit 19 is configured to receive and buffer the adjusted clock signal from the duty cycle correction circuit, and to output the adjusted clock signal to the differential current signal output circuit 12.

[0066] In some embodiments, the on-chip calibration source circuitry also includes a power supply module (not shown) for providing the required operating voltage to all circuit modules and the required current to the differential current signal output circuitry 11, the magnitude of which can be adjusted by changing the register configuration.

[0067] In some embodiments, the power module may include, but is not limited to, a low-dropout regulator (LDO), a current mirror, etc.

[0068] This application also provides a chip, which includes an RF direct sampling receiver link and an on-chip calibration source circuit. The RF direct sampling receiver link includes a variable gain amplifier and a time-interleaved analog-to-digital converter. The on-chip calibration source circuit includes the on-chip calibration source circuit provided in the above embodiments.

[0069] This application also provides a communication device, including the chip described above.

[0070] For details regarding the on-chip calibration source circuit, please refer to the specific description of the on-chip calibration source circuit in the above embodiments, which will not be repeated here.

[0071] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. An on-chip calibration source circuit for a radio frequency direct sampling receiver link, the radio frequency direct sampling receiver link including a variable gain amplifier and a time-interleaved analog-to-digital converter, the on-chip calibration source circuit comprising: The circuit includes a clock signal output circuit and a differential current signal output circuit. The output terminal of the clock signal output circuit is connected to the input terminal of the differential current signal output circuit. The output terminal of the differential current signal output circuit is movably connected to the input terminal of the variable gain amplifier. The output terminal of the variable gain amplifier is connected to the input terminal of the time-interleaved analog-to-digital converter. The clock signal output circuit is used to output a clock signal to the differential current signal output circuit; The differential current signal output circuit is used to generate a first calibration signal according to the input clock signal and output the first calibration signal to the variable gain amplifier. The first calibration signal is a differential current signal. The first calibration signal is used to perform error calibration on the variable gain amplifier; The variable gain amplifier is used to output a second calibration signal to the time-interleaved analog-to-digital converter based on the first calibration signal, wherein the second calibration signal is a voltage signal. The second calibration signal is used to perform error calibration on the time-interleaved analog-to-digital converter.

2. The on-chip calibration source circuit according to claim 1, wherein, The clock signal is a differential clock signal, which includes a first clock signal and a second clock signal; the first calibration signal includes a first differential current signal and a second differential current signal. The differential current signal output circuit includes at least one set of differential current driving circuits, and each set of differential current driving circuits includes a first output circuit and a second output circuit. The first output circuit is configured to generate the first differential current signal based on the first clock signal and the second clock signal, and the second output circuit is configured to generate the second differential current signal based on the second clock signal and the first clock signal.

3. The on-chip calibration source circuit according to claim 2, wherein, The first output circuit includes a first transistor and a second transistor; The control electrode of the first transistor is connected to the output terminal of the clock signal output circuit that outputs the first clock signal; the first electrode of the first transistor is connected to the first power supply terminal; the second electrode of the first transistor is connected to the first output terminal of the differential current signal output circuit. The control electrode of the second transistor is connected to the output terminal of the clock signal output circuit that outputs the second clock signal; the first electrode of the second transistor is connected to the second power supply terminal; and the second electrode of the second transistor is connected to the first output terminal of the differential current signal output circuit.

4. The on-chip calibration source circuit according to claim 2, wherein, The second output circuit includes a third transistor and a fourth transistor; The control electrode of the third transistor is connected to the output terminal of the clock signal output circuit that outputs the second clock signal; the first electrode of the third transistor is connected to the first power supply terminal; the second electrode of the third transistor is connected to the second output terminal of the differential current signal output circuit. The control electrode of the fourth transistor is connected to the output terminal of the clock signal output circuit that outputs the first clock signal; the first electrode of the fourth transistor is connected to the second power supply terminal; and the second electrode of the fourth transistor is connected to the second output terminal of the differential current signal output circuit.

5. The on-chip calibration source circuit according to claim 3 or 4, wherein, Each group of differential current drive circuits also includes a common-mode feedback circuit; The common-mode feedback circuit includes an operational amplifier. The output terminal of the operational amplifier is connected to a first power supply terminal, the first input terminal is a reference voltage terminal, and the second input terminal is connected to the first and second output terminals of the differential current signal output circuit through a resistor.

6. The on-chip calibration source circuit according to claim 2, wherein, The differential current signal output circuit includes multiple differential current driving circuits. During each error calibration, the output terminal of the clock signal output circuit is connected to one of the differential current driving circuits of the differential current signal output circuit. The multiple differential current drive circuits correspond to different frequencies of the input clock signals, and the output current signals of the multiple differential current drive circuits correspond to different magnitudes.

7. The on-chip calibration source circuit according to claim 1, wherein, An impedance adjustment circuit is also connected between the differential current signal output circuit and the variable gain amplifier. The differential current signal output circuit has two output terminals, and the variable gain amplifier has two input terminals. The impedance adjustment circuit includes a first resistor and a second resistor. One end of the first resistor is connected to one output terminal of the differential current signal output circuit, and the other end of the first resistor is movably connected to one input terminal of the variable gain amplifier. One end of the second resistor is connected to the other output terminal of the differential current signal output circuit, and the other end of the second resistor is movably connected to the other input terminal of the variable gain amplifier.

8. The on-chip calibration source circuit according to claim 7, wherein, The impedance adjustment circuit further includes a third resistor, which is connected between the two output terminals of the differential current signal output circuit. One end of the third resistor is connected to one output terminal of the differential current signal output circuit, and the other end of the third resistor can be movably connected to the other output terminal of the differential current signal output circuit.

9. The on-chip calibration source circuit according to claim 7 or 8, wherein, The movable connection includes a connection via a switch.

10. The on-chip calibration source circuit according to claim 1, wherein, The clock signal output circuit includes a digital loop-locked phase circuit.

11. The on-chip calibration source circuit according to claim 1, wherein, A buffer circuit and a duty cycle correction circuit are also connected between the clock signal output circuit and the differential current signal output circuit. The buffer circuit is configured to receive and store the clock signal output by the clock signal output circuit; The duty cycle correction circuit is configured to receive the clock signal from the buffer circuit, adjust the duty cycle of the clock signal, and output the adjusted clock signal to the differential current signal output circuit.

12. The on-chip calibration source circuit according to claim 11, wherein, A latch circuit is also connected between the duty cycle correction circuit and the differential current signal output circuit. The latch circuit is configured to receive and buffer the adjusted clock signal from the duty cycle correction circuit, and to output the adjusted clock signal to the differential current signal output circuit.

13. A chip comprising a radio frequency direct sampling receiver link and an on-chip calibration source circuit, wherein the radio frequency direct sampling receiver link comprises a variable gain amplifier and a time-interleaved analog-to-digital converter, and the on-chip calibration source circuit comprises the on-chip calibration source circuit as claimed in any one of claims 1-12.

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