Circuit board manufacturing methods and circuit boards

Abstract

This application discloses a method for fabricating a circuit board and the circuit board itself. The method includes: obtaining a multilayer copper foil comprising a first copper foil layer and a second copper foil layer; wherein the first copper foil layer includes a first surface and a second surface disposed opposite to each other, a groove is provided on the first surface, and the second copper foil layer is disposed in the groove; pressing the multilayer copper foil together with a substrate to be processed to obtain a substrate to be processed; wherein the outer surface of the substrate to be processed is the second surface of the first copper foil layer; sequentially performing drilling, electroplating, and surface pattern preparation on the outer surface of the substrate to be processed; wherein, along the thickness direction of the substrate to be processed, the orthographic projection of the drilling area and the surface pattern area does not overlap with the orthographic projection of the second copper foil layer; removing the first copper foil layer covering the second copper foil layer; and fabricating a high-speed circuit pattern on the exposed second copper foil layer. This application can improve the copper thickness uniformity of the high-speed circuit pattern, thereby improving the impedance control accuracy of the surface circuit.

Description

Technical Field

[0001] This application relates to the field of circuit board processing technology, and in particular to methods for preparing circuit boards and circuit boards themselves. Background Technology

[0002] A printed circuit board (PCB) is a carrier that holds electronic components and provides electrical connections for them. With the continuous development of electronic technology, the requirements for signal transmission quality and speed in PCB products are constantly increasing.

[0003] Currently, with the widespread adoption of 5G networks, extremely high precision is required for high-speed PCB circuitry to meet the demands of 5G communication. In related technologies, the dielectric thickness and copper thickness of the inner PCB core board are fixed, making impedance processing relatively easy to control. However, the surface layer circuitry (i.e., outer layer circuitry) often exhibits inconsistent copper thickness across different locations due to electroplating, leading to lower impedance processing precision.

[0004] However, under high-speed transmission, the copper thickness fluctuation of the outer layer of the PCB has a great impact on circuit control and signal integrity. Uneven copper thickness may directly lead to impedance mismatch of the circuit, thus making it difficult for the PCB to meet the requirements of high-frequency and high-speed products. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a method for manufacturing a circuit board and the circuit board itself, which can solve the problem that related technologies cannot improve the impedance control accuracy of the circuit board.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted in this application is to provide a method for manufacturing a circuit board, comprising: obtaining a multilayer copper foil including a first copper foil layer and a second copper foil layer; wherein the first copper foil layer includes a first surface and a second surface disposed opposite to each other, a groove is provided on the first surface, and the second copper foil layer is disposed in the groove; pressing the multilayer copper foil together with a board to be processed to obtain a board to be processed; wherein the outer surface of the board to be processed is the second surface of the first copper foil layer; sequentially performing drilling, electroplating, and surface pattern preparation on the outer surface of the board to be processed; wherein, along the thickness direction of the board to be processed, the orthographic projection of the drilling area and the surface pattern area does not overlap with the orthographic projection of the second copper foil layer; removing the first copper foil layer covering the second copper foil layer; and preparing a high-speed circuit pattern on the exposed second copper foil layer.

[0007] The step of obtaining a multilayer copper foil including a first copper foil layer and a second copper foil layer includes: obtaining a first copper foil and a second copper foil; wherein the first copper foil includes a first surface and a second surface disposed opposite to each other, and the thickness of the first copper foil is greater than the thickness of the second copper foil; processing a groove on the first surface of the first copper foil based on the size and thickness of the second copper foil; embedding the second copper foil into the groove to obtain a multilayer copper foil.

[0008] The step of processing a groove on the first surface of the first copper foil based on the size and thickness of the second copper foil includes: attaching a dry film to the first surface and the second surface of the first copper foil; exposing and developing the dry film attached to the first surface based on a mask adapted to the size of the second copper foil to remove the dry film in a set area; performing micro-etching on the first copper foil to form a groove with a preset depth in the set area; wherein the preset depth is equal to the thickness of the second copper foil; and removing the remaining dry film on the first surface and the dry film on the second surface.

[0009] The step of pressing multiple layers of copper foil together with the substrate to be processed to obtain the substrate to be processed includes: stacking multiple layers of copper foil, prepreg and the substrate to be processed in sequence, and performing hot pressing curing, so that the second copper foil layer and the first surface of the first copper foil layer are bonded to the substrate to be processed through the prepreg.

[0010] The process of pressing multiple layers of copper foil together with the substrate to be processed to obtain the substrate to be processed includes: performing micro-etching treatment on the outer surface of the substrate to be processed, and ensuring that the thickness of the first copper foil layer after micro-etching treatment is still greater than the thickness of the second copper foil layer; and performing drilling, electroplating and surface pattern preparation sequentially on the outer surface of the substrate to be processed, including: performing drilling, electroplating and surface pattern preparation sequentially on the outer surface of the substrate to be processed after micro-etching treatment.

[0011] The thickness of the first copper foil is 1.3 to 1.35 times the thickness of the second copper foil. The step of performing micro-etching treatment on the outer surface of the substrate to be treated, and ensuring that the thickness of the first copper foil layer after micro-etching treatment is still greater than the thickness of the second copper foil layer, includes: performing micro-etching treatment on the outer surface of the substrate to be treated, and ensuring that the thickness of the thinned copper layer is less than or equal to 0.2 times the thickness of the second copper foil layer.

[0012] The process includes drilling, electroplating, and surface pattern preparation sequentially on the outer surface of the substrate after micro-etching. Then, the first copper foil layer located at the edge of the second copper foil layer is etched to separate the first copper foil layer covering the second copper foil layer from the remaining first copper foil layers bonded to the substrate.

[0013] The step of removing the first copper foil layer covering the second copper foil layer includes: peeling off the first copper foil layer covering the second copper foil layer to expose the second copper foil layer.

[0014] The step of preparing a high-speed circuit pattern on the exposed second copper foil layer includes: forming a solder resist layer on the outer surface of the board material on which the high-speed circuit pattern is provided, to obtain a circuit board.

[0015] To solve the above-mentioned technical problems, the second technical solution adopted in this application is to provide a circuit board, which is manufactured by the above-mentioned circuit board preparation method; wherein, the circuit board includes a high-speed circuit pattern.

[0016] The beneficial effects of this application are as follows: Unlike the prior art, this application provides a method for preparing a circuit board and a circuit board. By obtaining a multilayer copper foil including a first copper foil layer and a second copper foil layer, and setting the second copper foil layer in a groove located on the first surface of the first copper foil layer, and when pressing the multilayer copper foil with the board to be processed, making the outer surface of the board to be processed the second surface of the first copper foil layer, a closed space can be formed between the groove of the first copper foil layer and the board to be processed, thereby protecting the second copper foil layer. Then, drilling, electroplating, and surface pattern preparation are sequentially performed on the outer surface of the board to be processed. Along the thickness direction of the board to be processed, the orthographic projection of the drilling area and the surface pattern area is made to not overlap with the orthographic projection of the second copper foil layer. After drilling, electroplating, and surface pattern preparation are completed, the first copper foil layer covering the second copper foil layer is removed, and high-speed circuit patterns are prepared on the exposed second copper foil layer. This can reduce the impact of drilling, electroplating, and surface pattern preparation processes on the second copper foil layer, thereby improving the copper thickness uniformity of the high-speed circuit pattern, improving the impedance control accuracy of the surface circuit, and thus improving the product yield of the circuit board to meet the needs of high-frequency and high-speed products. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of the first embodiment of the method for manufacturing the circuit board of this application;

[0019] Figure 2 This is a schematic flowchart of the second embodiment of the method for manufacturing the circuit board of this application;

[0020] Figure 3 This is a schematic diagram of the structure of one embodiment of the multilayer copper foil obtained in S203;

[0021] Figure 4This is a schematic diagram of the structure of the plate material to be processed obtained in S204 according to one embodiment;

[0022] Figure 5 This is a schematic diagram of the structure of the plate material to be processed obtained in S207 according to one embodiment;

[0023] Figure 6 This is a schematic diagram of the structure of the plate material to be processed obtained in S208 according to one embodiment;

[0024] Figure 7 This is a schematic diagram of the structure of the plate material to be processed obtained in S209 according to one embodiment;

[0025] Figure 8 This is a schematic diagram of one embodiment of the circuit board of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0028] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0029] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0030] Currently, with the massive increase in data throughput driven by the growth of the AI ​​industry, high-speed signal transmission rates have already exceeded 112Gbps, and may even reach 224Gbps in the future. To meet the stringent requirement of 5G communication for amplitude variation ≤1.0dB, the impedance tolerance of high-speed PCBs needs to be compressed from ±10% to ±5%. Under this scenario, the impedance matching of arbitrary traces on the PCB board faces severe challenges.

[0031] In related technologies, the dielectric thickness and copper thickness of the inner core board of a PCB are fixed, making impedance processing relatively easy to control. However, the outermost layer of the PCB, due to electroplating, often exhibits inconsistent copper thickness across different locations, leading to lower impedance processing accuracy. Furthermore, the copper thickness increase at different locations on the outermost layer of the PCB, also due to electroplating, results in inconsistent impedance processing accuracy.

[0032] However, under high-speed transmission, the copper thickness fluctuation of the outer layer of the PCB has a great impact on circuit control and signal integrity. Uneven copper thickness may directly lead to impedance mismatch (a fluctuation of ±10% in the total thickness of the base copper and the copper plating can cause an impedance deviation of ±1.5Ω), which in turn causes problems such as signal reflection, increased attenuation and eye diagram closure, making it difficult for the PCB to meet the needs of high-frequency and high-speed products.

[0033] Based on the above, this application provides a method for manufacturing a circuit board and a circuit board, which can solve the problem that related technologies cannot improve the impedance control accuracy of circuit boards.

[0034] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] Please see Figure 1 , Figure 1 This is a schematic flowchart of the first embodiment of the method for fabricating the circuit board according to this application. In this embodiment, the fabrication method includes:

[0036] S11: Obtain a multilayer copper foil including a first copper foil layer and a second copper foil layer; wherein, the first copper foil layer includes a first surface and a second surface disposed opposite to each other, a groove is provided on the first surface, and the second copper foil layer is disposed in the groove.

[0037] In this embodiment, the second copper foil layer is directly embedded in the groove, and no adhesive is provided between the second copper foil layer and the groove.

[0038] In this embodiment, the first copper foil layer is a thick copper foil, the second copper foil layer is a copper foil used to prepare high-speed traces, and the thickness of the second copper foil layer is less than the thickness of the first copper foil layer.

[0039] The thickness of the second copper foil layer is calculated based on the surface impedance requirement.

[0040] In this embodiment, the size of the groove is equal to or slightly larger than the size of the second copper foil layer, so that the second copper foil layer can be embedded in the groove.

[0041] In some implementations, the depth of the groove is equal to the thickness of the second copper foil layer, so that the side surface of the second copper foil layer facing away from the bottom of the groove is at the same height as the first surface of the first copper foil layer.

[0042] In other embodiments, the depth of the groove is slightly greater than or slightly less than the thickness of the second copper foil layer to reduce the difficulty of processing the groove.

[0043] S12: Press multiple layers of copper foil together with the substrate to be processed to obtain the substrate to be processed; wherein, the outer surface of the substrate to be processed is the second surface of the first copper foil layer.

[0044] In this embodiment, the surface of the multilayer copper foil in which the second copper foil layer is disposed (that is, the first surface of the first copper foil layer) is pressed together with the plate to be processed, so that the outer surface of the obtained processed plate is the second surface of the first copper foil layer.

[0045] In some embodiments, the substrate to be processed is bonded to the side surface of the second copper foil layer opposite to the bottom of the groove and the first surface of the first copper foil layer using a prepreg.

[0046] The second copper foil layer has a high adhesion to the substrate on the side facing away from the bottom of the groove, and the first surface of the first copper foil layer has a high adhesion to the substrate.

[0047] Understandably, by making the outer surface of the substrate to be processed the second surface of the first copper foil layer, a closed space can be formed between the groove of the first copper foil layer and the substrate to be processed, thereby protecting the second copper foil layer.

[0048] In some embodiments, the material to be processed is a multilayer core board obtained by lamination, wherein a prepreg is disposed between the core boards.

[0049] S13: Drilling, electroplating, and surface pattern preparation are performed sequentially on the outer surface of the substrate to be treated; wherein, along the thickness direction of the substrate to be treated, the orthographic projection of the drilling area and the surface pattern area does not overlap with the orthographic projection of the second copper foil layer.

[0050] In this embodiment, through holes are first drilled in a predetermined area on the outer surface of the substrate to be treated. Along the thickness direction of the substrate, the orthographic projection of the predetermined area does not overlap with the orthographic projection of the second copper foil layer.

[0051] Understandably, the orthographic projection of the preset area does not overlap with the orthographic projection of the second copper foil layer, which can avoid drilling holes in the second copper foil layer and thus avoid affecting the copper thickness consistency of the second copper foil layer.

[0052] In some implementations, the number of vias is set according to actual needs.

[0053] In some embodiments, the number of vias is one. In other embodiments, the number of vias is at least two. In still other embodiments, the number of vias may be three, five, or more, and this application does not limit this.

[0054] In some embodiments, holes are drilled in a predetermined area of ​​the material to be treated using mechanical drilling. In other embodiments, holes are drilled in the predetermined area of ​​the material to be treated using laser drilling; this application is not limited to either method.

[0055] In some embodiments, the via is a through hole. In other embodiments, the via is a blind hole. In still other embodiments, the via includes both through holes and blind holes; this application does not limit the specific embodiment.

[0056] In this embodiment, after drilling is completed, the entire board of material to be treated is electroplated to perform hole metallization treatment on the through holes.

[0057] Understandably, since the second copper foil layer is enclosed within the groove and the substrate to be processed, the electroplating process will not affect the second copper foil layer.

[0058] In this embodiment, a surface pattern is prepared on the outer surface of the substrate to be treated after electroplating. Along the thickness direction of the substrate, the orthographic projection of the surface pattern area does not overlap with the orthographic projection of the second copper foil layer.

[0059] Understandably, the orthographic projection of the surface pattern area does not overlap with the orthographic projection of the second copper foil layer, which can avoid etching the second copper foil layer and thus avoid affecting the copper thickness consistency of the second copper foil layer.

[0060] In some implementations, the surface pattern includes pads and copper plating.

[0061] S14: Remove the first copper foil layer covering the second copper foil layer.

[0062] In this embodiment, since no adhesive is provided between the second copper foil layer and the groove, there is no adhesion or the adhesion is small between the second copper foil layer and the first copper foil layer covering the second copper foil layer. The first copper foil layer covering the second copper foil layer can be directly removed by peeling.

[0063] Understandably, since the surface drilling process, electroplating process, and other surface fabrication processes except for high-speed graphic circuits are all completed when the second copper foil layer is protected, the above processes will not affect the copper thickness consistency of the second copper foil layer. That is, after removing the first copper foil layer covering the second copper foil layer, the copper thickness at different locations of the second copper foil layer is the same, and the copper thickness consistency is extremely high.

[0064] S15: Fabricate a high-speed circuit pattern on the exposed second copper foil layer.

[0065] Understandably, because the copper thickness of the exposed second copper foil layer is extremely uniform, the copper thickness uniformity of the prepared high-speed circuit pattern is high, which can greatly reduce the difficulty of surface impedance control.

[0066] Unlike related technologies, this embodiment obtains a multilayer copper foil comprising a first copper foil layer and a second copper foil layer, and places the second copper foil layer in a groove located on the first surface of the first copper foil layer. During the lamination of the multilayer copper foil with the substrate to be processed, the outer surface of the resulting substrate is the second surface of the first copper foil layer. This allows the groove of the first copper foil layer to form a closed space with the substrate, thereby protecting the second copper foil layer. Drilling, electroplating, and surface pattern preparation are then sequentially performed on the outer surface of the substrate. Along the thickness direction of the substrate, the orthographic projections of the drilled area and the surface pattern area do not overlap with the orthographic projection of the second copper foil layer. After drilling, electroplating, and surface pattern preparation are completed, the first copper foil layer covering the second copper foil layer is removed, and high-speed circuit patterns are prepared on the exposed second copper foil layer. This reduces the impact of drilling, electroplating, and surface pattern preparation processes on the second copper foil layer, improving the copper thickness uniformity of the high-speed circuit patterns, thereby increasing the impedance control accuracy of the surface circuits and ultimately improving the product yield of the circuit board to meet the needs of high-frequency and high-speed products.

[0067] Please see Figure 2 , Figure 2 This is a schematic flowchart of a second embodiment of the method for fabricating the circuit board according to this application. In this embodiment, the fabrication method includes:

[0068] S201: Obtain a first copper foil and a second copper foil; wherein the first copper foil includes a first surface and a second surface disposed opposite to each other, and the thickness of the first copper foil is greater than the thickness of the second copper foil.

[0069] In this embodiment, the thickness of the second copper foil layer is calculated based on the surface impedance requirement.

[0070] In this embodiment, the thickness of the first copper foil is 1.3 to 1.35 times the thickness of the second copper foil.

[0071] In some specific embodiments, if the second copper foil layer is 20 μm thick, then the thickness of the first copper foil layer is 26 μm to 27 μm. In other specific embodiments, if the second copper foil layer is 35 μm thick, then the thickness of the first copper foil layer is greater than or equal to 45.5 μm to 47.25 μm.

[0072] S202: Based on the dimensions and thickness of the second copper foil, a groove is machined on the first surface of the first copper foil.

[0073] In this embodiment, a dry film is attached to a first surface and a second surface of a first copper foil. The dry film attached to the first surface is exposed and developed using a mask adapted to the size of the second copper foil to remove the dry film in a designated area. The first copper foil is micro-etched to form a groove with a predetermined depth in the designated area; wherein the predetermined depth is equal to the thickness of the second copper foil. The remaining dry film on the first surface and the dry film on the second surface are then removed.

[0074] S203: Embed the second copper foil into the groove to obtain multilayer copper foil.

[0075] Specifically, please refer to Figure 3 , Figure 3 This is a schematic diagram of one embodiment of the multilayer copper foil obtained in S203.

[0076] In this embodiment, the multilayer copper foil includes a first copper foil layer 10 and a second copper foil layer 20. The first copper foil layer 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. A groove 103 is provided on the first surface 101, and the second copper foil layer 20 is disposed in the groove 103.

[0077] S204: Pressing multiple layers of copper foil together with the substrate to be processed to obtain the substrate to be processed; wherein, the outer surface of the substrate to be processed is the second surface of the first copper foil layer.

[0078] In this embodiment, multiple layers of copper foil, prepreg, and the substrate to be processed are stacked sequentially and then hot-pressed and cured so that the second copper foil layer and the first surface of the first copper foil layer are bonded together with the substrate to be processed through the prepreg.

[0079] Understandably, by making the outer surface of the substrate to be processed the second surface of the first copper foil layer, a closed space can be formed between the groove of the first copper foil layer and the substrate to be processed, thereby protecting the second copper foil layer.

[0080] Specifically, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the material to be processed obtained in S204 according to one embodiment.

[0081] In this embodiment, the substrate 100 to be processed includes multiple layers of copper foil and the substrate to be processed. The substrate to be processed includes multiple core boards 11, with a prepreg 12 disposed between adjacent core boards 11. The core board 11 includes a dielectric layer 13 and copper layers 14 disposed on both sides of the dielectric layer 13. The multiple copper foils include a first copper foil layer 10 and a second copper foil layer 20. The first copper foil layer 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. A groove 103 is disposed on the first surface 101, and the second copper foil layer 20 is disposed in the groove 103. The first surface 101 of the first copper foil layer 10 and the second copper foil layer 20 are bonded to the outermost core board 11 of the substrate to be processed by the prepreg 12, and one outer surface of the substrate to be processed is the second surface 102 of the first copper foil layer 10.

[0082] S205: Perform micro-etching on the outer surface of the substrate to be processed, and ensure that the thickness of the first copper foil layer after micro-etching is still greater than the thickness of the second copper foil layer.

[0083] In this embodiment, the outer surface of the substrate to be treated is subjected to micro-etching treatment, and the thickness of the thinned copper layer is less than or equal to 0.2 times the thickness of the second copper foil layer.

[0084] Understandably, the thickness of the first copper foil is 1.3 to 1.35 times the thickness of the second copper foil, and the thickness of the copper layer thinned from the first copper foil layer does not exceed 0.2 times the thickness of the second copper foil layer, so that the thinned first copper foil layer still covers the second copper foil layer, thereby providing protection for the second copper foil layer.

[0085] Understandably, by thinning the first copper foil layer, the difficulty of subsequent drilling and pattern preparation on the first copper foil layer can be reduced.

[0086] S206: Drilling, electroplating, and surface pattern preparation are performed sequentially on the outer surface of the substrate after micro-etching; wherein, along the thickness direction of the substrate, the orthographic projection of the drilling area and the surface pattern area does not overlap with the orthographic projection of the second copper foil layer.

[0087] In this embodiment, drilling, electroplating, and circuit pattern fabrication are performed sequentially on the second surface of the first copper foil layer after micro-etching.

[0088] Please refer to the description in S13 for the specific process, which will not be repeated here.

[0089] S207: Etch the first copper foil layer located at the edge of the second copper foil layer to separate the first copper foil layer covering the second copper foil layer from the remaining first copper foil layer bonded to the substrate to be processed.

[0090] Understandably, by etching the first copper foil layer located at the edge of the second copper foil layer, it is possible to separate the first copper foil layer covering the second copper foil layer from the first copper foil layer bonded to the substrate to be processed for forming the surface pattern.

[0091] Specifically, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of the material to be processed obtained in S207 according to one embodiment.

[0092] In this embodiment, the substrate 200 to be processed includes a multilayer core board 11, with a prepreg 12 disposed between adjacent core boards 11. Each core board 11 includes a dielectric layer 13 and copper layers 14 disposed on both sides of the dielectric layer 13. A second copper foil layer 20 and a surface pattern 30 are disposed on the substrate 200. The second copper foil layer 20 and the surface pattern 30 are bonded to the outermost core board 11 via the prepreg 12. The surface of the second copper foil layer 20 facing away from the prepreg 12 is covered with a first copper foil layer 10. The substrate 200 to be processed includes at least one metallized through-hole 40.

[0093] S208: Strip the first copper foil layer covering the second copper foil layer to expose the second copper foil layer.

[0094] In this embodiment, since no adhesive is provided between the second copper foil layer and the groove, there is no adhesion or very weak adhesion between the second copper foil layer and the first copper foil layer covering the second copper foil layer. Simultaneously, since the first copper foil layer covering the second copper foil layer is separated from the first copper foil layer bonded to the substrate for forming the surface pattern, the first copper foil layer covering the second copper foil layer can be directly removed by peeling.

[0095] Understandably, since the surface drilling process, electroplating process, and other surface fabrication processes except for high-speed graphic circuits are all completed when the second copper foil layer is protected, the above processes will not affect the copper thickness consistency of the second copper foil layer. That is, after removing the first copper foil layer covering the second copper foil layer, the copper thickness at different locations of the second copper foil layer is the same, and the copper thickness consistency is extremely high.

[0096] Specifically, please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of the material to be processed obtained in S208 according to one embodiment.

[0097] In this embodiment, the substrate 300 to be processed includes a multilayer core board 11, with a prepreg 12 disposed between adjacent core boards 11. Each core board 11 includes a dielectric layer 13 and copper layers 14 disposed on both sides of the dielectric layer 13. A second copper foil layer 20 and a surface pattern 30 are disposed on one side surface of the substrate 300. The second copper foil layer 20 and the surface pattern 30 are bonded to the outermost core board 11 by the prepreg 12. The substrate 300 to be processed includes at least one metallized through-hole 40.

[0098] S209: Fabricate a high-speed circuit pattern on the exposed second copper foil layer.

[0099] Specifically, please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of the material to be processed obtained in S209 according to one embodiment.

[0100] In this embodiment, the substrate 400 to be processed includes a multilayer core board 11, with a prepreg 12 disposed between adjacent core boards 11. Each core board 11 includes a dielectric layer 13 and copper layers 14 disposed on both sides of the dielectric layer 13. A high-speed circuit pattern 50 and a surface pattern 30 are disposed on the substrate 400, and the high-speed circuit pattern 50 and the surface pattern 30 are bonded to the outermost core board 11 by the prepreg 12. The substrate 400 to be processed includes at least one metallized through-hole 40.

[0101] S210: A solder resist layer is formed on the outer surface of the board material to be processed, which has a high-speed circuit pattern, to obtain a circuit board.

[0102] Understandably, by forming a solder resist layer on the outer surface of the board material to be processed, where high-speed circuit patterns are set, the high-speed circuit patterns and surface patterns can be protected by the solder resist layer, thereby improving the reliability and stability of the circuit board.

[0103] Specifically, please refer to Figure 8 , Figure 8 This is a schematic diagram of one embodiment of the circuit board of this application.

[0104] In this embodiment, the circuit board 500 includes a multilayer core board 11, with a prepreg 12 disposed between adjacent core boards 11. Each core board 11 includes a dielectric layer 13 and copper layers 14 disposed on both sides of the dielectric layer 13. The circuit board 500 has a high-speed circuit pattern 50 and a surface pattern 30, which are bonded to the outermost core board 11 by the prepreg 12. A solder resist layer 60 is disposed on the surface of the high-speed circuit pattern 50 and the surface pattern 30 facing away from the prepreg 12. The circuit board 500 includes at least one metallized via 40.

[0105] Unlike related technologies, this application obtains a multilayer copper foil comprising a first copper foil layer and a second copper foil layer, and places the second copper foil layer in a groove located on the first surface of the first copper foil layer. During the lamination of the multilayer copper foil with the substrate to be processed, the outer surface of the resulting substrate is the second surface of the first copper foil layer. This allows the groove of the first copper foil layer to form a closed space with the substrate, thereby protecting the second copper foil layer. Drilling, electroplating, and surface patterning are then sequentially performed on the outer surface of the substrate. Along the thickness direction of the substrate, the orthographic projections of the drilled area and the surface pattern area do not overlap with the orthographic projection of the second copper foil layer. After drilling, electroplating, and surface patterning are completed, the first copper foil layer covering the second copper foil layer is removed, and high-speed circuit patterns are fabricated on the exposed second copper foil layer. This reduces the impact of drilling, electroplating, and surface patterning processes on the second copper foil layer, improving the copper thickness uniformity of the high-speed circuit patterns, thereby increasing the impedance control accuracy of the surface circuits and ultimately improving the product yield of the circuit board to meet the needs of high-frequency and high-speed products.

[0106] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: A multilayer copper foil including a first copper foil layer and a second copper foil layer is obtained; wherein, the first copper foil layer includes a first surface and a second surface disposed opposite to each other, a groove is provided on the first surface, and the second copper foil layer is disposed in the groove; The multilayer copper foil is pressed together with the substrate to be processed to obtain the substrate to be processed; wherein, the outer surface of the substrate to be processed is the second surface of the first copper foil layer; Drilling, electroplating, and surface pattern preparation are sequentially performed on the outer surface of the substrate to be processed; wherein, along the thickness direction of the substrate to be processed, the orthographic projections of the drilled area and the surface pattern area do not overlap with the orthographic projection of the second copper foil layer; Remove the first copper foil layer that covers the second copper foil layer; High-speed circuit patterns are fabricated on the exposed second copper foil layer.

2. The method for manufacturing a circuit board according to claim 1, characterized in that, The step of obtaining a multilayer copper foil including a first copper foil layer and a second copper foil layer includes: A first copper foil and a second copper foil are obtained; wherein, the first copper foil includes a first surface and a second surface disposed opposite to each other, and the thickness of the first copper foil is greater than the thickness of the second copper foil; The groove is machined on the first surface of the first copper foil based on the size and thickness of the second copper foil; The second copper foil is embedded into the groove to obtain the multilayer copper foil.

3. The method for manufacturing a circuit board according to claim 2, characterized in that, The step of machining the groove on the first surface of the first copper foil based on the dimensions and thickness of the second copper foil includes: A dry film is attached to the first surface and the second surface of the first copper foil; The dry film attached to the first surface is exposed and developed based on a mask adapted to the size of the second copper foil to remove the dry film in a set area. The first copper foil is subjected to micro-etching to form a groove with a preset depth in the designated area; wherein the preset depth is equal to the thickness of the second copper foil; Remove the remaining dry film on the first surface and the dry film on the second surface.

4. The method for manufacturing a circuit board according to claim 1, characterized in that, The step of pressing the multilayer copper foil together with the substrate to be processed to obtain the substrate includes: The multilayer copper foil, the prepreg, and the substrate to be processed are stacked sequentially and then hot-pressed and cured to bond the second copper foil layer and the first surface of the first copper foil layer to the substrate to be processed through the prepreg.

5. The method for manufacturing a circuit board according to claim 1, characterized in that, After the step of pressing the multilayer copper foil together with the substrate to be processed to obtain the substrate to be processed, the following steps are included: The outer surface of the plate to be processed is subjected to micro-etching treatment, and the thickness of the first copper foil layer after micro-etching treatment is still greater than the thickness of the second copper foil layer. The steps of sequentially drilling, electroplating, and surface pattern preparation on the outer surface of the substrate to be treated include: Drilling, electroplating, and surface pattern preparation are performed sequentially on the outer surface of the substrate after micro-etching.

6. The method for manufacturing a circuit board according to claim 5, characterized in that, The thickness of the first copper foil is 1.3 to 1.35 times the thickness of the second copper foil; The step of performing micro-etching treatment on the outer surface of the substrate to be treated, and ensuring that the thickness of the first copper foil layer after micro-etching treatment is still greater than the thickness of the second copper foil layer, includes: The outer surface of the substrate to be treated is subjected to micro-etching, and the thickness of the thinned copper layer is less than or equal to 0.2 times the thickness of the second copper foil layer.

7. The method for manufacturing a circuit board according to claim 6, characterized in that, After the steps of drilling, electroplating, and surface pattern preparation are performed sequentially on the outer surface of the substrate after micro-etching, the process includes: The first copper foil layer located at the edge of the second copper foil layer is etched to separate the first copper foil layer covering the second copper foil layer from the remaining first copper foil layer bonded to the substrate to be processed.

8. The method for manufacturing a circuit board according to claim 7, characterized in that, The step of removing the first copper foil layer covering the second copper foil layer includes: The first copper foil layer covering the second copper foil layer is peeled off to expose the second copper foil layer.

9. The method for manufacturing a circuit board according to claim 1, characterized in that, After the step of fabricating a high-speed circuit pattern on the exposed second copper foil layer, the method includes: A solder resist layer is formed on the outer surface of the substrate to be processed, on which the high-speed circuit pattern is provided, to obtain the circuit board.

10. A circuit board, characterized in that, The circuit board is manufactured by the method for preparing a circuit board according to any one of claims 1 to 9; wherein the circuit board includes a high-speed circuit pattern.

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